SI3480-A01-GMR

Si3480 Si3480 P OWER M ANAGEMENT C O N T R O L L E R Features Enables use of a smaller power  Pin programmable for overall supply for a 4 or 8 port PoE power supply capacity, port system power level, port priority, and detection timing  Self-contained solution operates  LED indication of port status and without the need for a host for overall power consumption unmanaged operation No software required  20-pin Quad flat package No data isolation required (4x4 mm) 4x4 mm PCB footprint; RoHS  Fully compliant with IEEE 802.3 compliant clause 33 for Power over Ethernet including the 802.3at amendment  Extended operating temperature range (–40 to +85 °C) for higher power (30 W category 2 ports) N ot fo R r N ec o ew m m D e es nd ig e ns d  Ordering Information: See Ordering Guide on page 9. Pin Assignments Description SCL LEDBANK PWRCFG POECFG 18 17 16 VDD 3 13 LED8 RST 4 12 LED7 NC 5 11 LED6 7 8 9 10 LED5 ALTCFG LED4 PRIOCFG 14 LED3 15 2 LED2 1 LED1 SDA GND 6 The Si3480 power management controller is pin programmed. The pins are used to set the power supply capacity, the number of low power (category 1, 15.4 W), and high power (category 2, 30 W) ports, the port priority, and the detection timing (Alternative A or Alternative B). The Si3480 uses the real time overload and current monitoring capability of the Si3452 to manage power for up to eight ports. Power management is based on actual consumption rather than mere classification in order to supply power to the greatest number of ports. 19 The Si3452 is capable of delivering over 30 W per port, which means that, in a typical 8-port system, a 240 W power supply would have to be used to avoid overload. Typically, not all ports are used at full power; so, a smaller power supply in the range of 30 to 150 W can be used along with the Si3480 power management controller. 20 The Si3480 is a power manager intended for use with the Si3452 Power over Ethernet (PoE) controller. The Si3480 enables the use of a smaller, lower cost, and more efficiently-utilized power supply in an unmanaged PoE Power Sourcing Equipment (PSE) system. INT (Top View) The Si3480 also provides LED drive to indicate port status and drive an LED bar graph display to indicate the power supply capacity in use. If a port is denied power due to power supply capacity limitations, the LED indicators provide a simple and intuitive indication, helping a user recognize and correct the overload situation by rebalancing loads or adding mid-span power injectors to ports that would not otherwise be powered. In case of a port overload, the port is easily re-enabled by disconnecting the Powered Device (PD) and then reconnecting the PD after correcting the overload situation. Rev. 1.1 1/15 Copyright © 2015 by Silicon Laboratories Si3480 Si3480 Functional Block Diagram Configuration Pins Power Provided Port Power Port Priority Detection Timing Si3480 Power Management Controller Power Meter LEDs N ot fo R r N ec o ew m m D e es nd ig e ns d Port Status LEDs Si3452 PoE Controllers 2 Rev. 1.1 Si3480 TABLE O F C ONTENTS Section Page N ot fo R r N ec o ew m m D e es nd ig e ns d 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1. Device Initialization and Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2. I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.3. LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4. LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.1. Start-Up LED Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.2. Port Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.3. Power Meter LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8. Landing Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9. Top Marking: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Rev. 1.1 3 Si3480 1. Electrical Specifications Table 1. Recommended Operating Conditions Description Symbol Test Conditions Min Typ Max Units TA No airflow –40 — 85 °C VDD Supply Voltage VDD All operating modes 2.7 — 3.6 V LED Current ILED LEDBANK pin at 50% duty cycle — 20 — mA Min Typ Max Units Ambient Temperature under Bias –55 — 125 °C Storage Temperature –65 — 150 °C –0.3 — 5.8 V –0.3 — 4.2 V Maximum Total LED Current — — 500 mA Maximum LED Current per Pin — — 100 mA Operating Temperature Range Table 2. Absolute Maximum Ratings Conditions N ot fo R r N ec o ew m m D e es nd ig e ns d Parameter Voltage on any I/O with respect to GND VDD > 2.2 V Voltage on VDD with respect to GND Note: Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 3. Electrical Characteristics* Description Symbol Test Conditions Min Typ Max Units VIH RST, SCL, SDA, ALTCFG 2.0 — — V VIL RST, SCL, SDA, ALTCFG — — 0.8 V IIL RST, and all CFG pins SCL and SDA high — — ±1 µA Output Low (LED pins, SCL and SDA) VOL IOL = 8.5 mA IOL = 25 mA — — — 1.0 0.6 — V Output High (LED Pins) VOH IOH = –3 mA IOH = –10 mA — — — VDD–0.8 VDD–0.7 — V ∆VSENSE Percent of VDD –1.5 — +1.5 % IDD VDD = 3.0 V VDD = 3.6 V — — — — 10 13 mA Input High Input Low Input Leakage Current Sense Accuracy for Analog Configuration Pins VDD Current *Note: VDD = 2.7 to 3.6 V, –40 to 85 °C unless otherwise noted. 4 Rev. 1.1 R117 R113 R112 R115 R114 Status LEDs 13 12 11 10 17 16 15 14 LED8 LED7 LED6 LED5 6 7 8 9 1 20 19 18 Bank LED_1_5 LED_2_6 LED_3_7 LED_4_8 Q4 Q5 +3V3 1K R101 Si3500 RTN +1V1 +3V3 -52V->+3.3V Converter +3V3 R10310K R102 1K SW PUSHBUTTON Figure 1. Si3480 Typical Application Schematic Power Display LEDs LED1 LED2 LED3 LED4 SDA SCL INT LEDBANK VREF_IN Two Si3452 Controllers RESET_L SDA SCL INT HV Port Controllers N ot fo R r N ec o ew m m D e es nd ig e ns d R100 10K SW1 +3V3 3 VDD U101 Si3480 PWRCFG POECFG PRIOCFG ALTCFG GND 2 5 4 -52V_RTN +3V3 -52V_RTN NC RST -52V -52V C101 1uF +3V3_RTN R116 Bank LED_1_5 LED_2_6 LED_3_7 LED_4_8 -52V VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 RTN0 RTN1 RTN2 RTN3 RTN4 RTN5 RTN6 RTN7 POE_OUT PoE magnetics and connector VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 -52V +3V3 Si3480 2. Typical Application Schematic Rev. 1.1 5 Si3480 3. Functional Description 3.1. Device Initialization and Configuration Pins The Si3480 will discover Si3452 devices at addresses 0x20 and 0x21 at power up. If only one device is found, it will manage the power for four ports. If two devices are found, the Si3480 will manage power for eight ports. For the case of eight ports, ports 1–4 are associated with the Si3452 at address 0x20, and ports 5–8 are associated with device 0x21. After power-up, the CFG pins are measured to determine how power is to be managed. 3.1.1. Pin PWRCFG The voltage on pin PWRCFG specifies the power provided by the system power supply. The power provided is: PPROVIDED = 200 x VPWRCFG / VDD (Watts) N ot fo R r N ec o ew m m D e es nd ig e ns d The total power provided is the rating of the main power supply for continuous output. The amount of total power provided depends on the expected usage. 30 W of total power provided might be realistic for a four-port system that only supports 15.4 W per port and is not expected to have PDs on all ports. 150 W of total power might be realistic for an eight port system that supports 30 W per port and is expected to have category 2 PDs connected to all ports. To avoid overloads, a port will not be granted power unless the power consumed plus the power requested according to classification (4, 7, 15.4, or 30 W) allows for 15% power supply reserve. If, due to variation in power over time, the total power consumed by all the loads exceeds the power supply capacity, the power manager will shut down ports in priority order. 3.1.2. Pin POECFG The voltage on the POECFG pins determines how many ports are enabled for 30 W maximum per port. If the voltage is at ground, no ports will be enabled for 30 W maximum. If the voltage is at VDD, all ports are enabled for 30 W maximum. The number of ports enabled for 30 W is: N = 8 x VPOECFG / VDD rounded to the nearest integer In a four-port system, VPOECFG > VDD / 2 means that 30 W is enabled on all ports. If a port is enabled for 30 W maximum, special high-current Ethernet transformers should be used, and the user should be aware that the wiring to the PD should be category 5E or better or category 5 manufactured after 1995 (See 802.3 clause 33 for details). 3.1.3. Pin PRIOCFG The Si3452 implements a port priority set according to the voltage on pin PRIOCFG. Low priority ports may be turned off if a high priority port is requesting power. Also, low-priority ports are shut down before high-priority ports in case the power supply is overloaded. Similar to the POECFG pin, the number of ports that are high priority is: N = 8 x VPRIORITYCFG / VDD rounded to the nearest integer 3.1.4. Pin ALTCFG The Si3480 can be set to put the Si3452 parts in either Alternative A or Alternative B timing mode. Alternative A is used when the power is applied to wire pairs 1,2 and 3,6. Alternative B is used when the power is applied to wire pairs 4,5 and 7,8. Timing between detection pulses is less than 0.5 s for Alternative A and greater than two seconds for Alternative B. The timing is Alternative A if pin ALTCFG is tied low and Alternative B if the pin is tied high. 3.2. I2C Communication The open drain Si3480 pins (SDA, SCL, and INT) are for I2C communication and connect to the Si3452/53 pins with the same name. See the Si3452/53 data sheet for more detailed information. 3.3. LED Control The LED pins each connect to two LEDs. The LED being driven is determined by the LEDBANK pin in a normal multiplexing fashion. The LEDBANK pin is driven at 500 Hz (1 msec high and 1 ms low). 6 Rev. 1.1 Si3480 4. LEDs Upon power application or reset (by SW1 in the upper left corner), the Si3480 probes to see whether there are one or two Si3452 ICs connected (4 or 8 ports). The Si3480 then controls the LED display in the start-up sequence described and automatically starts managing the power among the ports as determined by the configuration pins. After start-up, the Si3480 controls the power meter and port status LEDs give a visual indication of the status. 4.1. Start-Up LED Sequence During start-up, the LEDs are lit in the sequence listed in Table 4 (1 second for each step). Table 4. LED Sequence Step Action All LEDs on. 2 Port 1 LED and either four or eight power meter LEDs to indicate the number of 4-port controllers found by the Si3480 (no LEDs if no controllers are found). 3 4 5 N ot fo R r N ec o ew m m D e es nd ig e ns d 1 Port 2 LED and zero to eight power meter LEDs to indicate the provided power as determined by reading the voltage at the PWRCFG pin in 25 W steps (e.g. two LEDs is 50 W). Port 3 LED and zero to eight power meter LEDs to indicate the number of PoE+ ports as determined by reading the voltage at the POECFG pin. Port 4 LED and zero to eight power meter LEDs to indicate the number of high-priority ports as determined by reading the voltage at the PRIOCFG pin. 4.2. Port Status LEDs After the start-up sequence, the port status LEDs display the patterns listed in Table 5 to indicate port status. Table 5. Port LED Pattern Definitions Port LED Pattern Meaning Flashing once every two seconds Detection and Classification in process Continuously lit PoE port is on Blinks off once every two seconds PoE+ port is on with a class 4 PD load (30 W granted) Flashing five times per second Port overloaded Flashing twice every two seconds Power denied due to lack of power For a port overload, an open circuit must be seen before the port is re-enabled; that is, the PD must be unplugged, and the overload must be cleared. Ports are turned off in priority order if more than the available power is being consumed. If the amount of power consumed is >10% more than the available power, all low-priority ports are shut off immediately. Ports are not granted power unless there is enough power available to grant the requested power (based on classification) with 15% margin. The 15% margin generally avoids situations where a port is granted power and then later turned off due to lack of power. If a port is turned off or denied power due to a lack of available power, the LED continues flashing twice every two seconds until enough power is available to turn the port on or the PD is unplugged. 4.3. Power Meter LEDs The power meter LEDs light consecutively, indicating the amount of power that is being consumed. There are eight LEDs in the power meter. The LEDs will light in bar graph fashion: Number_LEDs_Lit = 8 x Total_Power_Consumed / (0.85 x Provided_Power – 4 W) (rounded down) The eighth power meter LED is generally a red LED. If this LED is lit, it means that there is not enough power available to grant even a Class 1 load power and maintain a 15% margin. The eighth LED is flashed five times per second if the Si3452 controllers report a power supply undervoltage. Rev. 1.1 7 Si3480 SCL INT LEDBANK PWRCFG POECFG 5. Pin Descriptions 20 19 18 17 16 SDA 1 15 PRIOCFG GND 2 14 ALTCFG VDD 3 13 LED8 RST 4 12 LED7 NC 5 11 LED6 LED5 LED4 LED3 LED2 LED1 N ot fo R r N ec o ew m m D e es nd ig e ns d 9 10 8 7 6 Table 6. Si3480 Pin Descriptions Pin # Pin Name 1 SDA 2 Pin Function Open Collector Connect to Si3452 SDA and pull-up resistor. GND Power Ground. VDD Power VDD. RST Input NC NC LED1 Output LED2 Output LED3 Output LED4 Output LED5 Output LED6 Output LED7 Output LED8 Output 14 ALTCFG Input Low is Alternative A timing, High is Alternative B timing. See "3.1.4. Pin ALTCFG" on page 6. 15 PRIOCFG Input This pin sets the number of ports that are high priority. See "3.1.3. Pin PRIOCFG" on page 6. 16 POECFG Input The pin sets the number of ports that are high power. See "3.1.2. Pin POECFG" on page 6. 17 PWRCFG Input This pin sets the power provided. See "3.1.1. Pin PWRCFG" on page 6. 18 LEDBANK Output 19 INT Input 20 SCL 3 4 5 6 7 8 9 10 11 12 13 8 Pin Type Reset (a low will reset the Si3480). Do not connect to this pin. Pins LED1–LED4 work with Pin LEDBANK to drive the eight power meter LEDs. Pins LED5 – LED8 work with Pin LEDBANK to drive the eight port status LEDs. This pin determines which LED bank is being turned on. Connect to Si3452 INT and pull up resistor. Open Collector Connect to Si3452 SCL and pull up resistor. Rev. 1.1 Si3480 6. Ordering Guide Ordering Part Number Description Package Information Si3480-A01-GM Power management controller 20 pin 4x4 mm QFN RoHS compliant Si3480 Kit An eight-port evaluation kit with the Si3480, two Si3452 controllers and the Si3500 for generating the 3.3 V supply from the PoE supply Evaluation Board N ot fo R r N ec o ew m m D e es nd ig e ns d Notes: 1. Add “R” to the part number to denote tape and reel option (Si3480-A01-GMR) 2. The ordering part number is not the same as the device mark. See “9. Top Marking: 20-Pin QFN” for device marking information. Rev. 1.1 9 Si3480 7. Package Outline N ot fo R r N ec o ew m m D e es nd ig e ns d Figure 2 illustrates the package details for the Si3480. Table 7 lists the values for the dimensions shown in the illustration. Figure 2. QFN-20 Package Drawing Table 7. QFN-20 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A A1 b D D2 e E E2 0.80 0.00 0.18 0.90 0.02 0.25 4.00 BSC. 2.15 0.50 BSC. 4.00 BSC. 2.15 1.00 0.05 0.30 L L1 aaa bbb ddd eee Z Y 0.45 0.00 — — — — — — 0.55 — — — — — 0.43 0.18 0.65 0.15 0.15 0.10 0.05 0.08 — — 2.00 2.00 2.25 2.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 10 Rev. 1.1 Si3480 8. Landing Pattern: 20-Pin QFN N ot fo R r N ec o ew m m D e es nd ig e ns d Figure 3 illustrates the landing pattern for the Si3480. Table 8 lists the values for the dimensions shown in the illustration. Figure 3. QFN-20 Recommended PCB Land Pattern Table 8. QFN-20 PCB Land Pattern Dimensions Dimension C1 C2 E X1 Min Max Dimension Min Max X2 Y1 Y2 2.15 0.90 2.15 2.25 1.00 2.25 3.70 3.70 0.50 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. A 2x2 array of 0.95mm openings on a 1.1 mm pitch should be used for the center pad to assure the proper paste volume (71% Paste Coverage). Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 11 Si3480 9. Top Marking: 20-Pin QFN Figure 4 illustrates the top markings for the Si3480. Table 9 explains the values for the markings shown in the illustration. N ot fo R r N ec o ew m m D e es nd ig e ns d 3480A 01 TTTTT YYWW+ Figure 4. Si3480 Top Marking Table 9. Top Marking Explanations Line 1 Marking: Pin 1 Identifier Circle, 0.25 mm diameter Product ID Si3480A Line 2 Marking: Line 3 Marking: Line 4 Marking: 12 01 = Firmware revision 01 TTTTT = Trace Code YYWW = Date Code Assigned by Assembly Contractor YY = Last 2 digits of current year (ex. = 2010) WW = Current Work Week Lead Free Designator + Rev. 1.1 Si3480 DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0  Updated Table 3 Updated typical output low, typical output high, and sense accuracy. Updated pin description. Revision 1.0 to Revision 1.1 Added “Not Recommended for New Designs” watermark. N ot fo R r N ec o ew m m D e es nd ig e ns d  Rev. 1.1 13 Si3480 CONTACT INFORMATION N ot fo R r N ec o ew m m D e es nd ig e ns d Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 14 Rev. 1.1