SI4032-V2-FMR

S i 4 0 3 1/32 Si4031/32 ISM T R A N S M I T T E R Features              Integrated 32 kHz RC or 32 kHz XTAL Integrated voltage regulators Configurable packet structure TX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 20-Pin QFN package FSK, GFSK, and OOK modulation Low BOM Power-on-reset (POR) Ordering Information: See page 112. Pin Assignments Silicon Laboratories’ Si4031/32 highly integrated, single chip wireless ISM transmitter is part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4031/32 offers advanced radio features including continuous frequency coverage from 240–930 MHz with adjustable power output levels of –8 to +13 dBm on the Si4030/31 and +11 to +20 dBm on the Si4032. Power adjustments are made in 3 dB steps. The Si4031/32’s high level of integration offers reduced BOM cost while simplifying the overall system design. The Si4032’s Industry leading +20 dBm output power ensures extended range and improved link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX FIFO, and automatic packet handling reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with FCC and ETSI regulations. Preliminary Rev 0.2 2/09 Copyright © 2009 by Silicon Laboratories nSEL 20 19 18 17 16 VDD_RF 1 15 SCLK TX 2 14 SDI NC 3 13 SDO NC 4 12 VDD_DIG VR_PA 5 11 NC Metal Paddle Description XIN Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors 6 7 8 GPIO1       NC Remote control Home security & alarm Telemetry Personal data logging Toy control Wireless PC peripherals GPIO0       SDN Applications nIRQ Si4031/32 9 10 VDR      XOUT  Frequency Range = 240–930 MHz Output Power Range +11 to +20 dBm (Si4032) –8 to +13 dBm (Si4030/31) Low Power Consumption (Si4032) 80 mA @ +20 dBm 27 mA @ +11 dBm (Si4031) 28 mA @ +13 dBm 16 mA @ +1 dBm Data Rate = 1 to 128 kbps Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Wake Up Timer GPIO2   Patents pending Si4031/32 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si4031/32 SDN XOUT XIN DIGLDO nIRQ Functional Block Diagram VDR LPLDO 30 M XTAL OSC VDD Digital Logic RF LDO Controller & Register Bank PA_RAMP PWR_CTRL PLL LDO SCLK SDO SCK VCO LDO VCO 30 MHz TX LPF Delta Sigma Modulator N Battery Level Detector Temperature Sensor General Purpose 8-bit ADC 2 Preliminary Rev 0.2 VR_DIG RC 32 K OSC GPIO_2 POR GPIO_0 32 K XTAL SPI & Interfance PFD Wake-Up Timer PA_RAMP PWR_CTRL XTW CP GPIO_1 PA SDI TX DATA FIFO & Packet Handler Si4031/32 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.4. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 4.5. PN9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.6. Synchronous vs. Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Preliminary Rev 0.2 3 Si4031/32 10. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12. Pin Descriptions: Si4031/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 4 Preliminary Rev 0.2 Si4031/32 L I S T OF F IGURES Figure 1. SPI Timing.................................................................................................................. 15 Figure 2. SPI Timing—READ Mode ..........................................................................................16 Figure 3. SPI Timing—Burst Write Mode .................................................................................. 16 Figure 4. SPI Timing—Burst Read Mode .................................................................................. 16 Figure 5. State Machine Diagram.............................................................................................. 17 Figure 6. TX Timing................................................................................................................... 21 Figure 7. Frequency Deviation .................................................................................................. 25 Figure 8. FSK vs GFSK Spectrums........................................................................................... 27 Figure 9. PLL Synthesizer Block Diagram................................................................................. 30 Figure 10. FIFO Threshold ........................................................................................................33 Figure 11. Packet Structure....................................................................................................... 34 Figure 12. Multiple Packets in TX Packet Handler .................................................................... 35 Figure 13. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 36 Figure 14. POR Glitch Parameters............................................................................................ 37 Figure 15. General Purpose ADC Architecture ......................................................................... 39 Figure 16. ADC Differential Input Example—Bridge Sensor ..................................................... 40 Figure 17. ADC Differential Input Offset for Sensor Offset Coarse Compensation................... 41 Figure 18. Temperature Ranges using ADC8 ........................................................................... 43 Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46 Figure 20. Si4031 Reference Design Schematic ...................................................................... 48 Figure 21. Si4031 Reference Design Schematic—Top............................................................. 50 Figure 22. Si4031 Reference Design Schematic—Top Silkscreen ........................................... 50 Figure 23. Si4031 Reference Design Schematic—Bottom .......................................................51 Figure 24. TX Modulation (40 kbps, 20 kHz Deviation)............................................................. 52 Figure 25. Si4031 TX Unmodulated Spectrum (917 MHz)........................................................ 52 Figure 26. Si4031 TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK)..... 53 Figure 27. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ........................... 53 Figure 28. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 54 Figure 29. QFN-20 Package Dimensions................................................................................ 113 Preliminary Rev 0.2 5 Si4031/32 L I S T OF TABLES Table 1. DC Characteristics .......................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8 Table 3. Transmitter AC Electrical Characteristics1 ...................................................................9 Table 4. Auxiliary Block Specifications1 ...................................................................................10 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 11 Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 11 Table 7. Absolute Maximum Ratings ........................................................................................ 12 Table 8. Operating Modes ........................................................................................................14 Table 9. Serial Interface Timing Parameters ............................................................................15 Table 10. Operating Modes ...................................................................................................... 17 Table 11. Frequency Band Selection ....................................................................................... 23 Table 12. Packet Handler Registers ......................................................................................... 35 Table 13. POR Parameters ...................................................................................................... 37 Table 14. Temperature Sensor Range ..................................................................................... 42 Table 15. Reference Design Bill of Materials ........................................................................... 48 Table 16. Recommended Crystal Parameters ......................................................................... 55 Table 17. Register Descriptions ............................................................................................... 56 Table 18. Interrupt or Status 1 Bit Set/Clear Description ......................................................... 61 Table 19. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? ............. 61 Table 20. Interrupt or Status 2 Bit Set/Clear Description ........................................................ 63 Table 21. Detailed Description of Status Registers when not Enabled as Interrupts ............... 63 Table 22. Internal Analog Signals Available on the Analog Test Bus ...................................... 85 Table 23. Internal Digital Signals Available on the Digital Test Bus .........................................86 Preliminary Rev 0.2 6 Si4031/32 1. Electrical Specifications Table 1. DC Characteristics Parameter Symbol Conditions Min Typ Max Units 1.8 3.0 3.6 V Supply Voltage Range Vdd Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 — 10 TBD nA IStandby Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF1 — 400 — nA ISleep RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF1 — 800 — nA ISensor-LBD Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA ISensor-TS Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled1 — 600 — µA ITune Synthesizer and regulators enabled — 9.5 — mA TX Mode Current for Si4032 ITX_+20 txpow[2:0] = 011 (+20 dBm), VDD = 3.3 V — 80 — mA ITX_+11 txpow[2:0] = 000 (+11 dBm), VDD = 3.3 V — 27 — mA TX Mode Current for Si4031 ITX_+13 txpow[2:0] = 111 (+13 dBm), VDD = 3.3 V — 28 — mA ITX_+1 txpow[2:0] = 100 (+1 dBm), VDD = 3.3 V — 16 — mA TUNE Mode Current Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. Preliminary Rev 0.2 7 Si4031/32 Table 2. Synthesizer AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units FSYNTH-LB Low Band 240 — 480 MHz FSYNTH-HB High Band 480 — 930 MHz FRES-LB Low Band — 156.25 — Hz FRES-HB High Band — 312.5 — Hz Reference Frequency fREF fcrystal / 3 — 10 — MHz Reference Frequency Input Level2 fREF_LV When using reference frequency instead of crystal. Measured peak-to-peak (VPP) 0.7 — 1.6 V Synthesizer Settling Time2 tLOCK Measured from leaving Ready mode with XOSC running to any frequency including VCO Calibration — 200 — µs Residual FM2 FRMS Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) — 2 4 kHzRMS Phase Noise2 L(fM) F = 10 kHz — –80 — dBc/Hz F = 100 kHz — –90 — dBc/Hz F = 1 MHz — –115 — dBc/Hz F = 10 MHz — –130 — dBc/Hz Synthesizer Frequency Range Synthesizer Frequency Resolution2 Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 8 Preliminary Rev 0.2 Si4031/32 Table 3. Transmitter AC Electrical Characteristics1 Parameter TX Frequency Range1 2 Symbol Conditions Min Typ Max Units FSYNTH-LB Low Band 240 — 480 MHz FSYNTH-HB High Band 480 — 930 FSK Modulation Data Rate DRFSK 1 — 128 kbps OOK Modulation Data Rate2 DROOK 1.2 — 40 kbps Modulation Deviation1 Δf ±320 kHz Modulation Deviation Resolution ΔfRES Production tests maximum limit of 320 kHz ±0.625 — 0.625 — kHz Output Power Range1(Si4031) PTX Power control by txpow[2:0] Register Production test at txpow[2:0] = 11 Tested at 915 MHz –8 — +13 dBm Output Power Range1(Si4032) PTX Power control by txpow[2:0] Register Production test at txpow[2:0] = 11 Tested at 915 MHz +11 — +20 dBm TX RF Output Steps2 PRF_OUT controlled by txpow[2:0] Register — 3 — dB TX RF Output Level Variation vs. Voltage2 PRF_V Measured from VDD=3.6 V to VDD=1.8 V — 2 — dB TX RF Output Level2 Variation vs. Temperature PRF_TEMP –40 to +85 C — 2 — dB TX RF Output Level Variation vs. Frequency2 PRF_FREQ Measured across any one frequency band — 1 — dB Transmit Modulation Filtering2 B*T Gaussian Filtering Bandwith Time Product — 0.5 — Spurious Emissions2 POB-TX1 POUT = 11 dBm, Frequencies