SI4133GX2-BM

Si4133G-X2 DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz IF synthesizer 1070.4, 1080, and 1089.6 MHz Integrated VCOs, loop filters, varactors, and resonators Minimal number of external components required Optimized for use with Hitachi Bright2+ transceiver Settling time < 150 µs Low phase noise Programmable powerdown modes 1 µA standby current 18 mA typical supply current 2.7 to 3.6 V operation Packages: 24-pin TSSOP and 28-pin MLP S i4 13 3G Dual-band RF synthesizers -X T 2 Features Ordering Information See page 24. Pin Assignments Applications Si4133G-XT2 AUXOUT 4 21 GNDI RFLC 5 20 IFLB GNDR 6 19 IFLA RFLB 7 18 GNDD RFLA 8 17 VDDD GNDR 9 16 GNDD GNDR 10 15 XIN RFOUT 11 14 PWDN VDDR 12 13 AUXOUT ÷N RFOUT RFLD RF2 ÷N Phase Detector IFOUT IF ÷N IFLA IFLB GNDI IFOUT 28 27 26 25 24 23 22 GNDR 1 21 GNDI RFLD 2 20 IFLB RFLC 3 19 IFLA GNDR 4 18 GNDD RFLB 5 17 VDDD RFLA 6 16 GNDD GNDR 7 15 XIN RFLC Phase Detector VDDI RFLB RF1 SCLK Si4133G-XM2 RFLA Phase Detector 22-bit Data Register Test Mux RFLD GND Pad 8 9 10 11 12 13 14 GNDD SEN IFOUT PWDN SCLK Serial Interface 22 AUXOUT SDATA 3 SEN PWDN Powerdown Control ÷65 GNDR VDDR Reference Amplifier VDDI GNDR XIN SEN 23 RFOUT Functional Block Diagram 24 2 SDATA The Si4133G-X2 is a monolithic integrated circuit that performs both IF and dual-band RF synthesis for GSM and GPRS wireless communications applications. The Si4133G-X2 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and powerdown settings are programmable through a three-wire serial interface. 1 GNDR Description SCLK SDATA GNDR GSM 850, E-GSM 900, DCS 1800, and PCS 1900 cellular telephones GPRS data terminals HSCSD data terminals Patents pending Rev. 1.2 5/03 Copyright © 2003 by Silicon Laboratories Si4133GX2-DS12 Si4133G-X2 2 Rev. 1.2 Si4133G-X2 TA B L E O F C O N T E N TS Section Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133G-XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133G-XM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.2 4 14 15 15 15 16 17 17 17 18 18 18 19 22 23 24 25 26 27 28 3 Si4133G-X2 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Temperature TA –20 25 85 °C Supply Voltage VDD 2.7 3.0 3.6 V Supply Voltages Difference V∆ –0.3 — 0.3 V (VDDR – VDDD), (VDDI – VDDD) Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 3.0 V and an operating temperature of 25 °C unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit VDD –0.5 to 4.0 V Input Current3 IIN ±10 mA Input Voltage3 VIN -0.3 to VDD+0.3 V TSTG –55 to 150 DC Supply Voltage Storage Temperature Range o C Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should be done only at ESD-protected workstations. 3. For signals SCLK, SDATA, SEN, PWDN, and XIN. 4 Rev. 1.2 Si4133G-X2 Table 3. DC Characteristics (VDD = 2.7 to 3.6 V, TA = –20 to 85 °C) Parameter Test Condition Min Typ Max Unit RF1 and IF operating — 18 31 mA RF1 Mode Supply Current1 — 13 17 mA RF2 Mode Supply Current1 — 12 17 mA IF Mode Supply Current1 — 10 14 mA — 1 — µA Total Supply Current Symbol 1 Standby Current PWDN High Level Input Voltage2 VIH 0.7 VDD — — V Low Level Input Voltage2 VIL — — 0.3 VDD V High Level Input Current2 IIH VIH = 3.6 V, VDD = 3.6 V –10 — 10 µA Low Level Input Current2 IIL VIL = 0 V, VDD= 3.6 V –10 — 10 µA High Level Output Voltage3 VOH IOH = –500 µA VDD–0.4 — — V Low Level Output Voltage3 VOL IOH = 500 µA — — 0.4 V Notes: 1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 1080 MHz 2. For signals SCLK, SDATA, SEN, and PWDN. 3. For signal AUXOUT. Rev. 1.2 5 Si4133G-X2 Table 4. Serial Interface Timing (VDD = 2.7 to 3.6 V, TA = –20 to 85 °C) Symbol Test Condition Min Typ Max Unit SCLK Cycle Time tclk Figure 1 40 — — ns SCLK Rise Time tr Figure 1 — — 50 ns SCLK Fall Time tf Figure 1 — — 50 ns SCLK High Time th Figure 1 10 — — ns SCLK Low Time tl Figure 1 10 — — ns SDATA Setup Time to SCLK↑2 tsu Figure 2 5 — — ns SDATA Hold Time from SCLK↑2 Parameter1 thold Figure 2 0 — — ns 2 SEN↓ to SCLK↑ Delay Time ten1 Figure 2 10 — — ns SCLK↑ to SEN↑ Delay Time2 ten2 Figure 2 12 — — ns SEN↑ to SCLK↑ Delay Time2 ten3 Figure 2 12 — — ns tw Figure 2 10 — — ns SEN Pulse Width Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of waveform. See Figure 2. tr tf 80% S CLK 50% 20% th t clk tl Figure 1. SCLK Timing Diagram 6 Rev. 1.2 Si4133G-X2 tsu thold SCLK SDATA D17 D16 D15 A1 A0 ten3 ten1 ten2 SEN tw Figure 2. Serial Interface Timing Diagram First bit c loc ked in Last bit c loc ked in D D D D D D D D D 17 16 15 14 13 12 11 10 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 data field D 0 A 3 A 2 A 1 A 0 address field Figure 3. Serial Word Format Rev. 1.2 7 Si4133G-X2 Table 5. RF and IF Synthesizer Characteristics (VDD = 2.7 to 3.6 V, TA = –20 to 85 °C) Parameter1 Symbol Test Condition Min Typ Max Unit XIN Input Frequency fREF — 13 — MHz Reference Amplifier Sensitivity VREF 0.5 — VDD +0.3 VPP Internal Phase Detector Frequency fφ RF1 VCO Center Frequency Range fCEN 947 — 1720 MHz RF2 VCO Center Frequency Range fCEN 789 — 1429 MHz IFOUT Center Frequency fCEN — 1080 — MHz Note: LEXT ±10% –5 — 5 % Open loop — 0.5 — MHz/V RF2 VCO Pushing — 0.4 — MHz/V IF VCO Pushing — 0.3 — MHz/V — 0.4 — MHzPP — 0.1 — MHzPP — 0.1 — MHzPP 1 MHz offset — –132 — dBc/Hz 3 MHz offset — –142 — dBc/Hz 1 MHz offset — –134 — dBc/Hz 3 MHz offset — –144 — dBc/Hz 100 kHz offset — –117 — dBc/Hz RF1 Integrated Phase Error 100 Hz to 100 kHz — 0.9 — deg rms RF1 Harmonic Suppression Second Harmonic — –26 — dBc RF2 Harmonic Suppression — –26 — dBc IF Harmonic Suppression — –26 — dBc Tuning Range from fCEN RF1 VCO Pushing RF1 VCO Pulling RF2 VCO Pulling fφ = fREF/65 VSWR = 2:1, all phases, open loop IF VCO Pulling RF1 Phase Noise RF2 Phase Noise IF Phase Noise 200 KHz RFOUT Power Level ZL = 50 Ω –7 –2 1 dBm IFOUT Power Level ZL = 50 Ω –10 –6 –3 dBm Notes: 1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz for all parameters unless otherwise noted. 2. From powerup request (PWDN↑ or SEN↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs. 3. From powerdown request (PWDN↓, or SEN↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. 8 Rev. 1.2 Si4133G-X2 Table 5. RF and IF Synthesizer Characteristics (Continued) (VDD = 2.7 to 3.6 V, TA = –20 to 85 °C) Symbol Parameter1 RF1 Reference Spurs RF2 Reference Spurs Test Condition Min Typ Max Unit Offset = 200 kHz — –70 — dBc Offset = 400 kHz — –75 — dBc Offset = 600 kHz — –80 — dBc Offset = 200 kHz — –75 — dBc Offset = 400 kHz — –80 — dBc Offset = 600 kHz — –80 — dBc Powerup Request to Synthesizer Ready Time, RF1, RF2, IF2 tpup Figures 5, 4 — 140 — µs Powerdown Request to Synthesizer Off Time3 tpdn Figures 5, 4 — — 100 ns Notes: 1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz for all parameters unless otherwise noted. 2. From powerup request (PWDN↑ or SEN↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs. 3. From powerdown request (PWDN↓, or SEN↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. RF and IF synthesizers settled to within 0.1 ppm frequency error. tpup IT tpdn IPWDN SEN SDATA PDRB = 1 PDIB = 1 PDRB = 0 PDIB = 0 Figure 4. Software Power Management Timing Diagram RF and IF synthesizers settled to within 0.1 ppm frequency error. IT tpup tpdn IPWDN PWDN Figure 5. Hardware Power Management Timing Diagram Rev. 1.2 9 Si4133G-X2 TRACE A: Ch1 FM Gate Time A Offset 800 Hz 133.59375 us Axis is 0.1 ppm/div Real 160 Hz /div -800 Hz Stop: 299.21875 us Start: 0 s Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency 10 Rev. 1.2 Si4133G-X2 Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.2 11 Si4133G-X2 Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency 12 Rev. 1.2 Si4133G-X2 Figure 11. Typical IF Phase Noise at 1080 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 1080 MHz with 200 kHz Phase Detector Update Frequency Rev. 1.2 13 Si4133G-X2 Typical Application Circuits Si4133G-XT2 From 1 System Controller 2 5 6 7 8 9 10 RFOUT 2 nH 11 0.022 µF VDD IFOUT GNDR 4 560 pF VDDI SDATA 3 Printed Trace Inductors SEN SCLK RFLD GNDI RFLC IFLB GNDR IFLA RFLB GNDD RFLA VDDD GNDR GNDD GNDR XIN PWDN RFOUT 12 AUXOUT VDDR 24 VDD 23 0.022 µF 18 nH 22 560 pF IFOUT 21 Printed T race Inductor or Chip Inductor 20 19 18 17 0.022 µF VDD 16 560 pF 15 External Clock 14 PWDN 13 AUXOUT Figure 13. Si4133G-XT2 VDD From 0.022 µF System 18 nH 560 pF Controller IFOUT 7 GNDI IFOUT VDDI SEN SCLK SDATA RFLC IFLA Si4133G-XM2 GNDR GNDD RFLB VDDD RFLA GNDD GNDR XIN 8 9 10 11 12 13 Printed Trace Inductor or Chip Inductor 21 20 19 18 VDD 17 16 0.022 µF 560 pF 15 External Clock GNDD 6 22 IFLB PWDN 5 23 RFLD AUXOUT 4 24 VDDR Printed Trace Inductors 25 GNDI RFOUT 3 26 GNDR GNDR 2 27 GNDR 1 GNDR 28 14 VDD 0.022µF AUXOUT PWDN 2 nH 560 pF RFOUT Figure 14. Si4133G-XM2 14 Rev. 1.2 Si4133G-X2 Functional Description Serial Interface The Si4133G-X2 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless applications such as GSM 850, E-GSM 900, DCS 1800, and PCS 1900. Its fast transient response also makes the Si4133G-X2 especially well suited to GPRS and HSCSD multislot applications where channel switching and settling times are critical. This integrated circuit (IC), with a minimum number of external components, is all that is necessary to implement the frequency synthesis function. The Si4133G-X2 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. Figure 3 on page 7 shows the format of the serial interface. A timing diagram for the serial word is shown in Figure 2 on page 7. When the serial interface is enabled (i.e., when SEN is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SEN into the internal data register addressed in the address field. The serial word is disabled when SEN is high. The Si4133G-X2 has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the Si4133G-X2 suitable for use in demanding cellular applications. Phase detectors, loop filters, and reference dividers are also integrated. The IC is programmed through a three-wire serial interface. Table 9 on page 19 summarizes the Data register functions and addresses. It is not necessary (although it is permissible) to clock into the internal shift register any leading bits that are “don’t cares”. One PLL is provided for IF synthesis, and two PLLs are provided for dual-band RF synthesis. One RF VCO is optimized to have its center frequency set between 947 and 1720 MHz, whereas the second RF VCO is optimized to have its center frequency set between 789 and 1429 MHz. Each RF PLL can adjust its output frequency by ±5% relative to its VCO’s center frequency. The IF VCO is optimized to have its center frequency set to 1080 MHz. Three settings are provided for IF output frequencies of 1070.4, 1080 and 1089.6 MHz. The PLLs can adjust the IF and RF output frequencies ±5% with respect to their VCO center frequencies. Each center frequency is established by the value of an external inductance connected to the respective VCO. Manufacturing tolerances of ±10% for the external inductances are acceptable. The Si4133G-X2 compensates for inaccuracies in each inductance by executing a self-tuning algorithm following powerup or following a change in the programmed output frequency. The center frequency of each of the three VCOs is set by the connection of an external inductance. Inaccuracies in the value of the inductance are compensated for by the Si4133G-X2’s proprietary selftuning algorithm. This algorithm is initiated each time the PLL is powered-up (by either the PWDN pin or by software) and/or each time a new output frequency is programmed. Setting the VCO Center Frequencies Because the total tank inductance is in the low nH range, the inductance of the package must be considered in determining the correct external inductance. The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows: The two RF PLLs share a common output pin, so only one PLL is active at a time. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service different frequency bands, therefore the Si4133G-X2 ideal for use in dual-band cellular handsets. The unique PLL architecture used in the Si4133G-X2 produces a transient response that is superior in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. Rev. 1.2 1 F CEN = -------------------------------------------2π L TOT × C NOM or 1 F CEN = ------------------------------------------------------------------------2π ( L PKG + CL EXT ) × C NOM 15 Si4133G-X2 Tables 6 and 7 summarize these characteristics for each VCO. Table 6. Si4133G-XT2 VCO Characteristics VCO fCEN Range (MHz) CNOM (pF) Min Max RF1 947 1720 4.3 RF2 789 1429 IF 1080 LPKG (nH) LEXT Range (nH) Min Max 2.0 0.0 4.6 4.8 2.3 0.3 6.2 6.5 2.1 In most cases the requisite value of the external inductance is small enough to utilize a PC board trace. During initial board layout, a length of trace approximating the required inductance can be used. For more information, refer to AN31: Inductor Design for the Si41xx Synthesizer Family. 1.2 Self-Tuning Algorithm Table 7. Si4133G-XM2 VCO Characteristics VCO fCEN Range (MHz) CNOM (pF) Min Max RF1 947 1720 4.3 RF2 789 1429 IF 1080 LPKG (nH) The self-tuning algorithm is initiated immediately following powerup of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the required output frequency. The algorithm compensates for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It also reduces the frequency error for which the PLL must correct to get precisely the required output frequency. The self-tuning algorithm leaves the VCO oscillating at a frequency in error by less than 1% of the required output frequency. LEXT Range (nH) Min Max 1.5 0.5 5.1 4.8 1.5 1.1 7.0 6.5 1.6 1.7 After self-tuning, the PLL controls the VCO oscillation frequency. The PLL completes frequency locking, eliminating remaining frequency error. From then on, it maintains frequency-lock, compensating for effects caused by temperature and supply voltage variations. Si4133G-XM2 LPKG 2 LEXT The Si4133G-X2’s self-tuning algorithm compensates for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients approximately ±150 ppm/oC, the PLL can maintain lock for changes in temperature of approximately ±30 oC. LPKG 2 Figure 15. External Inductance Connection As a design example, consider a design that is required to synthesize frequencies in a 25 MHz band between 1120 and 1145 MHz. The center frequency should be defined as midway between the two extremes, or 1132.5 MHz. The PLL can adjust the VCO output frequency ±5% of the center frequency, or ±56.6 MHz of 1132.5 MHz (i.e., from approximately 1076 to 1189 MHz, more than enough for this example). The RF2 VCO has a CNOM of 4.8 pF, and a 4.1 nH inductance in parallel with this capacitance yields the 16 required center frequency. An external inductance of 1.8 nH should be connected between RFLC and RFLD as shown in Figure 15. This, in addition to 2.3 nH of package inductance, presents the correct total inductance to the VCO. In manufacturing, the external inductance can vary ±10% of its nominal value and the Si4133G-X2 corrects for the variation with the selftuning algorithm. Applications where the PLL is regularly powered down or switched between channels minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned when it is powered up or when a new frequency is programmed. In applications where the ambient temperature can drift substantially after selftuning, it may be necessary to monitor the LDETB (lockdetect bar) signal on the AUXOUT pin to determine the locking state of the PLL. (See the AUXILIARY OUTPUT section below for how to select LDETB.) Rev. 1.2 Si4133G-X2 The LDETB signal is low after self-tuning has completed but rises when either the IF or RF PLL nears the limit of its compensation range (LDETB is also high when either PLL is executing the self-tuning algorithm). The output frequency is still locked when LDETB goes high, but the PLL eventually loses lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be retuned by initiating the self-tuning algorithm. Output Frequencies The IF and RF output frequencies are set by programming the N-Divider registers. Each RF PLL has its own N register and can be programmed independently. All three PLL R-dividers are fixed at R=65 to yield a 200 kHz phase detector update rate from a 13 MHz reference frequency. Programming the N-Divider register for either RF1 or RF2 automatically selects the associated output. The reference frequency on the XIN pin is divided by R and this signal is input to the PLL’s phase detector. The other input to the phase detector is the PLL’s VCO output frequency divided by N. The PLL acts to make these frequencies equal. That is, after an initial transient F REF F OUT -------------- = ------------N 65 the RF and IF PLLs Tφ = 5 µS. During the first 6.5 update periods, the Si4133G-X2 executes the selftuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the Si4133G-X2 PLLs, the time required to settle the output frequency to 0.1 ppm error is approximately 21 update periods. Thus, the total time after powerup or a change in programmed frequency until the synthesized frequency is well settled (including time for self-tuning) is around 28 update periods or 140 µS. RF and IF Outputs The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which N-Divider register was last written to. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. The RFOUT pin must be coupled to its load through an ac coupling capacitor. A matching network is required to maximize power delivered into a 50 Ω load. The network consists of a 2 nH series inductance, which can be realized with a PC board trace, connected between the RFOUT pin and the ac coupling capacitor. The network is made to provide an adequate match to an external 50 Ω load for both the RF1 and RF2 frequency bands. The matching network also filters the output signal to reduce harmonic distortion. A 50 Ω load is not required for proper operation of the Si4133G-X2. Depending on transceiver requirements, the matching network may not be required. See Figure 16 below. or N F OUT = ------ × F REF 65 For XIN = 13 MHz this simplifies to 2 nH F OUT = N × 200 kHz 560 pF RFOUT The integer N is set by programming the RF1 N-Divider register (Register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). Each N-divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the calculation of these values is done automatically. Only the appropriate N value must be programmed PLL Loop Dynamics 50 Ω Figure 16. RFOUT 50 Ω Test Circuit The IFOUT pin must also be coupled to its load through an ac coupling capacitor. A matching network is also required to drive a 50 Ω load. See Figure 17 below. The transient response for each PLL is optimized for a GSM application. VCO gain, phase detector gain, and loop filter characteristics are not programmable. The settling time for each PLL is directly proportional to its phase detector update period Tφ (Tφ equals 1/fφ). For a GSM application with a 13 MHz reference frequency, Rev. 1.2 17 Si4133G-X2 18 nH The reference frequency amplifier, IF, and RF sections of the Si4133G-X2 circuitry can be individually powered down by setting the Powerdown register bits PDIB and PDRB low, respectively. The reference frequency amplifier is also powered up if the PDRB and PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Powerdown register to 1. The serial interface remains available and can be written in all powerdown modes. 560 pF IFOUT 50 Ω Figure 17. IFOUT 50 Ω Matching Network Reference Frequency Amplifier The Si4133G-X2 provides a reference frequency amplifier. If the driving signal has CMOS levels it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be ac coupled to the XIN pin through a 560 pF capacitor. Powerdown Modes Table 8 summarizes the powerdown functionality. The Si4133G-X2 can be powered down by taking the PWDN pin low or by setting bits in the Powerdown register (Register 2). When the PWDN pin is low, the Si4133GX2 is powered down regardless of the Powerdown register settings. When the PWDN pin is high, power management is under control of the Powerdown register bits. Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 11. As discussed previously, this signal can be used to indicate that the IF or RF PLL is about to lose lock because of excessive ambient temperature drift and should be re-tuned. The LDETB signal indicates a logical OR result if both IF and RF are simultaneously generating a signal. Table 8. Powerdown Configuration PWDN Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry PWDN = 0 x x x OFF OFF 0 0 0 OFF OFF 0 0 1 OFF ON 0 1 0 ON OFF 0 1 1 ON ON 1 x x ON ON PWDN = 1 18 Rev. 1.2 Si4133G-X2 Control Registers Table 9. Register Summary Register Name Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 0 Main Configuration 1 Reserved 2 Powerdown 3 RF1 NDivider 4 RF2 NDivider 0 5 IF N-Divider 0 6 Reserved Bit 3 Bit 2 Bit 1 Bit 0 1 0 0 0 0 0 AUXSEL [1:0] 0 0 0 0 0 0 0 0 AUTO PDB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB NRF1[17:0] NRF2[16:0] NIF[15:0] 0 . . . 15 Reserved Note: Registers 1 and 6–15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed here is reserved and should not be written. Rev. 1.2 19 Si4133G-X2 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name 0 0 0 0 AUXSEL [1:0] 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 AUTO PDB 0 1 0 0 Bit Name Function 17:14 Reserved 13:12 AUXSEL[1:0] 11:4 Reserved Program to zero. 3 AUTOPDB Auto Powerdown 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. 2 Reserved Program to zero. 1 Reserved Program to one. 0 Reserved Program to zero. Program to zero. Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 10 = Reserved. 11 = Lock Detect—LDETB. Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 20 0 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 0 0 0 0 0 0 0 Bit Name Function 17:2 Reserved 1 PDIB Powerdown IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. 0 PDRB Powerdown RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. Program to zero. Rev. 1.2 D1 D0 PDIB PDRB Si4133G-X2 Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 NRF1[17:0] Name Bit Name Function 17:0 NRF1[17:0] N-Divider for RF1 Synthesizer. Register 4. RF2 N-Divider Address Field = A[3:0] = 0100 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name D9 0 D8 D7 D6 NRF2[16:0] Bit Name Function 17 Reserved Program to zero. 16:0 NRF2[16:0] N-Divider for RF2 Synthesizer. Register 5. IF N-Divider Address Field (A[3:0]) = 0101 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 D9 0 D8 D7 D6 NIF[15:0] Name Function 17:16 Reserved Program to zero. 15:0 NIF[15:0] N-Divider for IF Synthesizer. Only the following values are allowed (frequencies assume XIN is 13 MHz): 7150 = 1070.4 MHz 7215 = 1080.0 MHz 7280 = 1089.6 MHz Rev. 1.2 21 Si4133G-X2 Pin Descriptions: Si4133G-XT2 SCLK 1 24 SEN SDATA 2 23 VDDI GNDR 3 22 IFOUT RFLD 4 21 GNDI RFLC 5 20 IFLB GNDR 6 19 IFLA RFLB 7 18 GNDD RFLA 8 17 VDDD GNDR 9 16 GNDD GNDR 10 15 XIN RFOUT 11 14 PWDN VDDR 12 13 AUXOUT Pin Number Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3 GNDR Common ground for RF analog circuitry 4 RFLD Pins for inductor connection to RF2 VCO 5 RFLC Pins for inductor connection to RF2 VCO 6 GNDR Common ground for RF analog circuitry 7 RFLB Pins for inductor connection to RF1 VCO 8 RFLA Pins for inductor connection to RF1 VCO 9 GNDR Common ground for RF analog circuitry 10 GNDR Common ground for RF analog circuitry 11 RFOUT Radio frequency (RF) output of the selected RF VCO 12 VDDR Supply voltage for the RF analog circuitry 13 AUXOUT Auxiliary output 14 PWDN Powerdown input pin 15 XIN Reference frequency amplifier input 16 GNDD Common ground for digital circuitry 17 VDDD Supply voltage for digital circuitry 18 GNDD Common ground for digital circuitry 19 IFLA Pins for inductor connection to IF VCO 20 IFLB Pins for inductor connection to IF VCO 21 GNDI Common ground for IF analog circuitry 22 IFOUT Intermediate frequency (IF) output of the IF VCO 23 VDDI Supply voltage for IF analog circuitry 24 SEN Enable serial port input 22 Rev. 1.2 Si4133G-X2 GNDI IFOUT VDDI SEN SCLK SDATA GNDR Pin Descriptions: Si4133G-XM2 28 27 26 25 24 23 22 GNDR 1 21 GNDI RFLD 2 20 IFLB RFLC 3 19 IFLA GNDR 4 18 GNDD RFLB 5 17 VDDD RFLA 6 16 GNDD GNDR 7 15 XIN GNDD PWDN VDDR GNDR 10 11 12 13 14 AUXOUT 9 RFOUT 8 GNDR GND Pad Pin Number Name Description 1 GNDR Common ground for RF analog circuitry 2 RFLD Pins for inductor connection to RF2 VCO 3 RFLC Pins for inductor connection to RF2 VCO 4 GNDR Common ground for RF analog circuitry 5 RFLB Pins for inductor connection to RF1 VCO 6 RFLA Pins for inductor connection to RF1 VCO 7 GNDR Common ground for RF analog circuitry 8 GNDR Common ground for RF analog circuitry 9 GNDR Common ground for RF analog circuitry 10 RFOUT Radio frequency (RF) output of the selected RF VCO 11 VDDR Supply voltage for the RF analog circuitry 12 AUXOUT Auxiliary output 13 PWDN Powerdown input pin 14 GNDD Common ground for digital circuitry 15 XIN Reference frequency amplifier input 16 GNDD Common ground for digital circuitry 17 VDDD Supply voltage for digital circuitry 18 GNDD Common ground for digital circuitry 19 IFLA Pins for inductor connection to IF VCO 20 IFLB Pins for inductor connection to IF VCO 21 GNDI Common ground for IF analog circuitry 22 GNDI Common ground for IF analog circuitry 23 IFOUT Intermediate frequency (IF) output of the IF VCO 24 VDDI Supply voltage for IF analog circuitry 25 SEN Enable serial port input 26 SCLK Serial clock input 27 SDATA Serial data input 28 GNDR Common ground for RF analog circuitry Rev. 1.2 23 Si4133G-X2 Ordering Guide 24 Ordering Part Number Description Package Temperature Si4133G-XM2 RF1/RF2/IF OUT 28-Pin MLP –20 to 85 oC Si4133G-XT2 RF1/RF2/IF OUT 24-Pin TSSOP –20 to 85 oC Rev. 1.2 Si4133G-X2 Package Outline: Si4133G-XT2 Figure 18 illustrates the package details for the Si4133G-XT2. Table 10 lists the values for the dimensions shown in the illustration. E H θ L B D A e A1 γ C Approximate device weight is 115.7 mg. Figure 18. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 10. Package Diagram Dimensions Millimeters Symbol Min Max Typical* A — 1.20 3 A1 0.05 0.15 3 B 0.19 0.30 C 0.09 0.20 D 7.70 7.90 E 4.30 4.50 e 0.65 BSC H 6.40 BSC L 0.45 0.75 θ 0° 8° γ 3 3 0.10 *Note: To guarantee coplanarity (γ), the parameters marked “Typical” may be exceeded. Rev. 1.2 25 Si4133G-X2 Package Outline: Si4133G-XM2 Figure 19 illustrates the package details for the Si4113G-XM2. Table 11 lists the values for the dimensions shown in the illustration. A D D/2 A D1 b A1 D1/2 D2 N 1 2 3 E1/2 1 2 3 E/2 E1 E2 E (Ne–1) Xe REF. L θ TOP VIEW e (Nd–1) Xe REF. CC CL b A1 BOTTOM VIEW SECTION "C–C" SCALE: NONE e Figure 19. 28-Pin Micro Leadframe Package (MLP) Table 11. Package Dimensions Symbol Millimeters Min Nom Max A — 0.85 0.90 A1 0.00 0.01 0.05 b 0.18 0.23 0.30 D, E 5.00 BSC D1, E1 4.75 BSC D2 2.55 2.70 2.85 E2 2.55 2.70 2.85 N 28 Nd 7 Ne 7 e 0.50 BSC L 0.50 0.60 θ 26 Pin 1 ID 0.20 R N 0.75 12° Rev. 1.2 Si4133G-X2 Document Change List Revision 1.1 to Revision 1.2 TSSOP outline updated. Rev. 1.2 27 Si4133G-X2 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free:1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 28 Rev. 1.2