SI4133W-BM

Si4133W RF S Y N T H E S I Z E R W I T H I N T E G R A T E D V C O S F O R W - CD M A A N D G S M / U M T S W I R E L E S S C O M M U N I C A T I O N S Features Dual RF synthesizers RF1: 2.3 GHz to 2.6 GHz RF2: 750 MHz to 1.7 GHz IF synthesizer IF: 62.5 MHz to 1.0 GHz Integrated VCOs, loop filters, dividers, and phase detectors Minimal external components Continuous operation over a wide temperature range Fast settling time: 200 µsec Low phase noise 5 µA standby current 28-lead MLP, 5 x 5 mm Ordering Information: See page 28. Applications Single-mode W-CDMA wireless handsets, terminals, and modems Dual-mode GSM/UMTS wireless handsets, terminals, and modems GNDR RFLD Pin Assignments Si4133W-BM SDATA IFOUT GNDR SENB SCLK GNDI VDDI Description The Si4133W is a monolithic integrated circuit that performs RF and IF synthesis for GSM/GPRS and W-CDMA wireless communications. In dualmode GSM/UMTS handsets, the Si4133W meets demanding requirements for very low phase noise and fast settling time for both modes. The Si4133W integrates three complete phase-locked loops (PLLs) on a single die including VCOs, loop filters, reference and VCO dividers, and phase detectors. Dividers and powerdown settings are programmable through a three-wire serial interface. GNDI IFLB IFLA GNDD VDDD GNDD XIN RFLC GNDR NC GNDR GNDR AUXOUT RFOUT GNDR GNDR Functional Block Diagram Patents pending XIN Reference Am plifier Power Down Control ÷R Phase Detector RF1 PW DNB ÷N ÷R RFOUT SDATA SCLK SENB Serial Interface 22-bit Data Register Phase Detector RF2 RFLC RFLD ÷N ÷R AUXOUT Test Mux Phase Detector IF IFDIV IFOUT ÷N IFLA IFLB Rev. 1.1 9/02 Copyright © 2002 by Silicon Laboratories Si4133W-DS11 PW DNB GNDD VDDR S i4133W 2 Rev. 1.1 S i4133W TA B L E O F C O N T E N TS Section Page 4 16 16 16 17 18 18 19 19 19 20 1 27 28 29 30 32 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si4133W-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: Si4133W-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.1 3 S i4133W Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Symbol TA VDD V∆ (VDDR – VDDD), (VDDI – VDDD) Test Condition Min –25 2.7 –0.3 Typ 25 3.3 — Max 85 3.6 0.3 Unit °C V V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. Table 2. Absolute Maximum Ratings1,2 Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value –0.5 to 4.0 ±10 –0.3 to VDD+0.3 –55 to 150 Unit V mA V °C Note: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN. 4 Rev. 1.1 S i4133W Table 3. DC Characteristics (VDD = 2.7 to 3.6 V, TA = –25 to 85 °C) Parameter Typical Supply Current1 RF1 Mode Supply Current1 RF2 Mode Supply Current IF Mode Supply Current Standby Current High Level Input Voltage2 Low Level Input Voltage 2 2 1 1 Symbol Test Condition RF1 and IF operating Min — — — — Typ 23 15 12 9 5 — — — — — — Max 27.5 18 15 11.5 — — 0.3 VDD 10 10 — 0.4 Unit mA mA mA mA µA V V µA µA V V PWDNB = 0 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = –500 µA IOH = 500 µA — 0.7 VDD — –10 –10 VDD–0.4 — High Level Input Current Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage Notes: 3 1. RF1 = 2.4 GHz, RF2 = 1.6 GHz, IFOUT = 800 MHz, LPWR = 0. 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT. Rev. 1.1 5 S i4133W Table 4. Serial Interface Timing (VDD = 2.7 to 3.6 V, TA = –25 to 85 °C) Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK↑ 2 2 Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 40 — — 10 10 5 0 10 12 12 10 Typ — — — — — — — — — — — Max — 50 50 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns SDATA Hold Time from SCLK↑ SENB↓ to SCLK↑ Delay Time SENB↑ to SCLK↑ Delay Time SENB Pulse Width 2 SCLK↑ to SENB↑ Delay Time2 2 Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2. 6 Rev. 1.1 S i4133W tr 80% tf S CLK 50% 20% th t clk tl Figure 1. SCLK Timing Diagram ts u t hold S CLK S DA TA D17 D16 D15 A1 A0 t en3 ten2 ten1 S E NB tw Figure 2. Serial Interface Timing Diagram First bit c loc ked in Last bit clocked in DDDDDDDDD 17 16 15 14 13 12 11 10 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A 3 A 2 A 1 A 0 data field address field Figure 3. Serial Interface Format Rev. 1.1 7 S i4133W Table 5. Si4133W RF and IF Synthesizer Characteristics (VDD = 2.7 to 3.6 V, TA = –25 to 85 °C) Parameter1 XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency2 RF1 VCO Tuning Range 3 Symbol fREF VREF fφ fCEN Test Condition Min 2 0.5 Typ — — — — — — — — — 300 150 50 150 50 10 –130 –145 –150 1.7 –132 1.2 Max 40 VDD +0.3 V 250 2600 1619 5 952 1000 5 — — — — — — — — — — — — Unit MHz VPP kHz MHz MHz % MHz MHz % kHz/V kHz/V kHz/V kHz p-p kHz p-p kHz p-p dBc/Hz dBc/Hz dBc/Hz degrees rms dBc/Hz degrees rms fφ = fREF/R 10 2300 789 RF2 VCO Center Frequency Range4 RF2 Tuning Range from fCEN5 IF VCO Center Frequency Range IFOUT Tuning Range from fCEN IFOUT VCO Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise Note: LEXT ±10% fCEN with IFDIV Note: LEXT ±10% Open loop –5 526 62.5 –5 — — — VSWR = 2:1, all phases, open loop — — — 1 MHz offset 5 MHz offset 10 MHz offset — — — — — — RF1 Integrated Phase Error RF2 Phase Noise RF2 Integrated Phase Error 100 Hz to 1 MHz 1 MHz offset 100 Hz to 1 MHz Notes: 1. fφ = 200 kHz, RF1 = 2.4 GHz, RF2 = 1.5 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Low update frequencies have a maximum value of N for stable operation. See Table 8 on page 18. 3. RF1 tuning range is fixed by inductance of internally bonded wires. 4. RF2 VCO center frequency is fixed by inductance of printed circuit board trace or external inductor. To properly design and layout the external inductor, see “AN31: Inductor Design for the Si41xx Synthesizer Family”. 5. Tuning range of externally tuned VCO assumes tolerance of LEXT to ±10%. See “Setting the VCO Center Frequencies” on page 16. 6. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to synthesizer ready (settled to within 0.1 ppm frequency error). 7. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. 8 Rev. 1.1 S i4133W Table 5. Si4133W RF and IF Synthesizer Characteristics (Continued) (VDD = 2.7 to 3.6 V, TA = –25 to 85 °C) Parameter1 IF Phase Noise IF Integrated Phase Error RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Output Power Level ZL = 50 Ω, RF1 active ZL = 50 Ω, RF2 active IFOUT Output Power Level IF Output Voltage Level RF1 Output Reference Spurs ZL = 50 Ω ZL = 200 Ω Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz RF2 Output Reference Spurs Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz Power Up Request to Synthesizer Ready Time, RF1/RF2/IF6 Power Down Request to Synthesizer Off Time, RF1/RF2/IF7 tpup tpdn Figure 4, Figure 5 Figure 4, Figure 5 Symbol Test Condition 100 kHz offset 100 Hz to 1 MHz Second Harmonic Min — — — — — –8 –5 –7.5 — — — — — — — — — Typ –115 0.7 –28 –23 –26 –3 –1 –4 0.30 –65 –70 –75 –65 –70 –75 200 — Max — — –20 –20 –20 0.5 1 –1 — — — — — — — — 100 Unit dBc/Hz degrees rms dBc dBc dBc dBm dBm dBm VRMS dBc dBc dBc dBc dBc dBc µs ns Notes: 1. fφ = 200 kHz, RF1 = 2.4 GHz, RF2 = 1.5 GHz, IFOUT = 800 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Low update frequencies have a maximum value of N for stable operation. See Table 8 on page 18. 3. RF1 tuning range is fixed by inductance of internally bonded wires. 4. RF2 VCO center frequency is fixed by inductance of printed circuit board trace or external inductor. To properly design and layout the external inductor, see “AN31: Inductor Design for the Si41xx Synthesizer Family”. 5. Tuning range of externally tuned VCO assumes tolerance of LEXT to ±10%. See “Setting the VCO Center Frequencies” on page 16. 6. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to synthesizer ready (settled to within 0.1 ppm frequency error). 7. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN. Rev. 1.1 9 S i4133W RF and IF s y nthes iz ers s ettled to w ithin 0.1 ppm f requenc y error. tpup tpdn t pup RF and IF synthesizers settled to within 0.1 ppm frequency error. IT I PW D N S E NB IT IPW DN PW DNB t pdn S DA TA PD IB = 1 PD R B = 1 PD IB = 0 PD R B = 0 Figure 4. Software Power Management Timing Diagram Figure 5. Hardware Power Management Timing Diagram 10 Rev. 1.1 S i4133W Figure 6. Typical Transient Response RF1 at 2.4 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.1 11 S i4133W -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 Offset Frequency (Hz) 1.E+05 1.E+06 Figure 7. Typical RF1 Phase Noise at 2.4 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 2.4 GHz with 200 kHz Phase Detector Update Frequency 12 Rev. 1.1 S i4133W -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 Offset Frequency (Hz) 1.E+05 1.E+06 Figure 9. Typical RF2 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.1 13 S i4133W -60 -70 -80 -90 -100 -110 -120 -130 -140 1.E+02 1.E+03 1.E+04 O ffse t Fre que nc y (Hz) 1.E+05 1.E+06 Figure 11. Typical IF Phase Noise at 800 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 800 MHz with 200 kHz Phase Detector Update Frequency 14 Rev. 1.1 S i4133W V DDI 30 Ω * From System Controller 28 27 26 25 24 23 0.022 µ F 40 nH 560 pF IFOUT 22 VDDI SCLK SDATA IFOUT GNDR SENB GNDI Printed Trace Inductor 1 2 3 4 GNDR RFLD RFLC GNDR GNDI IFLB IFLA 21 20 19 18 17 16 15 Printed Trace Inductor Si4133W G NDD VDDD G NDD AUXOUT XIN GNDD V DD 5 NC 6 7 GNDR GNDR RFOUT GNDR GNDR VDDR 0.022 µ F 560 pF External Clock 8 9 10 11 12 13 PW DNB 14 V DD 0.022 µ F AUXOUT 2 nH * Add 30 Ω s eries resistance w hen using IF output divide values 2, 4, or 8, and operating at frequencies greater than 500 MHz. 560 pF RFOUT Figure 13. Application Diagram Rev. 1.1 15 S i4133W Functional Description The Si4133W is a monolithic integrated circuit that performs IF and dual-band RF synthesis for W-CDMA communications applications. The Si4133W may be operated continuously over a wide ambient temperature range of –25 to +85 oC. The Si4133W has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the Si4133W suitable for use in demanding wireless communications applications. Also integrated are phase detectors, loop filters, and reference and output frequency dividers. The IC is programmed through a three-wire serial interface. Two PLLs are provided for dual-band RF synthesis. These RF PLLs are multiplexed so that only one PLL is active at a given time, as determined by the setting of an internal register. The active PLL is the last one written. The center frequency of the VCO in each PLL is set either by the internally bonded inductance within the package or by the value of an external inductance. For example, the Si4133W can have the RF2 center frequency set by an external inductor, while the RF1 center frequency is fixed by the inductance of internal bond wires. Inaccuracies in these inductances are compensated for by the self-tuning algorithm. The Si4133W executes the algorithm following powerup or following a change in the programmed output frequency. The RF2 PLL, whose frequency is set through an external inductance, can adjust the output frequency by ±5% of its VCO’s center frequency when active. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service two widely separated frequency bands by programming the corresponding N-Divider. The Si4133W has the RF1 VCO optimized to operate from 2.3 to 2.6 GHz, while the RF2 VCO is optimized to have its center frequency set between 750 MHz and 1.7 GHz. One PLL is provided for IF synthesis. The center frequency of this circuit’s VCO is set by connection of an external inductance. The PLL can adjust the IF output frequency by ±5% of the VCO center frequency. Inaccuracies in the value of the external inductance are compensated for by the Si4133W’s proprietary selftuning algorithm. This algorithm is initiated each time the PLL is powered-up (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The IF VCO can have its center frequency set as low as 526 MHz and as high as 952 MHz. An IF output divider is provided to divide down the IF output frequencies, if needed. The divider is programmable, capable of dividing by 1, 2, 4, or 8. The unique PLL architecture used in the Si4133W produces settling (lock) times comparable in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. Serial Interface A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial interface. The Si4133W is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SENB into the internal data register addressed in the address field. The serial interface is disabled when SENB is high. Table 11 on page 21 summarizes the data register functions and addresses. The internal shift register will ignore any leading bits before the 22 required bits. Setting the VCO Center Frequencies The PLLs can adjust the IF and RF2 output frequencies ±5% of the center frequencies of their VCOs. The RF1 PLL has a fixed operating range due to the inductance set by the internally bonded wires. Each center frequency for IF and RF2 PLLs is established by the value of the total inductance (internal and/or external) connected to the respective VCO. Manufacturing tolerances of ±10% for the external inductances are acceptable. The Si4133W will compensate for inaccuracies in each inductance by executing a selftuning algorithm following PLL powerup or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows: 16 Rev. 1.1 S i4133W 1 f CEN = --------------------------------------------2 π L TOT ⋅ C NOM For more information on designing the external trace inductors, please refer to Application Note 31. or f CEN 1 = ---------------------------------------------------------------------2 π ( L PKG + L EXT ) ⋅ C NOM Self-Tuning Algorithm The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In doing so, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. The Si4133W’s self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients around ±150 ppm/oC, the PLL will be able to maintain lock for changes in temperature of –50 to +80 oC from the temperature at which it initialized lock. If the PLL is regularly powered down or the frequency is periodically reprogrammed, then this temperature range is of no concern because the VCO lock will be reinitiated. Lock-detect bar (LDETB) may be monitored on the AUXOUT pin for an indication that the PLL is about to run out of locking capability. (See “Auxiliary Output (AUXOUT)” for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL nears the limit of its compensation range. LDETB will also be high when either PLL is executing the self-tuning algorithm. The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to change in the same direction. Therefore, if LDETB goes high, both the IF and RF PLLs should promptly be re-tuned by initiating the selftuning algorithm. Table 6 summarizes the characteristics of each VCO. Table 6. Si4133W-BM VCO Characteristics VCO Fcen Range Cnom (MHz) (pF) Min Max Lpkg (nH) Lext Range (nH) Min Max RF2 IF 789 526 1619 952 5.1 6.8 1.6 1.6 0.29 2.5 6.4 11.9 L PKG 2 L EXT L PKG 2 Figure 14. External Inductance Connection As a design example, suppose synthesizing IFs in a 30 MHz band between 735 MHz and 765 MHz is desired. The center frequency should be defined as midway between the two extremes, or 750 MHz. The PLL will be able to adjust the VCO output frequency ±5% of the center frequency, or ±37.5 MHz of 750 MHz (i.e., from approximately 713 to 788 MHz). The IF VCO has a CNOM of 6.8 pF. A 6.6 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 5.0 nH should be connected between IFLA and IFLB, as shown in Figure 14. This, in addition to 1.6 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary ±10% of its nominal value and the Si4133W will correct for the variation with the self-tuning algorithm. Rev. 1.1 17 S i4133W Output Frequencies The IF and RF output frequencies are set by programming the R- and N-Divider registers. Each PLL has its own R and N registers so that each can be programmed independently. Programming either the Ror N-Divider register for RF1 or RF2 automatically selects the associated output. The reference frequency on the XIN pin is divided by R and this signal is the input to the PLL’s phase detector. The other input to the phase detector is the PLL’s VCO output frequency divided by N. The PLL works to make these frequencies equal. That is, after an initial transient f OUT f REF ----------- = ----------N R The gain value bits must be set manually by writing to Register 1. In general, a higher phase detector gain will increase the speed of the PLL transient until the point at which stability begins to be compromised. The optimal gain depends on N. Table 8 lists recommended settings for different values of N. For large values of N, the output may become unstable as indicated by “x”. In that case, to avoid unstable operation, it is recommended to increase the phase detector update rate (by lowering R or increasing fREF) to achieve the same output frequency. Table 8. Optimal KP Settings N ≤1023 RF1 KP1 00 00 00 01 10 11 11 11 x RF2 KP2 00 00 01 10 11 11 11 x x IF KPI 00 01 10 11 11 11 x x x or f OUT N = --- ⋅ f REF R 1024–2047 2048–4095 4096–8191 8192–16383 16384–24575 24576–57343 57344–98303 ≥98304 The integers R are set by programming the RF1 RDivider register (Register 6), the RF2 R-Divider register (Register 7) and the IF R-Divider register (Register 8). The values of R are limited to the range of about 7 (decimal) to 8189 depending on the phase detector gain (see Registers 6–8 on pages 25 and 26.) The integers N are set by programming the RF1 NDivider register (Register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). Each N-Divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. Note: The “x” indicates possible unstable operation. PLL Loop Dynamics The transient response for each PLL is determined by its phase detector update rate fφ (equal to fREF/R) and the phase detector gain programmed for each RF1, RF2, or IF synthesizer. (See Register 1.) Four different settings for the phase detector gain are available for each PLL. The highest gain is programmed by setting the two phase detector gain bits to 00 and the lowest by setting the bits to 11. The values of the available gains relative to the highest gain are shown in Table 7. Table 7. Gain Values (Register 1) KP Bits 00 01 10 11 Relative P.D. Gain 1 1/2 1/4 1/8 The VCO gain and loop filter characteristics are not programmable. The settling time for the PLL is directly proportional to its phase detector update period Tφ (Tφ = 1/fφ). During the first 13 update periods the Si4133W executes the selftuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the Si4133W PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled—including time for selftuning—is around 40 update periods. 18 Rev. 1.1 S i4133W RF and IF Outputs (RFOUT and IFOUT) The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which R- or NDivider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. Figure 13 on page 15 shows an application diagram for the Si4133W. The RF output signal must be coupled to its load through an ac coupling capacitor. An external inductance between the RFOUT pin and the ac coupling capacitor is required as part of an output matching network to maximize power delivered to the load. This 2 nH inductance may be realized with a PC board trace. The network is made to provide an adequate match to an external 50 Ω load for both the RF1 and RF2 frequency bands. The matching network also filters the output signal to reduce harmonic distortion. The IFOUT pin must also be coupled to its load through an ac coupling capacitor. The IF output level is dependent upon the load. Figure 17 displays the output level versus load resistance for a variety of output frequencies. For resistive loads greater than 500 Ω the output level saturates and the bias currents in the IF output amplifier are higher than they need to be. The LPWR bit in the Main Configuration register (Register 0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the IF amplifier. For loads less than 500 Ω, LPWR should be set to 0 to maximize the output level. For IF frequencies greater than 500 MHz, a matching network is required in order to drive a 50 Ω load. See Figure 15. Table 9. LMATCH Values Frequency 500–600 MHz 600–800 MHz 800–1 GHz LMATCH 40 nH 27 nH 18 nH For frequencies less than 500 MHz, the IF output buffer can directly drive a 200 Ω resistive load or higher. For resistive loads greater than 500 Ω (f < 500 MHz) the LPWR bit can be set to reduce the power consumed by the IF output buffer. See Figure 16. >500 pF IFOUT >200 Ω Figure 16. IF Frequencies < 500 MHz 450 400 350 LPWR=1 LPWR=0 300 Output Voltage (mVrms) 250 200 150 100 50 >500 pF IFOUT L MATCH 50 Ω 0 0 200 400 600 Load Resistance (Ω ) 800 1000 1200 Figure 17. IF Output Voltage vs. Load Reference Frequency Amplifier The Si4133W provides a reference frequency amplifier. If the driving signal has CMOS levels, it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be ac coupled to the XIN pin through a 560 pF capacitor. Figure 15. IF Frequencies > 500 MHz Power Down Modes Table 10 summarizes the power down functionality. The Si4133W can be powered down by taking the PWDNB pin low or by setting bits in the Powerdown register (Register 2). When the PWDNB pin is low, the Si4133W Rev. 1.1 19 S i4133W will be powered down regardless of the Powerdown register settings. When the PWDNB pin is high, power management is under control of the Powerdown register bits. The reference frequency amplifier, IF, and RF sections of the Si4133W circuitry can be individually powered down by setting the Power Down register bits PDIB and PDRB low. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Powerdown register to 1. The serial interface remains available and can be written in all power down modes. When multiple Si4133Ws are driven by a single reference oscillator, as in variable duplex W-CDMA applications, additional bits may be set in the control registers to prevent unwanted interaction during power down. For further information please refer to Application Note 44. Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 11b. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be re-tuned. Table 10. Power Down Configuration PWDNB Pin PWDNB = 0 AUTOPDB X 0 0 PWDNB = 1 0 0 1 PDIB X 0 0 1 1 x PDRB X 0 1 0 1 x IF Circuitry OFF OFF OFF ON ON ON RF Circuitry OFF OFF ON OFF ON ON 20 Rev. 1.1 S i4133W Control Registers Table 11. Register Summary Register Name Bit Bit Bit Bit 17 16 15 14 Bit 13 Bit 12 Bit 11 Bit Bit Bit Bit Bit 10 9 8 7 6 Bit 5 LPWR Bit 4 Bit 3 AUTO PDB Bit 2 Bit 1 Bit 0 0 1 2 3 4 5 6 7 8 9 . . . 15 Main Configuration Phase Detector Gain Powerdown 0 0 0 0 0 0 0 0 0 0 0 0 AUXSEL[1:0] IFDIV[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 KPI[1:0] 0 0 KP2[1:0] 0 0 KP1[1:0] PDIB PDRB RF1 N-Divider NRF1[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRF2[16:0] NIF[15:0] RRF1[12:0] RRF2[12:0] RIF[12:0] RF2 N-Divider IF N-Divider RF1 R-Divider RF2 R-Divider IF R-Divider Reserved Reserved Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Rev. 1.1 21 S i4133W Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 AUXSEL[1:0] IFDIV[1:0] D9 0 D8 0 D7 0 D6 0 D5 LPWR D4 0 D3 AUTO PDB D2 0 D1 1 D0 0 Bit 17:14 13:12 Name Reserved AUXSEL[1:0] Program to zero. Function Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 10 = Reserved. 11 = Lock Detect (LDETB). IF Output Divider. 00 = IFOUT = IFVCO Frequency 01 = IFOUT = IFVCO Frequency/2 10 = IFOUT = IFVCO Frequency/4 11 = IFOUT = IFVCO Frequency/8 Program to zero. Output Power-Level Settings for IF Synthesizer Circuit. 0 = RLOAD < 500 Ω—normal power mode. 1 = RLOAD ≥ 500 Ω—low power mode. Program to zero. Auto Power Down. 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. Program to zero. Program to one. Program to zero. 11:10 IFDIV[1:0] 9:6 5 Reserved LPWR 4 3 Reserved AUTOPDB 2 1 0 Reserved Reserved Reserved 22 Rev. 1.1 S i4133W Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit Name Bit 17:6 5:4 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 0 0 D9 0 D8 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0 KPI[1:0] KP2[1:0] KP1[1:0] Name Reserved KPI[1:0] Program to zero. Function IF Phase Detector Gain Constant. N Value KPI 4095 = 11 RF2 Phase Detector Gain Constant. N Value KP2 8191 = 11 RF1 Phase Detector Gain Constant. N Value KP1 16383 = 11 3:2 KP2[1:0] 1:0 KP1[1:0] Rev. 1.1 23 S i4133W Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit Name Bit 17:2 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0 PDIB PDRB Name Reserved PDIB Program to zero. Function Power Down IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. Power Down RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. 0 PDRB Note: Enabling any PLL with PDIB or PDRB will automatically power on the reference amplifier. Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 Bit Name Bit 17:0 Name NRF1[17:0] N-Divider for RF1 Synthesizer. D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NRF1[17:0] Function Register 4. RF2 N-Divider Address Field = A[3:0] = 0100 Bit Name Bit 17 16:0 D17 D16 D15 D14 D13 D12 D11 D10 0 Name Reserved NRF2[16:0] Program to zero. N-Divider for RF2 Synthesizer. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NRF2[16:0] Function 24 Rev. 1.1 S i4133W Register 5. IF N-Divider Address Field (A[3:0]) = 0101 Bit Name Bit 17:16 15:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 Name Reserved NIF[15:0] Program to zero. N-Divider for IF Synthesizer. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NIF[15:0] Function Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name 17:13 12:0 Reserved RRF1[12:0] Program to zero. R-Divider for RF1 Synthesizer. RRF1 can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RRF1[12:0] Function Register 7. RF2 R-Divider Address Field (A[3:0]) = 0111 Bit Name Bit 17:13 12:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name Reserved RRF2[12:0] Program to zero. R-Divider for RF2 Synthesizer. RRF2 can be any value from 7 to 8189 if KP2 = 00 8 to 8189 if KP2 = 01 10 to 8189 if KP2 = 10 14 to 8189 if KP2 = 11 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RRF2[12:0] Function Rev. 1.1 25 S i4133W Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit Name Bit 17:13 12:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name Reserved RIF[12:0] Program to zero. R-Divider for IF Synthesizer. RIF can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIF[12:0] Function 26 Rev. 1.1 S i4133W Pin Descriptions: Si4133W-BM SDATA IFOUT GNDR SENB SCLK GNDI VDDI GNDR RFLD RFLC GNDR NC GNDR GNDR GNDI IFLB IFLA GNDD VDDD GNDD XIN RFOUT AUXOUT PW DNB GNDR Pin Number(s) Name 1,4, 6–9, 28 2, 3 5 10 11 12 13 14, 16, 18 15 17 19–20 21–22 23 24 25 26 27 GNDR RFLC, RFLD NC RFOUT VDDR AUXOUT PDWNB GNDD XIN VDDD IFLA, IFLB GNDI IFOUT VDDI SENB SCLK SDATA Description Common ground for RF analog circuitry Pins for inductor connection to RF2 VCO No connect Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Power down input pin Common ground for digital circuitry Reference frequency amplifier input Supply voltage for digital circuitry Pins for inductor connection to IF VCO Common ground for IF analog circuitry Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input Serial clock input Serial data input GNDR Rev. 1.1 GNDD VDDR 27 S i4133W Ordering Guide Ordering Part Number Si4133W-BM Description 2.4 GHz/RF2/IFOUT Operating Temperature –25 to 85 oC 28 Rev. 1.1 S i4133W Package Outline: Si4133W-BM A D D/2 D1 D1/2 N 1 2 3 A A1 D2 N 1 2 3 E E2 (Ne–1) Xe REF. b Pin 1 ID 0.20 R E1/2 E1 E/2 L TOP VIEW CC C L θ e (Nd–1) Xe REF. C L b A1 BOTTOM VIEW SECTION "C–C" SCALE: NONE e e FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE Figure 18. 28-Pin Micro Leadframe Package (MLP) Table 12. Package Dimensions Controlling Dimension: mm Symbol Min A A1 b D, E D1, E1 D2, E2 N Nd Ne e L θ 0.50 2.55 — 0.00 0.18 Millimeters Nom 0.85 0.01 0.23 5.00 BSC 4.75 BSC 2.70 28 7 7 0.50 BSC 0.60 0.75 12° 2.85 Max 0.90 0.05 0.30 Rev. 1.1 29 S i4133W Document Change List Revision 1.0 to Revision 1.1 Table 5 on page 8 RFOUT and IFOUT Output Power Level specifications have been updated Note 1 RF2 spec changed to 1.5 GHz 30 Rev. 1.1 S i4133W Notes: Rev. 1.1 31 S i4133W Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free: 1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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