Si4330-B1
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Si4330 ISM R ECEIVER
Description
nSEL
nIRQ
20 19 18 17 16
NC 2
15 SCLK
RXp 3
14 SDI
GND
PAD
RXn 4
13 SDO
NC 5
12 VDD_DIG
6
7
8
9
10 11 NC
Patents pending
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Silicon Laboratories’ Si4330 is a highly integrated, single chip wireless ISM
receiver. The high-performance EZRadioPRO® family includes a complete line of
transmitters, receivers, and transceivers allowing the RF system designer to
choose the optimal wireless part for their application.
The Si4330 offers advanced radio features including continuous frequency
coverage from 240–960 MHz. The Si4330’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The extremely low
receive sensitivity (–121 dBm) ensures extended range and improved link
performance. Built-in antenna diversity and support for frequency hopping can be
used to further extend range and enhance performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte RX FIFO, automatic packet handling, and preamble detection
reduce overall current consumption and allow the use of a lower-cost system
MCU. An integrated temperature sensor, general purpose ADC, power-on-reset
(POR), and GPIOs further reduce overall system cost and size.
The Si4330’s digital receive architecture features a high-performance ADC and
DSP based modem which performs demodulation, filtering, and packet handling
for increased flexibility and performance.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
VDD_RF 1
XOUT
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Tag readers
GPIO_2
VR_DIG
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Tire pressure monitoring
Wireless PC peripherals
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Si4330
XIN
Applications
Pin Assignments
GPIO_1
SDN
Ordering Information:
See page 63.
GPIO_0
Programmable GPIOs
Embedded antenna diversity
algorithm
Configurable packet handler
Preamble detector
RX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
Low BOM
Power-on-reset (POR)
ANT1
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Frequency Range = 240–960 MHz
Sensitivity = –121 dBm
Low Power Consumption
18.5 mA receive
Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Digital RSSI
Wake-up timer
Auto-frequency calibration (AFC)
Clear channel assessment
Programmable RX BW 2.6–620 kHz
Programmable packet handler
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Features
Rev 1.0 12/09
Copyright © 2009 by Silicon Laboratories
Si4330
Si4330-B1
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Functional Block Diagram
2
Preliminary Rev. 0.1
Si4330-B1
TABLE O F C ONTENTS
Page
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Section
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.3. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.8. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.9. Receive Header Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Preliminary Rev. 0.1
3
Si4330-B1
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8.6. Wake-Up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.9. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
10. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.1. Si4330 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16. Package Outline: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
17. PCB Land Pattern: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4
Preliminary Rev. 0.1
Si4330-B1
L I S T OF F IGURES
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Figure 1. RX Application Example............................................................................................ 14
Figure 2. SPI Timing.................................................................................................................. 16
Figure 3. SPI Timing—READ Mode ..........................................................................................17
Figure 4. SPI Timing—Burst Write Mode .................................................................................. 17
Figure 5. SPI Timing—Burst Read Mode .................................................................................. 17
Figure 6. State Machine Diagram.............................................................................................. 18
Figure 7. RX Timing .................................................................................................................. 22
Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset .................................................. 26
Figure 9. PLL Synthesizer Block Diagram................................................................................. 30
Figure 10. FIFO Threshold ........................................................................................................32
Figure 11. Packet Structure....................................................................................................... 33
Figure 12. Required RX Packet Structure with Packet Handler Disabled ................................. 33
Figure 13. Multiple Packets in RX Packet Handler.................................................................... 34
Figure 14. Multiple Packets in RX with CRC or Header Error ................................................... 34
Figure 15. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 36
Figure 16. Manchester Coding Example ...................................................................................36
Figure 17. Header ..................................................................................................................... 38
Figure 18. POR Glitch Parameters............................................................................................ 40
Figure 19. General Purpose ADC Architecture ......................................................................... 42
Figure 20. Temperature Ranges using ADC8 ........................................................................... 44
Figure 21. WUT Interrupt and WUT Operation.......................................................................... 47
Figure 22. Low Duty Cycle Mode .............................................................................................. 48
Figure 23. RSSI Value vs. Input Power..................................................................................... 51
Figure 24. Receiver—Schematic Receiver—Top...................................................................... 52
Figure 25. 20-Pin Quad Flat No-Lead (QFN) ............................................................................60
Figure 26. PCB Land Pattern .................................................................................................... 61
Preliminary Rev. 0.1
5
Si4330-B1
L I S T OF TABLES
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Table 1. DC Characteristics1 ......................................................................................................7
Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8
Table 3. Receiver AC Electrical Characteristics1 .......................................................................9
Table 4. Auxiliary Block Specifications1 ...................................................................................10
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 11
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 11
Table 7. Absolute Maximum Ratings ........................................................................................ 12
Table 8. Operating Modes ........................................................................................................15
Table 9. Serial Interface Timing Parameters ............................................................................16
Table 10. Operating Modes Response Time ............................................................................18
Table 11. Frequency Band Selection ....................................................................................... 24
Table 12. Packet Handler Registers ......................................................................................... 35
Table 13. Minimum Receiver Settling Time .............................................................................. 37
Table 14. POR Parameters ...................................................................................................... 40
Table 15. Temperature Sensor Range ..................................................................................... 43
Table 16. Antenna Diversity Control ......................................................................................... 50
Table 17. Register Descriptions ............................................................................................... 54
Table 18. Package Dimensions ................................................................................................ 60
Table 19. PCB Land Pattern Dimensions ................................................................................. 62
Preliminary Rev. 0.1
6
Si4330-B1
1. Electrical Specifications
Symbol
Conditions
Min
Typ
Max Units
1.8
3.0
3.6
V
—
15
50
nA
—
450
800
nA
—
1
—
µA
1
—
µA
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Parameter
D
Table 1. DC Characteristics1
Supply Voltage Range
VDD
Power Saving Modes
IShutdown
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF2
IStandby
Low Power Digital Regulator ON (Register values retained)
and Main Digital Regulator, and RC Oscillator OFF
ISleep
RC Oscillator and Low Power Digital Regulator ON
(Register values retained) and Main Digital Regulator OFF
ISensor-LBD
Main Digital Regulator and Low Battery Detector ON,
Crystal Oscillator and all other blocks OFF2
ISensor-TS
Main Digital Regulator and Temperature Sensor ON,
Crystal Oscillator and all other blocks OFF2
—
1
—
µA
IReady
Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF. Crystal Oscillator buffer disabled
—
800
—
µA
ITune
Synthesizer and regulators enabled
—
8.5
—
mA
—
18.5
—
mA
RX Mode Current
IRX
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TUNE Mode Current
—
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
Preliminary Rev. 0.1
7
Si4330-B1
Table 2. Synthesizer AC Electrical Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
240
—
960
MHz
156.25
—
Hz
312.5
—
Hz
—
1.6
V
200
—
µs
FSYN
Synthesizer Frequency
Resolution2
FRES-LB
Low Band, 240–480 MHz
—
FRES-HB
High Band, 480–960 MHz
—
fREF_LV
When using external reference signal
driving XOUT pin, instead of using
crystal. Measured peak-to-peak (VPP)
0.7
Synthesizer Settling Time2
tLOCK
Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO calibration.
—
Residual FM2
FRMS
Integrated over 250 kHz bandwidth
(500 Hz lower bound of integration)
—
2
4
kHzRMS
Phase Noise2
L(fM)
F = 10 kHz
—
–80
—
dBc/Hz
F = 100 kHz
—
–90
—
dBc/Hz
F = 1 MHz
—
–115
—
dBc/Hz
F = 10 MHz
—
–130
—
dBc/Hz
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Reference Frequency
Input Level2
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Synthesizer Frequency
Range
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
8
Preliminary Rev. 0.1
Si4330-B1
Table 3. Receiver AC Electrical Characteristics1
FRX
RX Channel Bandwidth3
BER Variation vs Power
Level3
LNA Input Impedance3
(Unmatched—measured
differentially across RX
input pins)
2-Ch Offset Selectivity
3-Ch Offset
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)3
—
PRX_125
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)
PRX_OOK
(BER < 0.1%)
(4.8 kbps, 350 kHz BW, OOK)3
—
dBm
–104
—
dBm
–101
—
dBm
—
–110
—
dBm
(BER < 0.1%)
(40 kbps, 400 kHz BW, OOK)3
—
–102
—
dBm
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—
620
kHz
0
0.1
ppm
RIN-RX
915 MHz
—
51–60j
—
868 MHz
—
54–63j
—
433 MHz
—
89–110j
—
315 MHz
—
107–137j
—
—
±0.5
—
dB
—
–31
—
dB
—
–35
—
dB
—
–40
—
dB
—
–52
—
dB
—
–56
—
dB
—
–63
—
dB
C/I3-CH
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–108
—
4MBLOCK
Spurious Emissions3
dBm
2.6
Offset3
Image Rejection
—
Up to +5 dBm Input Level
1MBLOCK
3
–121
PRX_RES
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Blocking at 8 MHz
MHz
PRX_100
3
Blocking at 4 MHz Offset
960
—
3
Blocking at 1 MHz Offset
—
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
C/I2-CH
Selectivity3
240
PRX_40
C/I1-CH
3
Units
—
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1-Ch Offset Selectivity
Max
(BER < 0.1%)
(2 kbps, GFSK, BT = 0.5,
f = 5 kHz)3
RESRSSI
3
Typ
PRX_2
BW
RSSI Resolution
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RX Frequency
Range
RX Sensitivity2
Conditions
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Symbol
D
Parameter
Desired Ref Signal 3 dB above sensitivity,
BER < 0.1%. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with
BT = 0.5, channel spacing = 150 kHz
Desired Ref Signal 3 dB above sensitivity.
Interferer and desired modulated with
40 kbps F = 20 kHz GFSK with BT = 0.5
ImREJ
Rejection at the image frequency.
IF=937 kHz
—
–30
—
dB
POB_RX1
Measured at RX pins
—
—
–54
dBm
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed
in the "Production Test Conditions" section on page 13.
2. Receive sensitivity at multiples of 30 MHz may be degraded. If channels with a multiple of 30 MHz are required it is
recommended to shift the crystal frequency. Contact Silicon Labs Applications Support for recommendations.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 13.
Preliminary Rev. 0.1
9
Si4330-B1
Table 4. Auxiliary Block Specifications1
Conditions
Min
Typ
Max
Units
Temperature Sensor
Accuracy2
TSA
After calibrated via sensor offset
register tvoffs[7:0]
—
0.5
—
°C
Temperature Sensor
Sensitivity2
TSS
—
5
—
mV/°C
Low Battery Detector
Resolution2
LBDRES
—
50
—
mV
Low Battery Detector
Conversion Time2
LBDCT
—
250
—
µs
Microcontroller Clock
Output Frequency
FMC
—
30M
Hz
—
8
—
bit
—
4
—
mV/bit
—
305
—
µs
—
600
—
µs
30MRES
—
97
—
fF
t32k
—
6
—
sec
—
100
—
ppm
32KRCRES
—
2500
—
ppm
POR Reset Time
tPOR
—
16
—
ms
Software Reset Time2
tsoft
—
100
—
µs
General Purpose ADC Bit
Resolution2
ADCRES
Temp Sensor & General
Purpose ADC Conversion
Time2
ADCCT
30 MHz XTAL Start-Up time
30 MHz XTAL Cap
Resolution2
t30M
32 kHz XTAL Start-Up Time2
32KRES
om
32 kHz XTAL Accuracy
using 32 kHz XTAL2
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32 kHz Accuracy using
Internal RC Oscillator2
D
32.768K
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General Purpose ADC Resolution2
Configurable to 30 MHz,
15 MHz, 10 MHz, 4 MHz,
3 MHz, 2 MHz, 1 MHz, or
32.768 kHz
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Symbol
fo
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Parameter
Using XTAL and board layout in
reference design. Start-up time
will vary with XTAL type and
board layout.
Using 20 ppm 32 kHz Crystal
N
ot
R
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section on page 13.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on
page 13.
10
Preliminary Rev. 0.1
Si4330-B1
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Symbol
Conditions
Min
Typ
Max
Units
Rise Time
TRISE
0.1 x VDD to 0.9 x VDD, CL= 5 pF
—
—
8
ns
Fall Time
TFALL
0.9 x VDD to 0.1 x VDD, CL= 5 pF
—
es
ig
ns
Parameter
—
8
ns
—
1
pF
—
—
V
—
0.6
V
—
100
nA
CIN
—
Logic High Level Input Voltage
VIH
VDD – 0.6
Logic Low Level Input Voltage
VIL
Input Current
IIN
0
