SI4420-D1-FT

Si4420 Universal ISM Band FSK Transceiver Si4420 PIN ASSIGNMENT DESCRIPTION SDI SCK nSEL SDO nIRQ FSK / DATA / nFFS DCLK / CFIL / FFIT CLK Silicon Labs’ Si4420 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 315, 433, 868 and 915 MHz bands. The Si4420 transceiver is a part of Silicon Labs’ EZRadioTM product line, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. The chip is a complete analog RF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. The Si4420 features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation. Consequently, no external components (except crystal and decoupling) are needed in most applications. The Si4420 dramatically reduces the load on the microcontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the Si4420 can provide a clock signal for the microcontroller, avoiding the need for two crystals. For low power applications, the Si4420 supports low duty cycle operation based on the internal wake-up timer. FUNCTIONAL BLOCK DIAGRAM MIX I AMP OC 7 clk RF1 13 Self cal. LNA RF2 12 MIX Q AMP Data Filt CLK Rec I/Q DEMOD data OC PA FIFO RSSI PLL & I/Q VCO with cal. RF Parts COMP DQD AFC BB Amp/Filt./Limiter CLK div Xosc WTM with cal. Data processing units LBD Controller Bias Low Power parts 8 9 15 1 2 CLK XTL / REF ARSSI SDI SCK 3 4 nSEL SDO 5 10 16 11 14 nIRQ nRES nINT / VDI VSS VDD 6 DCLK / CFIL / FFIT / FSK / DATA / nFFS nINT / VDI ARSSI VDD RF1 RF2 VSS nRES XTL / REF Rev C and later This document refers to Si4420-IC Rev D1. See www.silabs.com/integration for any applicable errata. See back page for ordering information. FEATURES                          Fully integrated (low BOM, easy design-in) No alignment required in production Fast-settling, programmable, high-resolution PLL synthesizer Fast frequency-hopping capability High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) Direct differential antenna input/output Integrated power amplifier Programmable TX frequency deviation (15 to 240 KHz) Programmable RX baseband bandwidth (67 to 400 kHz) Analog and digital RSSI outputs Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX synchron pattern recognition SPI compatible serial control interface Clock and reset signals for microcontroller 16 bit RX Data FIFO Two 8 bit TX data registers Low power duty cycle mode Standard 10 MHz crystal reference Wake-up timer 2.2 to 5.4 V supply voltage Low power consumption Low standby current (0.3 A) Compact 16 pin TSSOP package TYPICAL APPLICATIONS         Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy controls Remote keyless entry Tire pressure monitoring Telemetry Remote automatic meter reading 1 Si4420-DS Rev 1.7r 0308 www.silabs.com Si4420 DETAILED FEATURE-LEVEL DESCRIPTION The Si4420 FSK transceiver is designed to cover the unlicensed frequency bands at 315, 433, 868 and 915 MHz. The devices facilitate compliance with FCC and ETSI requirements. The receiver block employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The Si4420 incorporates a fully integrated multi-band PLL synthesizer, PA with antenna tuning, an LNA with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. Calibration always occurs when the synthesizer starts. If temperature or supply voltage changes significantly or operational band has changed, VCO recalibration is recommended.. Recalibration can be initiated at any time by switching the synthesizer off and back on again. RF Power Amplifier (PA) Data Filtering and Clock Recovery Output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: The filter is an RC type low-pass filter followed by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are integrated on the chip. An (external) capacitor can be chosen according to the actual bit rate. In this mode, the receiver can handle up to 256 kbps data rate. The FIFO can not be used in this mode and clock is not provided for the demodulated data. The LNA has 250 Ohm input impedance, which functions well with the proposed antennas (see: Application Notes available from www.silabs.com/integration) Digital operation: A digital filter is used with a clock frequency at 29 times the bit rate. In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. Using this clock the received data can fill a FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow mode. The CR starts in fast mode, then after locking it automatically switches to slow mode. If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. (Only the digital data filter and the clock recovery use the bit rate clock. For analog operation, there is no need for setting the correct bit rate.) The power amplifier has an open-collector differential output and can directly drive a loop antenna with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly trimming procedures and the so-called “hand effect.” LNA The LNA gain can be selected (0, –6, –14, –20 dB relative to the highest gain) according to RF signal strength. It can be useful in an environment with strong interferers. Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. An appropriate bandwidth can be chosen to accommodate various FSK deviation, data rate and crystal tolerance requirements. The filter structure is 7th order Butterworth lowpass with 40 dB suppression at 2*BW frequency. Offset cancellation is done by using a high-pass filter with a cut-off frequency below 7 kHz. 2 Si4420 Data Validity Blocks RSSI A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital RSSI can be can be monitored by reading the status register. Analog RSSI Voltage vs. RF Input Power When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Configuration Setting Command, the chip provides a fixed number (196) of further clock pulses (“clock tail”) for the microcontroller to let it go to idle or sleep mode. Low Battery Voltage Detector The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50 mV hysteresis. Wake-Up Timer P1 RSSI voltage [V] P2 P3 P4 The wake-up timer has very low current consumption (1.5 μA typical) and can be programmed from 1 ms to several days with an accuracy of ±5%. It calibrates itself to the crystal oscillator at every startup. When the crystal oscillator is switched off, the calibration circuit switches it on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. Event Handling Input Power [dBm] P1 -65 dBm 1300 mV P2 -65 dBm 1000 mV P3 -100 dBm 600 mV P4 -100 dBm 300 mV In order to minimize current consumption, the transceiver supports different power saving modes. Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface). The Data Quality Detector is based on counting the spikes on the unfiltered received data. For correct operation, the “DQD threshold” parameter must be filled in by using the Data Filter Command. If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin. AFC Interface and Controller By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the TX/RX offset in discrete steps, allowing the use of: An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data. DQD  Inexpensive, low accuracy crystals  Narrower receiver bandwidth (i.e. increased sensitivity)  Higher data rate Crystal Oscillator The Si4420 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The transceiver can supply the clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal. The transmitter block is equipped with an 8 bit wide TX data register. It is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. It is also possible to store the received data bits into a FIFO register and read them out in a buffered mode. 3 Si4420 PACKAGE PIN DEFINITIONS Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output SDI SCK nSEL SDO nIRQ FSK / DATA / nFFS DCLK / CFIL / FFIT CLK nINT / VDI ARSSI VDD RF1 RF2 VSS nRES XTL / REF Pin Name Type Function 1 SDI DI Data input of the serial control interface 2 SCK DI Clock input of the serial control interface 3 nSEL DI Chip select input of the serial control interface (active low) 4 SDO DO Serial data output with bus hold (tri-state) 5 nIRQ DO Interrupt request output (active low) FSK DI Transmit FSK data input DATA DO Received data output (FIFO not used) nFFS DI FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command DLCK DO Received data clock output (Digital filter used, FIFO not used) CFIL AIO External data filter capacitor connection (Analog filter used) FFIT DO FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the preprogrammed limit In FIFO mode, when bit ef is set in Configuration Setting Command CLK DO Microcontroller clock output XTL AIO Crystal connection (the other terminal of crystal to VSS) or external reference input REF AIO External reference input. Use 33 pF series coupling capacitor 10 nRES DIO Open drain reset output with internal pull-up and input buffer (active low) 11 VSS S Ground reference voltage 12 RF2 AIO RF differential signal input/output 13 RF1 AIO RF differential signal input/output 14 VDD S Positive supply voltage 15 ARSSI AO Analog RSSI output nINT DI Interrupt input (active low) VDI DO Valid data indicator output 6 7 8 9 16 Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver. 4 Si4420 Typical Application Typical application with FIFO usage VCC Microcontroller C1 1u P7 P6 P5 P4 P3 P2 P1 P0 CLKin nRES VDI SDI C2 100p C3 10p (optional) 1 16 SCK nSEL 2 3 15 14 SDO nIRQ 4 5 FFIT (optional) (optional) CLK (optional) nRES (optional) nFFS Si4420 (optional) C4 2.2n 13 12 6 11 7 8 10 9 Transmit mode el=0 in Configuration Setting Command Transmit mode el=1 in Configuration Setting Command Receive mode ef=0 in Configuration Setting Command Receive mode ef=1 in Configuration Setting Command TP X1 10MHz PCB Antenna Pin 6 Pin 7 TX Data input - Connect to logic high - RX Data output RX Data clock output nFFS input FFIT output 5 Si4420 GENERAL DEVICE SPECIFICATIONS All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Parameter Vdd Positive supply voltage -0.5 6 V Vin Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V Voc Voltage on open collector outputs (RF1, RF2) -0.5 Vdd+1.5 (Note 1) V Iin Input current into any pin except VDD and VSS -25 25 mA ESD Electrostatic discharge with human body model Tst Tld Min Max Units 1000 Storage temperature -55 Lead temperature (soldering, max 10 s) V 125 o 260 o C C Recommended Operating Range Symbol Parameter Vdd Positive supply voltage VocDC DC voltage on open collector outputs (RF1, RF2) VocAC AC peak voltage on open collector outputs (RF1, RF2) Top Ambient operating temperature Min Max 2.2 Vdd-1.5 (Note 1) -40 Units 5.4 V Vdd+1.5 (Note 2) V Vdd+1.5 85 V o C Note 1: At maximum, Vdd+1.5 V cannot be higher than 7 V. At minimum, Vdd - 1.5 V cannot be lower than 1.2 V. Note 2: At maximum, Vdd+1.5 V cannot be higher than 5.5 V. 6 Si4420 ELECTRICAL SPECIFICATION (Min/max values are valid over the whole recommended operating range, typ conditions: Top = 27 oC; Vdd = Voc = 2.7 V) DC Characteristics Symbol Idd_TX_0 Idd_TX_PMAX Parameter Supply current (TX mode, Pout = 0 dBm) Supply current (TX mode, Pout = Pmax) Idd_RX Supply current (RX mode) Ipd Standby current (Sleep mode) Ilb Low battery voltage detector current consumption Iwt Wake-up timer current consumption Conditions/Notes Min Typ Max Units 315/433 MHz bands 13 14 868 MHz band 16 18 915 MHz band 17 19 315/433 MHz bands 21 22 868 MHz band 23 25 915 MHz band 24 26 315/433 MHz bands 11 13 868 MHz band 12 14 915 MHz band 13 15 All blocks disabled 0.3 µA 0.5 µA 1.5 µA Ix Idle current Crystal oscillator and baseband parts are on Vlb Low battery detect threshold Programmable in 0.1 V steps Vlba Low battery detection accuracy Vil Digital input low level voltage Vih Digital input high level voltage Iil Digital input current Vil = 0 V Iih Digital input current Vih = Vdd, Vdd = 5.4 V Vol Digital output low level Iol = 2 mA Voh Digital output high level Ioh = -2 mA 3 2.25 3.5 5.35 +/-3 mA mA mA mA V % 0.3*Vdd V -1 1 µA -1 1 µA 0.4 V 0.7*Vdd Vdd-0.4 V V 7 Si4420 AC Characteristics (PLL parameters) Symbol Parameter Conditions/Notes fref PLL reference frequency (Note 1) fo Receiver LO/Transmitter carrier frequency tlock PLL lock time tst, P PLL startup time Min 8 Typ 10 Max Units 12 MHz 315 MHz band, 2.5 kHz resolution 310.24 319.75 433 MHz band, 2.5 kHz resolution 430.24 439.75 868 MHz band, 5.0 kHz resolution 860.48 879.51 915 MHz band, 7.5 kHz resolution 900.72 929.27 Frequency error < 1kHz 20 after 10 MHz step With a running crystal oscillator MHz µs 250 µs Max Units AC Characteristics (Receiver) Symbol BW Parameter Receiver bandwidth Conditions/Notes Min Typ mode 0 60 67 75 mode 1 120 134 150 mode 2 180 200 225 mode 3 240 270 300 mode 4 300 350 375 400 mode 5 360 BR FSK bit rate With internal digital filters 0.6 BRA FSK bit rate With analog filter -3 -109 kHz 450 115.2 kbps 256 kbps -100 dBm Pmin Receiver Sensitivity BER 10 , BW=67 kHz, BR=1.2 kbps (Note 2) AFCrange AFC locking range dfFSK: FSK deviation in the received signal IIP3inh Input IP3 In band interferers in high bands (868, 915 MHz) -21 dBm IIP3outh Input IP3 Out of band interferers l f-fo l > 4 MHz -18 dBm IIP3inl IIP3 (LNA –6 dB gain) In band interferers in low bands (315, 433 MHz) -15 dBm IIP3outl IIP3 (LNA –6 dB gain) Out of band interferers l f-fo l > 4 MHz -12 dBm Pmax Maximum input power LNA: high gain Cin RF input capacitance RSa RSSI accuracy RSr RSSI range CARSSI Filter capacitor for ARSSI RSstep RSSI programmable level steps RSresp DRSSI response time 0.8*dfFSK 0 dBm 1 pF +/-5 dB 46 dB 1 Until the RSSI signal goes high after the input signal exceeds the preprogrammed limit CARRSI = 5 nF nF 6 dB 500 µs All notes for tables above are on page 10. 8 Si4420 AC Characteristics (Transmitter) Symbol Parameter Conditions/Notes IOUT Open collector output DC current Programmable Available output power with optimal antenna impedance (Note 3, 4) In low bands 8 Pmax In high bands 4 Pout Typical output power Selectable in 2.5 dB steps (Note 5) Psp Spurious emission At max power with loop antenna (Note 6) Output capacitance (set by the automatic antenna tuning circuit) In low bands 2 2.6 3.2 Co In high bands 2.1 2.7 3.3 Quality factor of the output capacitance In low bands 13 15 17 In high bands 8 10 12 Qo Lout Output phase noise BR FSK bit rate dffsk FSK frequency deviation Min Typ 0.5 Max 6 Units mA dBm Pmax-21 Pmax dBm -50 dBc pF 100 kHz from carrier -75 1 MHz from carrier -85 Programmable in 15 kHz steps 15 dBc/Hz 256 kbps 240 kHz Max Units AC Characteristics (Turn-on/Turnaround timings) Symbol Parameter Conditions/Notes tsx Crystal oscillator startup time Crystal ESR < 100 (Note 8) Min Typ Ttx_rx_XTAL_ON Transmitter - Receiver turnover time Synthesizer off, crystal oscillator on during TX/RX change with 10 MHz step 450 µs Trx_tx_XTAL_ON Receiver - Transmitter turnover time Synthesizer off, crystal oscillator on during RX/TX change with 10 MHz step 350 µs Ttx_rx_SYNT_ON Transmitter - Receiver turnover time Synthesizer and crystal oscillator on during TX/RX change with 10 MHz step 425 µs Trx_tx_SYNT_ON Receiver - Transmitter turnover time Synthesizer and crystal oscillator on during RX/TX change with 10 MHz step 300 µs 1 5 ms AC Characteristics (Others) Symbol Parameter Conditions/Notes Cxl Crystal load capacitance, see crystal selection guide Programmable in 0.5 pF steps, tolerance +/- 10% tPOR Internal POR timeout After Vdd has reached 90% of final value (Note 7) tPBt Wake-up timer clock accuracy Crystal oscillator must be enabled to ensure proper calibration at startup (Note 8) Cin, D Digital input capacitance tr, f Digital output rise/fall time 15 pF pure capacitive load Min Typ 8.5 Max Units 16 pF 150 ms +/-10 % 2 pF 10 ns All notes for tables above are on page 10. 9 Si4420 AC Characteristics (continued) Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will change accordingly. Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time). Note 3: See matching circuit parameters and antenna design guide for information. Note 4: Optimal antenna admittance/impedance: Si4420 Zantenna [Ohm] Lantenna [nH] 315 MHz Yantenna [S] 1.5E-3 - j5.14E-3 52 + j179 98.00 433 MHz 1.4E-3 - j7.1E-3 27 + j136 52.00 868 MHz 2E-3 - j1.5E-2 8.7 + j66 12.50 915 MHz 2.2E-3 - j1.55E-2 9 + j63 11.20 Note 5: Adjustable in 8 steps. Note 6: With selective resonant antennas (see: Application Notes available from www.silabs.com/integration). Note 7: During this period, commands are not accepted by the chip. For detailed information see the Reset modes section. Note 8: The crystal oscillator start-up time strongly depends on the capacitance seen by the oscillator. Using low capacitance and low ESR crystal is recommended. When designing the PCB layout keep the trace connecting to the crystal short to minimize stray capacitance. 10 Si4420 CONTROL INTERFACE Commands (or TX data) to the transceiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers. The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When the nSEL is high, the SDO output is in a high impedance state. The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:  The TX register is ready to receive the next byte (RGIT)  The FIFO has received the preprogrammed amount of bits (FFIT)  Power-on reset (POR)  FIFO overflow (FFOV) / TX register underrun (RGUR)  Wake-up timer timeout (WKUP)  Negative pulse on the interrupt input pin nINT (EXT)  Supply voltage below the preprogrammed value is detected (LBD) FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out. Timing Specification Symbol Parameter Minimum value [ns] tCH Clock high time 25 tCL Clock low time 25 tSS Select setup time (nSEL falling edge to SCK rising edge) 10 tSH Select hold time (SCK falling edge to nSEL rising edge) 10 tSHI Select high time 25 tDS Data setup time (SDI transition to SCK rising edge) 5 tDH Data hold time (SCK rising edge to SDI transition) 5 tOD Data delay time 10 Timing Diagram tSHI tSS nSEL tCH tSH tOD tCL SCK tDS tDH SDI BIT15 SDO FFIT BIT14 BIT13 BIT8 BIT7 BIT1 BIT0 11 Si4420 Control Commands Control Command Related Parameters/Functions Related control bits 1 Configuration Setting Command Frequency band, crystal oscillator load capacitance, TX register, RX FIFO el, ef, b1 to b0, x3 to x0 2 Power Management Command Receiver/Transmitter mode change, synthesizer, xtal osc, PA, wake-up timer, clock output can be enabled here er, ebb, et, es, ex, eb, ew, dc 3 Frequency Setting Command Frequency of the local oscillator/carrier signal f11 to f0 4 Data Rate Command Bit rate cs, r6 to r0 5 Receiver Control Command Function of pin 16, Valid Data Indicator, baseband bw, LNA gain, digital RSSI threshold p16, d1 to d0, i2 to i0, g1 to g0, r2 to r0 6 Data Filter Command Data filter type, clock recovery parameters al, ml, s, f2 to f0 7 FIFO and Reset Mode Command Data FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable f3 to f0, al, ff, dr 8 Receiver FIFO Read Command RX FIFO can be read with this command 9 AFC Command AFC parameters a1 to a0, rl1 to rl0, st, fi, oe, en 10 TX Configuration Control Command Modulation parameters, output power, ea mp, m3 to m0, p2 to p0 11 Transmitter Register Write Command TX data register can be written with this command t7 to t0 12 Wake-Up Timer Command Wake-up time period r4 to r0, m7 to m0 13 Low Duty-Cycle Command Enable low duty-cycle mode. Set duty-cycle. d6 to d0, en 14 Low Battery Detector and Microcontroller Clock Divider Command LBD voltage and microcontroller clock division ratio d2 to d0, v4 to v0 15 Status Read Command Status bits can be read out In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the command registers after power-on. Description of the Control Commands 1. Configuration Setting Command Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 el 6 ef 5 b1 4 b0 3 x3 2 x2 1 x1 0 x0 POR 8008h Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level. Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. b1 0 0 1 1 b0 0 1 0 1 Frequency Band {MHz] 315 433 868 915 x3 0 0 0 0 x2 0 0 0 0 x1 0 0 1 1 x0 0 1 0 1 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 … 1 1 1 1 1 1 0 1 15.5 16.0 12 Si4420 2. Power Management Command Bit 15 1 14 0 13 0 12 0 11 0 10 0 9 1 8 0 7 er 6 ebb 5 et 4 es 3 ex 2 eb 1 ew 0 dc POR 8208h Bit Function of the control bit Related blocks er Enables the whole receiver chain RF front end, baseband, synthesizer, oscillator ebb The receiver baseband circuit can be separately switched on Baseband et Switches on the PLL, the power amplifier, and starts the transmission (If TX register is enabled) Power amplifier, synthesizer, oscillator es Turns on the synthesizer Synthesizer ex Turns on the crystal oscillator Crystal oscillator eb Enables the low battery detector Low battery detector ew Enables the wake-up timer Wake-up timer dc Disables the clock output (pin 8) Clock output buffer The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time. Logic connections between power control bits: enable power amplifier et start TX Edge detector clear TX latch (If TX latch is used) es enable RF synthesizer (osc.must be on) er enable RF front end enable baseband circuits ebb (synt. must be on) enable oscillator ex 13 Si4420 3. Frequency Setting Command Bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F value sent is out of range, the previous value is kept. The synthesizer center frequency f0 can be calculated as: 3 f3 2 f2 1 f1 0 f0 POR A680h The constants C1 and C2 are determined by the selected band as: f0 = 10 * C1 * (C2 + F/4000) [MHz] Band [MHz] 315 C1 1 C2 31 433 1 43 868 2 43 915 3 30 4. Data Rate Command 15 1 14 1 13 0 12 0 11 0 10 1 9 1 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C623h The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit parameter R (bits r6 to r0) and bit cs. BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps] In the receiver set R according to the next function: R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps. Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Data rate accuracy requirements: Clock recovery in slow mode: BR / BR < 1 / (29*Nbit) Clock recovery in fast mode: BR / BR < 3 / (29*Nbit) BR is the bit rate set in the receiver and BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximal number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be careful to use the same division ratio in the receiver and in the transmitter. 5. Power Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 0 1 0 p16 d1 d0 i2 i1 i0 g1 g0 r2 r1 r0 9080h Bit 10 (p16): pin16 function select p16 Function of pin 16 0 Interrupt input 1 VDI output 14 Si4420 Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting: d1 0 0 1 1 d0 0 1 0 1 Response Fast Medium Slow Always on CR_LOCK DQD d0 CR_LOCK d1 DRSSI MEDIUM FAST SLOW DQD LOGIC HIGH SEL0 SEL1 IN0 IN1 Y VDI IN2 IN3 MUX DRSSI DQD SET CR_LOCK Q R/S FF CLR Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select: i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 1 i0 0 1 0 1 0 1 0 1 BW [kHz] reserved 400 340 270 200 134 67 reserved 15 Si4420 Bits 4-3 (g1 to g0): LNA gain select: g1 0 0 1 1 g0 0 1 0 1 relative to maximum [dB] 0 -6 -14 -20 Bits 2-0 (r2 to r0): RSSI detector threshold: r2 0 0 0 0 1 1 1 1 r1 0 0 1 1 0 0 1 1 r0 0 1 0 1 0 1 0 1 RSSIsetth [dBm] -103 -97 -91 -85 -79 -73 Reserved Reserved The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSIth=RSSIsetth+GLNA 6. Data Filter Command Bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 al 6 ml 5 1 4 s 3 1 2 f2 1 f1 0 f0 POR C22Ch Bit 7 (al): Clock recovery (CR) auto lock control, if set. CR will start in fast mode, then after locking it will automatically switch to slow mode. Bit 6 (ml): Clock recovery lock control 1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended) 0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended) Using the slow mode requires more accurate bit timing (see Data Rate Command). Bits 4 (s): Select the type of the data filter: s 0 1 Filter Type Digital filter Analog RC filter Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Note: Bit rate can not exceed 115 kpbs in this mode. Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used. 16 Si4420 Bits 2-0 (f2 to f0): DQD threshold parameter. Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well. 7. FIFO and Reset Mode Command Bit 15 1 14 1 13 0 12 0 11 1 10 0 9 1 8 0 7 f3 6 f2 5 f1 4 f0 3 0 2 al 1 ff 0 dr POR CA80h Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level. Bit 2 (al): Set the input of the FIFO fill start condition: al 0 1 Synchron pattern Always fill Note: Synchron pattern in microcontroller mode is 2DD4h. FIFO_LOGIC al FIFO_WRITE _EN FFOV SYNCHRON PATTERN ff FFIT ef* nFIFO_RESET er** Note: * For details see the Configuration Setting Command ** For deatils see the Power Management Command Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared. Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For more detailed description see the Reset modes section. Note: To restart the synchron pattern recognition, bit 1 should be cleared and set. 17 Si4420 8. Receiver FIFO Read Command Bit 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 POR B000h With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command. nSEL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SDI received bits out SDO FFIT in RX mode / RGIT otherwise MSB LSB Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command 9. AFC Command Bit 15 1 14 1 13 0 12 0 11 0 10 1 9 0 8 0 7 a1 6 a0 5 rl1 4 rl0 3 st 2 fi 1 oe 0 en POR C4F7h Bit 7-6 (a1 to a0): Automatic operation mode selector: a1 a0 0 0 0 1 1 1 0 1 Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving Keep the foffset value Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values: rl1 0 0 1 1 rl0 0 1 0 1 Max deviation No restriction +15 fres to -16 fres +7 fres to -8 fres +3 fres to -4 fres fres: 315, 433 MHz bands: 2.5 kHz 868 MHz band: 5 kHz 915 MHz band: 7.5 kHz Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block. Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement uncertainty is about the half. Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL. Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit. 18 Si4420 ATGL** BASEBAND SIGNAL IN ASAME*** FINE fi SE L Y 10MHz CLK /4 en DIGITAL LIMITER CLK OFFS 7 BIT 12 BIT I0 DIGITAL AFC I1 MUX IF IN>MaxDEV THEN OUT=MaxDEV 7 CORE LOGIC ENABLE CALCULATION VDI* rl1 to rl0 st STROBE oe F OUTPUT ENABLE Fcorr Corrected frequency parameter to synthesizer ELSE OUT=IN singals for auto operation modes Power-on reset (POR) RANGE LIMIT FREQ. OFFSET REGISTER IF IN