SI4430-A0-FMR

Si4430 Si4430 ISM T RANSCEIVER Features           Frequency Range = 900–960 MHz Sensitivity = –118 dBm +13 dBm Max Output Power Configurable –8 to +13 dBm Low Power Consumption 18.5 mA receive 28 mA @ +13 dBm transmit Data Rate = 1 to 128 kbps Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Digital RSSI Wake-on-radio Auto-frequency calibration (AFC)               Antenna diversity and TR switch control Configurable packet structure Preamble detector TX and RX 64 byte FIFOs Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 20-Pin QFN package FSK, GFSK, and OOK modulation Low BOM Power-on-reset (POR) Ordering Information: See page 150. Pin Assignments Silicon Laboratories’ Si4430 highly integrated, single chip wireless ISM transceiver is part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4430 offers advanced radio features including continuous frequency coverage from 900–960 MHz The Si4430’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–118 dBm) coupled with industry leading +20 dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, poweron-reset (POR), and GPIOs further reduce overall system cost and size. The Si4430’s digital receive architecture features a high-performance ADC and DSP based modem which performs demodulation, filtering, and packet handling for increased flexibility and performance. This digital architecture simplifies system design while allowing for the use of lower-end MCUs. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with ARIB regulations. Copyright © 2009 by Silicon Laboratories nIRQ nSEL 15 SCLK TX 2 14 SDI RXp 3 13 SDO RXn 4 12 VDD_DIG VR_IF 5 11 NC 7 8 9 10 VDR 6 GPIO_2 1 Metal Paddle Description Preliminary Rev. 0.4 5/09 20 19 18 17 16 VDD_RF GPIO_1 Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors Tag readers XOUT SDN        NC Remote control Home security & alarm Telemetry Personal data logging Toy control Tire pressure monitoring Wireless PC peripherals GPIO_0        XIN Si4430 Applications Patents pending Si4430 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si4430 nIRQ Xin nSEL RC 32K OSC RF LDO Xout VDD_RF SDN Functional Block Diagram PLL LDO VCO LDO VCO LPF CP 30M XTAL OSC PFD LBD TX PA Temp Sensor PA_RAMP PWR_CTRL N 8Bit ADC Delta Sigma Modulator ANTDIV TXRXSW PA_RAMP PWR_CTRL TXMOD Digital Logic SCLK SDI SDO VDD_DIG SPI, & Controller Digital Modem AGC Control Low Power Digital LDO Digital LDO RFp ADC RFn POR LNA BIAS GPIO_0 GPIO_1 GPIO_2 IF LDO PGA VR_IF 2 Preliminary Rev. 0.4 VR_DIG Mixers Si4430 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.4. Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.5. PN9 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.6. Synchronous vs. Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 5.7. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.8. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.9. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.4. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.5. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Preliminary Rev. 0.4 3 Si4430 7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13. Pin Descriptions: Si4430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 4 Preliminary Rev. 0.4 Si4430 L I S T OF F IGURES Figure 1. Si4430 RX/TX Direct-Tie Application Example .......................................................... 16 Figure 2. SPI Timing.................................................................................................................. 18 Figure 3. SPI Timing—READ Mode ..........................................................................................19 Figure 4. SPI Timing—Burst Write Mode .................................................................................. 19 Figure 5. SPI Timing—Burst Read Mode .................................................................................. 19 Figure 6. State Machine Diagram.............................................................................................. 20 Figure 7. TX Timing................................................................................................................... 24 Figure 8. RX Timing .................................................................................................................. 25 Figure 9. Frequency Deviation .................................................................................................. 28 Figure 10. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................29 Figure 11. FSK vs GFSK Spectrums......................................................................................... 32 Figure 12. Direct Synchronous Mode Example......................................................................... 34 Figure 13. Direct Asynchronous Mode Example ....................................................................... 34 Figure 14. FIFO Mode Example ................................................................................................ 35 Figure 15. PLL Synthesizer Block Diagram............................................................................... 37 Figure 16. FIFO Thresholds ...................................................................................................... 40 Figure 17. Packet Structure....................................................................................................... 41 Figure 18. Multiple Packets in TX Packet Handler .................................................................... 42 Figure 19. Required RX Packet Structure with Packet Handler Disabled ................................. 42 Figure 20. Multiple Packets in RX Packet Handler.................................................................... 42 Figure 21. Multiple Packets in RX with CRC or Header Error ................................................... 43 Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 45 Figure 23. POR Glitch Parameters............................................................................................ 53 Figure 24. General Purpose ADC Architecture ......................................................................... 55 Figure 25. ADC Differential Input Example—Bridge Sensor ..................................................... 56 Figure 26. ADC Differential Input Offset for Sensor Offset Coarse Compensation................... 57 Figure 27. Temperature Ranges using ADC8 ........................................................................... 59 Figure 28. WUT Interrupt and WUT Operation.......................................................................... 62 Figure 29. Low Duty Cycle Mode .............................................................................................. 63 Figure 30. RSSI Value vs. Input Power..................................................................................... 66 Figure 31. Split RF I/Os with Separated TX and RX Connectors—Schematic ......................... 67 Figure 32. Split RF I/Os with Separated TX and RX Connectors—Top .................................... 69 Figure 33. Split RF I/Os with Separated TX and RX Connectors—Top Silkscreen .................. 69 Figure 34. Split RF I/Os with Separated TX and RX Connectors—Bottom............................... 70 Figure 35. Sensitivity vs. Data Rate ..........................................................................................71 Figure 36. Receiver Selectivity.................................................................................................. 72 Figure 37. TX Modulation (40 kbps, 20 kHz Deviation)............................................................. 73 Figure 38. TX Unmodulated Spectrum (917 MHz) .................................................................... 73 Figure 39. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) ................. 74 Figure 40. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ........................... 74 Figure 41. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 75 Figure 42. QFN-20 Package Dimensions................................................................................ 153 Figure 43. QFN-20 Landing Pattern Dimensions .................................................................... 153 Preliminary Rev. 0.4 5 Si4430 L I S T OF TABLES Table 1. DC Characteristics .......................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8 Table 3. Receiver AC Electrical Characteristics1 .......................................................................9 Table 4. Transmitter AC Electrical Characteristics1 ................................................................. 10 Table 5. Auxiliary Block Specifications1 ...................................................................................11 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 12 Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 12 Table 8. Absolute Maximum Ratings ........................................................................................ 13 Table 9. Operating Modes ........................................................................................................17 Table 10. Serial Interface Timing Parameters .......................................................................... 18 Table 11. Operating Modes ...................................................................................................... 20 Table 12. Frequency Band Selection ....................................................................................... 27 Table 13. RX Packet Handler Configuration ............................................................................43 Table 14. Packet Handler Registers ......................................................................................... 44 Table 15. Minimum Receiver Settling Time .............................................................................. 46 Table 16. RX Modem Configurations for FSK and GFSK ........................................................ 47 Table 17. Filter Bandwidth Parameters .................................................................................... 49 Table 18. Channel Filter Bandwidth Settings ........................................................................... 50 Table 19. ndec[2:0] Settings ..................................................................................................... 51 Table 20. RX Modem Configuration for OOK with Manchester Disabled ................................. 52 Table 21. RX Modem Configuration for OOK with Manchester Enabled ................................. 52 Table 22. POR Parameters ...................................................................................................... 53 Table 23. Temperature Sensor Range ..................................................................................... 58 Table 24. Antenna Diversity Control ......................................................................................... 65 Table 25. Split RF I/Os Bill of Materials .................................................................................... 68 Table 26. Recommended Crystal Parameters ......................................................................... 76 Table 27. Register Descriptions ............................................................................................... 77 Table 28. Interrupt or Status 1 Bit Set/Clear Description ......................................................... 82 Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? ............. 82 Table 30. Interrupt or Status 2 Bit Set/Clear Description ........................................................ 84 Table 31. Detailed Description of Status Registers when not Enabled as Interrupts ............... 84 Table 32. Internal Analog Signals Available on the Analog Test Bus .................................... 124 Table 33. Internal Digital Signals Available on the Digital Test Bus .......................................125 6 Preliminary Rev. 0.4 Si4430 1. Electrical Specifications Table 1. DC Characteristics Parameter Symbol Conditions Min Typ — Units 1.8 3.0 — V Supply Voltage Range Vdd Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 — 10 — nA IStandby Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF1 — 400 — nA ISleep RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF1 — 800 — nA ISensor-LBD Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA ISensor-TS Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled1 — 600 — µA ITune Synthesizer and regulators enabled — 9.5 — mA — 18.5 — mA TUNE Mode Current RX Mode Current IRX TX Mode Current ITX_+13 txpow[2:0] = 11 (+13 dBm), VDD = 3.3 V — 28 — mA ITX_+1 txpow[2:0] = 00 (+1 dBm), VDD = 3.3 V — 18 — mA Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. Preliminary Rev. 0.4 7 Si4430 Table 2. Synthesizer AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units Synthesizer Frequency Range FSYNTH 900 — 960 MHz Synthesizer Frequency Resolution2 FRES — 312.5 — Hz Reference Frequency fREF fcrystal / 3 — 10 — MHz Reference Frequency Input Level2 fREF_LV When using reference frequency instead of crystal. Measured peak-to-peak (VPP) 0.7 — 1.6 V Synthesizer Settling Time2 tLOCK Measured from leaving Ready mode with XOSC running to any frequency including VCO Calibration — 200 — µs Residual FM2 FRMS Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) — 2 4 kHzRMS Phase Noise2 L(fM) F = 10 kHz — –80 — dBc/Hz F = 100 kHz — –90 — dBc/Hz F = 1 MHz — –115 — dBc/Hz F = 10 MHz — –130 — dBc/Hz Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. 8 Preliminary Rev. 0.4 Si4430 Table 3. Receiver AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units 900 — 960 MHz RX Frequency Range FSYNTH RX Sensitivity PRX_2 (BER < 0.1%) (2 kbps, GFSK, BT = 0.5, f = 5 kHz)2 — –118 — dBm PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz)2 — –107 — dBm PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz)2 — –103 — dBm PRX_125 (BER < 0.1%) (125 kbps, GFSK, BT = 0.5, f = 62.5 kHz)1 — –101 — dBm PRX_OOK (BER < 0.1%) (4.8 kbps, 350 kHz BW, OOK)2 — –110 — dBm (BER < 0.1%) (40 kbps, 400 kHz BW, OOK)1 — –102 — dBm 2.6 — 620 kHz RX Bandwidth2 BW Residual BER Performance2 PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm Input Intercept Point, 3rd Order2 IIP3RX — –20 — dBm LNA Input Impedance2 (Unmatched, measured differentially across RX input pins) f1 = 915 MHz, f2 = 915 MHz, P1 = P2 = –40 dBm RIN-RX 915 MHz — 40–55 —  — ±0.5 — dB — –31 — dB — –35 — dB — –40 — dB RSSI Resolution 1-Ch Offset Selectivity (BER < 0.1%) 2 RESRSSI C/I1-CH 2-Ch Offset Selectivity2 (BER < 0.1%) C/I2-CH  3-Ch Offset Selectivity2 (BER < 0.1%) C/I3-CH Blocking at 1 MHz2 1MBLOCK 2 4MBLOCK MHz2 8MBLOCK Blocking at 4 MHz Blocking at 8 Image Rejection 2 Spurious Emissions 2 Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps F = 20 kHz GFSK with BT = 0.5 — –52 — dB — –56 — dB — –63 — dB ImREJ IF=937 kHz — –30 — dB POB_RX1 Measured at RX pins (LO feed through) — — –54 dBm Notes: 1. All specification guaranteed by production test unless otherwise noted. 2. Guaranteed by qualification. Preliminary Rev. 0.4 9 Si4430 Table 4. Transmitter AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units TX Frequency Range1 FSYNTH 900 — 960 MHz FSK Modulation Data Rate2 DRFSK 1 — 128 kbps OOK Modulation Data Rate2 DROOK 1.2 — 40 kbps Modulation Deviation1 Δf ±320 kHz Modulation Deviation Resolution ΔfRES Output Power Range1 PTX TX RF Output Steps2 TX RF Output Level Variation vs. Voltage2 Production tests maximum limit of 320 kHz ±0.625 — 0.625 — kHz Power control by txpow[2:0] Register Production test at txpow[2:0] = 111 Tested at 915 MHz –8 — +13 dBm PRF_OUT controlled by txpow[2:0] Register — 3 — dB PRF_V Measured from VDD=3.6 V to VDD=1.8 V — 2 — dB TX RF Output Level2 Variation vs. Temperature PRF_TEMP –40 to +85 C — 2 — dB TX RF Output Level Variation vs. Frequency2 PRF_FREQ Measured across any one frequency band — 1 — dB Transmit Modulation Filtering2 B*T Gaussian Filtering Bandwith Time Product — 0.5 — Spurious Emissions2 POB-TX1 POUT = 11 dBm, Frequencies