S i4464/63/61 / 6 0
Power supply = 1.8 to 3.6 V
Excellent selectivity performance
60 dB adjacent channel
75 dB blocking at 1 MHz
Antenna diversity and T/R switch control
Highly configurable packet handler
TX and RX 64 byte FIFOs
Auto frequency control (AFC)
Automatic gain control (AGC)
Low BOM
Low battery detector
Temperature sensor
20-Pin QFN package
IEEE 802.15.4g compliant
FCC Part 90 Mask D, FCC part 15.247,
15,231, 15,249, ARIB T-108, T-96, T-67,
RCR STD-30, China regulatory
ETSI Class-I Operation with SAW
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Frequency range = 119–1050 MHz
Receive sensitivity = –126 dBm
Modulation
(G)FSK, 4(G)FSK, (G)MSK
OOK
Max output power
+20 dBm (Si4464/63)
+16 dBm (Si4461)
+13 dBm (Si4460)
PA support for +27 or +30 dBm
Low active power consumption
10/13 mA RX
18 mA TX at +10 dBm (Si4460)
Ultra low current powerdown modes
30 nA shutdown, 50 nA standby
Data rate = 100 bps to 1 Mbps
Fast wake and hop times
Applications
Smart metering (802.15.4g & MBus)
Remote control
Home security and alarm
Telemetry
Garage and gate openers
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
Electronic shelf labels
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Pin Assignments
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H I G H -P E R F O R M A N C E, L O W -C U R R E N T T R A N SC E I V E R
Patents pending
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Silicon Laboratories' Si446x devices are high-performance, low-current
transceivers covering the sub-GHz frequency bands from 119 to 1050 MHz. The
radios are part of the EZRadioPRO® family, which includes a complete line of
transmitters, receivers, and transceivers covering a wide range of applications. All
parts offer outstanding sensitivity of –126 dBm while achieving extremely low
active and standby current consumption. The Si4463/61/60 offers frequency
coverage in all major bands. The Si4464 offers frequency coverage in bands not
covered by Si4463/61/60. Typically, these are non-standard frequencies or
licensed frequency bands. The Si446x includes optimal phase noise, blocking,
and selectivity performance for narrow band and licensed band applications, such
as FCC Part90 and 169 MHz wireless Mbus. The 60 dB adjacent channel
selectivity with 12.5 kHz channel spacing ensures robust receive operation in
harsh RF conditions, which is particularly important for narrow band operation.
The Si4464/63 offers exceptional output power of up to +20 dBm with outstanding
TX efficiency. The high output power and sensitivity results in an industry-leading
link budget of 146 dB allowing extended ranges and highly robust communication
links. The Si4460 active mode TX current consumption of 18 mA at +10 dBm and
RX current of 10 mA coupled with extremely low standby current and fast wake
times ensure extended battery life in the most demanding applications. The
Si4464/63 can achieve up to +27 dBm output power with built-in ramping control
of a low-cost external FET. The devices can meet worldwide regulatory standards:
FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g
and WMbus smart metering standards. The devices are highly flexible and can be
configured via the Wireless Development Suite (WDS) available on the Silicon
Labs web site.
Rev 1.3 7/20
Copyright © 2020 by Silicon Laboratories
Si4464/63/62/61/60
Si4 464/63/ 61/ 60
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Functional Block Diagram
Freq. Range
Max Output
Power
TX Current
RX Current
Narrow Band
Support
Image Cal
Si4464
Banded
119–960 MHz
+20 dBm
915 MHz: 85 mA
10.6/13.6 mA
Si4463
Major bands
142-1050 MHz
+20 dBm
169 MHz: 70 mA
915 MHz: 85 mA
10/13 mA
Si4461
Major bands
142-1050 MHz
+16 dBm
+13 dBm: 29 mA
+14 dBm: 33 mA
10/13 mA
Si4460
Major bands
142-1050 MHz
+13 dBm
+10 dBm: 18 mA
+11 dBm: 20 mA
10/13 mA
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Product
2
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
TA B L E O F C O N T E N T S
Section
Page
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. MODEM_MOD_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.3. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.4. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1. RX Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.2. RX Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.4. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8.2. Low Duty Cycle Mode (Auto RX Wake-Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . .44
8.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8.5. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9. Pin Descriptions: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
11. Package Outline: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
12. PCB Land Pattern: Si4464/63/61/60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.1. Si4464/63/61/60 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Rev 1.3
3
Si4 464/63/ 61/ 60
1. Electrical Specifications
Table 1. DC Characteristics1
Supply Voltage
Range
VDD
Unit
1.8
3.3
3.6
V
—
30
—
nA
—
50
—
nA
—
900
—
nA
—
1.7
—
μA
RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF
ISleepXO
Sleep current using an external 32 kHz crystal.2
ISensor
Low battery detector ON, register values maintained,
and all other blocks OFF
—
1
—
μA
IReady
Crystal Oscillator and Main Digital Regulator ON,
all other blocks OFF
—
1.8
—
mA
ITune_RX
RX Tune, High Performance Mode
—
7.2
—
mA
ITune_TX
TX Tune, High Performance Mode
—
8
—
mA
IRXH
High Performance Mode
—
13.7
—
mA
—
10.7
—
mA
+20 dBm output power, class-E match, 915 MHz,
3.3 V
—
85
—
mA
+20 dBm output power, class-E match, 460 MHz,
3.3 V
—
75
—
mA
+20 dBm output power, square-wave match,
169 MHz, 3.3 V
—
70
—
mA
ITX_+16
+16 dBm output power, class-E match, 868 MHz,
3.3 V2
—
43
—
mA
ITX_+14
+14 dBm output power, Switched-current match,
868 MHz, 3.3 V2
—
37
—
mA
ITX_+13
+13 dBm output power, switched-current match,
868 MHz, 3.3 V2
—
29
—
mA
ITX_+10
+10 dBm output power, Class-E match, 868 MHz,
3.3 V2
—
18
—
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D
ISleepRC
IRXL
TX Mode Current
(Si4460)
Max
Register values maintained and RC
oscillator/WUT OFF
RX Mode Current
TX Mode Current
(Si4461)
Typ
IStandby
-LBD
TX Mode Current
(Si4464/63)
RC Oscillator, Main Digital Regulator,
and Low Power Digital Regulator OFF
Min
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Power Saving Modes IShutdown
TUNE Mode Current
Test Condition
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Parameter
Low Power
Mode2
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Notes:
1. All specifications guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 14.
2. Guaranteed by qualification. Qualification test conditions are listed in the “Qualification Test Conditions” section in "1.1.
Definition of Test Conditions" on page 14.
4
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
Table 2. Synthesizer AC Electrical Characteristics1
Symbol
Synthesizer Frequency
Range (Si4463/61/60)
Test Condition
FSYN
Min
Typ
Max
Unit
850
—
1050
MHz
420
284
142
Synthesizer Frequency
Range (Si4464)
FSYN
705
—
525
MHz
—
350
MHz
—
175
MHz
—
960
MHz
—
479
MHz
D
353
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Parameter
—
159
MHz
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119
—
28.6
—
Hz
FRES-525
420–525 MHz
—
14.3
—
Hz
FRES-350
283–350 MHz
—
9.5
—
Hz
FRES-175
142–175 MHz
—
4.7
—
Hz
705–960 MHz
—
28.6
—
Hz
470–639 MHz
—
19.1
—
Hz
FRES-479
353–479 MHz
—
14.3
—
Hz
FRES-319
235–319 MHz
—
9.5
—
Hz
FRES-239
177–239 MHz
—
7.1
—
Hz
FRES-159
119–159 MHz
—
4.7
—
Hz
tLOCK
Measured from exiting Ready mode with
XOSC running to any frequency.
Including VCO Calibration.
—
50
—
μs
F = 10 kHz, 460 MHz, High Perf Mode
—
–106
—
dBc/Hz
F = 100 kHz, 460 MHz, High Perf Mode
—
–110
—
dBc/Hz
F = 1 MHz, 460 MHz, High Perf Mode
—
–123
—
dBc/Hz
F = 10 MHz, 460 MHz, High Perf Mode
—
–130
—
dBc/Hz
FRES-639
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Phase Noise4
MHz
850–1050 MHz
FRES-960
Synthesizer Settling Time4
319
FRES-960
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Synthesizer Frequency
Resolution (Si4464)3
—
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Synthesizer Frequency
Resolution3
177
L(fM)
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the “Production Test Conditions” section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Default API setting for modulation deviation resolution is double the typical value specified.
4. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 14.
Rev 1.3
5
Si4 464/63/ 61/ 60
Table 3. Receiver AC Electrical Characteristics1
Symbol
RX Frequency
Range (Si4463/61/60)
Test Condition
FRX
Min
Typ
Max
Unit
850
—
1050
MHz
420
—
525
MHz
284
142
RX Frequency
Range (Si4464)
FRX
705
353
—
350
MHz
—
175
MHz
—
960
MHz
—
479
MHz
—
319
MHz
159
MHz
D
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Parameter
119
—
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the
"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450–470 MHz band.
5. Guaranteed by bench characterization.
6
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
Table 3. Receiver AC Electrical Characteristics1 (Continued)
Min
Typ
Max
Unit
PRX_0.5
(BER < 0.1%)
(500 bps, GFSK, BT = 0.5,
f = 250Hz)3
—
–126
—
dBm
PRX_40
(BER < 0.1%)
(40 kbps, GFSK, BT = 0.5,
f = 20 kHz)3
—
PRX_100
(BER < 0.1%)
(100 kbps, GFSK, BT = 0.5,
f = 50 kHz)1
—
PRX_125
(BER < 0.1%)
(125 kbps, GFSK, BT = 0.5,
f = 62.5 kHz)3
—
PRX_500
(BER < 0.1%)
(500 kbps, GFSK, BT = 0.5,
f = 250 kHz)3
PRX_9.6
—
dBm
–106
—
dBm
–105
—
dBm
—
–97
—
dBm
(PER 1%)
(9.6 kbps, 4GFSK, BT = 0.5,
f = kHz)3,4
—
–110
—
dBm
PRX_1M
(PER 1%)
(1 Mbps, 4GFSK, BT = 0.5,
inner deviation = 83.3 kHz)3,4
—
–88
—
dBm
PRX_OOK
(BER < 0.1%, 4.8 kbps, 350 kHz BW,
OOK, PN15 data)3
—
–110
—
dBm
(BER < 0.1%, 40 kbps, 350 kHz BW,
OOK, PN15 data)3
—
–104
—
dBm
(BER < 0.1%, 120 kbps, 350 kHz BW,
OOK, PN15 data)3
—
–99
—
dBm
1.1
—
850
kHz
—
0
0.1
ppm
—
±0.5
—
dB
BER Variation vs Power
Level3
PRX_RES
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Up to +5 dBm Input Level
om
BW
D
–110
RX Channel Bandwidth5
RSSI Resolution
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Test Condition
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RX Sensitivity
Symbol
fo
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Parameter
RESRSSI
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the
"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450–470 MHz band.
5. Guaranteed by bench characterization.
Rev 1.3
7
Si4 464/63/ 61/ 60
Table 3. Receiver AC Electrical Characteristics1 (Continued)
Test Condition
Min
Typ
Max
Unit
1-Ch Offset Selectivity,
169 MHz3
C/I1-CH
—
–60
—
dB
1-Ch Offset Selectivity,
450 MHz3
C/I1-CH
1-Ch Offset Selectivity,
868 / 915 MHz3
C/I1-CH
Desired Ref Signal 3 dB above sensitivity, BER < 0.1%. Interferer is CW, and
desired is modulated with 2.4 kbps
F = 1.2 kHz GFSK with BT = 0.5, RX
channel BW = 4.8 kHz,
channel spacing = 12.5 kHz
Blocking 1 MHz Offset3
1MBLOCK
—
Blocking 8 MHz Offset3
8MBLOCK
Desired Ref Signal 3 dB above sensitivity, BER = 0.1%. Interferer is CW, and
desired is modulated with 2.4 kbps,
F = 1.2 kHz GFSK with BT = 0.5,
RX channel BW = 4.8 kHz
No image rejection calibration. Rejection at the image frequency.
IF = 468 kHz
Image Rejection3
ImREJ
—
—
With image rejection calibration in
Si446x. Rejection at the image frequency. IF = 468 kHz
–58
—
dB
–53
—
dB
–75
—
dB
–84
—
dB
D
—
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Symbol
—
35
—
dB
—
55
—
dB
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Parameter
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Guaranteed by qualification. BER is specified for the 450–470 MHz band. Qualification test conditions are listed in the
"Qualification Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
4. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. PER and BER tested
in the 450–470 MHz band.
5. Guaranteed by bench characterization.
8
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
Table 4. Transmitter AC Electrical Characteristics1
Symbol
Test Condition
Min
Typ
Max
Unit
850
—
1050
MHz
—
525
MHz
—
350
MHz
—
175
MHz
—
960
MHz
—
479
MHz
177
—
319
MHz
119
—
159
MHz
0.1
—
500
kbps
0.2
—
1000
kbps
0.1
—
120
kbps
—
1.5
—
MHz
420
FTX
284
142
D
705
353
TX Frequency
Range (Si4464)
4(G)FSK Data Rate3,4
DR4FSK
OOK Data Rate3,4
DROOK
850–1050 MHz
f525
420–525 MHz
—
750
—
kHz
f350
283–350 MHz
—
500
—
kHz
f175
142–175 MHz
—
250
—
kHz
f960
705–960 MHz
—
1.5
—
MHz
f479
353–479 MHz
—
750
—
kHz
f319
235–319 MHz
—
500
—
kHz
f239
177–239 MHz
—
375
—
kHz
f159
119–159 MHz
—
250
—
kHz
m
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f960
om
Modulation Deviation
Range (Si4464)3
fo
r
DRFSK
N
ew
FTX
(G)FSK Data Rate3,4
Modulation Deviation
Range3
es
ig
ns
Parameter
TX Frequency
Range (Si4463/61/60)
N
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ec
Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 14.
4. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
5. Default API setting for modulation deviation resolution is double the typical value specified.
6. Output power is dependent on matching components and board layout.
Rev 1.3
9
Si4 464/63/ 61/ 60
Table 4. Transmitter AC Electrical Characteristics1 (Continued)
Typ
Max
Unit
FRES-960
850–1050 MHz
—
28.6
—
Hz
FRES-525
420–525 MHz
—
14.3
—
Hz
FRES-350
283–350 MHz
—
9.5
—
Hz
FRES-175
142–175 MHz
—
4.7
—
Hz
FRES-960
705–960 MHz
—
28.6
—
Hz
FRES-479
353–479 MHz
—
14.3
—
Hz
FRES-319
235–319 MHz
—
9.5
—
Hz
FRES-239
177–239 MHz
7.1
—
Hz
FRES-159
119–159 MHz
—
4.7
—
Hz
–20
—
+20
dBm
–40
—
+16
dBm
–40
—
+13
dBm
Output Power Range
(Si4464/63)6
PTX
Output Power Range
(Si4461)6
PTX61
Output Power Range
(Si4460)6
PTX60
TX RF Output Steps3
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Min
D
Modulation Deviation
Resolution (Si4464)3
Test Condition
—
N
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Modulation Deviation
Resolution2,5
Symbol
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Parameter
Using switched current match within
6 dB of max power
—
0.1
—
dB
TX RF Output Level3
Variation vs. Temperature
PRF_TEMP
–40 to +85 C
—
1
—
dB
TX RF Output Level
Variation vs. Frequency3
PRF_FREQ
Measured across 902–928 MHz
—
0.5
—
dB
B*T
Gaussian Filtering Bandwith Time
Product
—
0.5
—
Transmit Modulation
Filtering3
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PRF_OUT
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. For applications that use the major bands covered by Si4463/61/60, customers should use those parts instead of
Si4464.
3. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 14.
4. The maximum data rate is dependant on the XTAL frequency and is calculated as per the formula:
Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz).
5. Default API setting for modulation deviation resolution is double the typical value specified.
6. Output power is dependent on matching components and board layout.
10
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
Table 5. Auxiliary Block Specifications1
Test Condition
Min
Typ
Max
Unit
4.5
—
ADC
Codes/
°C
Temperature Sensor
Sensitivity2
TSS
—
Low Battery Detector
Resolution
LBDRES
—
Temperature Sensor
Conversion2
XTAL Range4
FMC
Configurable to Fxtal or Fxtal
divided by 2, 3, 7.5, 10, 15, or
30 where Fxtal is the reference
XTAL frequency. In addition,
32.768 kHz is also supported.
32.768K
TEMPCT
Programmable setting
—
XTALRange
30 MHz XTAL Cap
Resolution2
32 kHz Accuracy using
Internal RC Oscillator2
POR Reset Time
mV
—
Fxtal
Hz
—
ms
32
MHz
3
—
250
—
μs
—
70
—
fF
—
2
—
sec
32KRCRES
—
2500
—
ppm
tPOR
—
—
5
ms
30MRES
t32k
Using XTAL and board layout in
reference design. Start-up time
will vary with XTAL type and
board layout.
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32 kHz XTAL Start-Up
Time2
t30M
—
25
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30 MHz XTAL Start-Up Time
50
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Microcontroller Clock
Output Frequency Range3
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Symbol
D
Parameter
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Notes:
1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are
listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 14.
2. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.
Definition of Test Conditions" on page 14.
3. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz and 32.768 kHz. Other frequencies tested in
bench characterization.
4. XTAL Range tested in production using an external clock source (similar to using a TCXO).
Rev 1.3
11
Si4 464/63/ 61/ 60
Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1
Rise
Fall Time3,4
Symbol
Test Condition
Min
Typ
Max
Unit
TRISE
0.1 x VDD to 0.9 x VDD,
CL = 10 pF,
DRV = HH
—
2.3
—
ns
TFALL
0.9 x VDD to 0.1 x VDD,
CL = 10 pF,
DRV = HH
—
CIN
—
Logic High Level Input Voltage
VIH
VDD x 0.7
Logic Low Level Input Voltage
VIL
—
Input Current
IIN
0 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be
smaller also.
Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be
10 μA x 10k = 100 mV.
Number
Command
Summary
0x2200
PA_MODE
0x2201
PA_PWR_LVL
0x2202
PA_BIAS_CLKDUTY
Sets PA type.
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Adjust TX power in fine steps.
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Adjust TX power in coarse steps
and optimizes for different
match configurations.
0x2203
Changes the ramp up/down time
of the PA.
PA_TC
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TX Power(dBm)
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5.4.1. Si4464/63: +20 dBm PA
The +20 dBm configuration utilizes a class-E matching configuration. Typical performance for the 900 MHz band
for output power steps, voltage, and temperature are shown in Figures 10–12. The output power is changed in 128
steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer
to the PA Matching application note.
TX Power vs. PA_PWR_LVL
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
0
10
20
30
40
50
60
70
80
90 100 110 120
PA_PWR_LVL
Figure 10. +20 dBm TX Power vs. PA_PWR_LVL
Rev 1.3
35
Si4 464/63/ 61/ 60
TX Power vs. VDD
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20
18
16
14
12
10
1.8
2
2.2
2.4
2.6
2.8
3
3.2
D
TX Power (dBm)
22
3.4
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Supply Voltage (VDD)
Figure 11. +20 dBm TX Power vs. VDD
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TX Power vs Temp
20
19.5
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TX Power (dBm)
20.5
19
18.5
18
-40 -30 -20 -10
0
10
20
30
40
50
60
Temperature (C)
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Figure 12. +20 dBm TX Power vs. Temp
36
Rev 1.3
70
80
3.6
S i4 4 6 4 /6 3 /6 1/60
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5.4.2. Si4461 +16 dBm PA
The Si4461 PA can utilize different matches to optimize the performance for 16, 14, 13 dBm, or a lower power. A
class-E match is recommended for 16 dBm to maximize the efficiency and battery life. For 13 and 14 dBm, a
switched current match is recommended to provide optimal performance over VDD and temperature variation.
Typical performance for the 900 MHz band for output power steps, voltage, and temperature are shown in Figures
13 and 14. The output power is changed in 128 steps through the PA_PWR_LVL API. For detailed matching
values, BOM, and performance at other frequencies, refer to “AN627: Si4460/61 Low-Power PA Matching.
om
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Figure 13. +13 dBm TX Power vs. PA_PWR_LVL
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Figure 14. +13 dBm TX Power vs. Supply Voltage (VDD)
Rev 1.3
37
Si4 464/63/ 61/ 60
5.5. Crystal Oscillator
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The Si446x includes an integrated crystal oscillator with a fast start-up time of less than 250 μs. The design is
differential with the required crystal load capacitance integrated on-chip to minimize the number of external
components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is
designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API
boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the
frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with
various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal
load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is
11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for
crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in
Figure 15.
ec
Figure 15. Capacitor Bank Frequency Offset Characteristics
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Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to
the XIN pin. The incoming clock signal is recommended to have a peak-to-peak swing in the range of 600 mV to
1.4 V and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4 V peak-to-peak, then dc
coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak.
The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the
POWER_UP command should be invoked with the TCXO option whenever external drive is used.
38
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
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Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 16. Writing to
command Register 66h loads data into the TX FIFO, and reading from command Register 77h reads data from the
RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the “TX_FIFO_EMPTY”
property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data
is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The
RX FIFO has one programmable threshold, which is programmed by setting the “RX_FIFO_FULL” property. When
the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via
the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold
indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both
the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command.
Figure 16. TX and RX FIFOs
6.2. Packet Handler
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When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual
fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can
be configured to be automatically added to the data payload. The fields needed for packet generation normally
change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload
in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between
the microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The
general packet structure is shown in Figure 17. Any or all of the fields can be enabled and checked by the internal
packet handler.
Figure 17. Packet Handler Structure
Rev 1.3
39
Si4 464/63/ 61/ 60
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The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The
general functions of the packet handler include the following:
Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal)
Detection of Sync word in RX mode (SYNC_OK signal)
Detection of valid packets in RX mode (PKT_VALID signal)
Detection of CRC errors in RX mode (CRC_ERR signal)
Data de-whitening and/or Manchester decoding (if enabled) in RX mode
Match/Header checking in RX mode
Storage of Data Field bytes into FIFO memory in RX mode
Construction of Preamble field in TX mode
Construction of Sync field in TX mode
Construction of Data Field from FIFO memory in TX mode
Construction of CRC field (if enabled) in TX mode
Data whitening and/or Manchester encoding (if enabled) in TX mode
For details on how to configure the packet handler, see “AN626: Packet Handler Operation for Si446x RFICs”.
40
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
7. RX Modem Configuration
The Si446x can easily be configured for different data rate, deviation, frequency, etc. by using the WDS settings
calculator, which generates an initialization file for use by the host MCU.
es
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8. Auxiliary Blocks
8.1. Wake-up Timer and 32 kHz Clock Source
N
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The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The
wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL.
The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG
property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the
GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated
on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then
need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response
register. The formula for calculating the Wake-Up Period is as follows:
WUT_R
42
WUT = WUT_M ----------------------------- ms
32 768
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The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator
is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the
recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration
period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the
32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration
needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD
results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL
parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging +
XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is
typically less than 10 ppm.
Rev 1.3
41
Si4 464/63/ 61/ 60
Table 15. WUT Specific Commands and Properties
Description
Requirements/Notes
GLOBAL_WUT_CONFIG
GLOBAL WUT configuration
WUT_EN—Enable/disable wake up timer.
WUT_LBD_EN—Enable/disable low battery detect
measurement on WUT interval.
WUT_LDC_EN:
0 = Disable low duty cycle operation.
1 = RX LDC operation
treated as wake up START_RX
WUT state is used
2 = TX LDC operation
treated as wakeup START_TX
WUT state is used
CAL_EN—Enable calibration of the 32 kHz RC
oscillator
WUT_CAL_PERIOD[2:0]—Sets calibration period.
GLOBAL_WUT_M_15_8
Sets HW WUT_M[15:8]
WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_ WUT_M_7_0
Sets HW WUT_M[7:0]
WUT_M—Parameter to set the actual wakeup time.
See equation above.
GLOBAL_WUT_R
Sets WUT_R[4:0]
Sets WUT_SLEEP to choose
WUT state
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API Properties
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WUT_R—Parameter to set the actual wakeup time.
See equation above.
WUT_SLEEP:
0 = Go to ready state after WUT
1 = Go to sleep state after WUT
GLOBAL_WUT_LDC
Sets FW internal WUT_LDC
WUT_LDC—Parameter to set the actual wakeup
time. See equation in "8.2. Low Duty Cycle Mode
(Auto RX Wake-Up)" on page 43.
Table 16. WUT Related API Commands and Properties
Description
om
Command/Property
INT_CTL_ENABLE
R
ec
INT_CTL_CHIP_ENABLE
N
ot
GLOBAL_CLK_CFG
GPIO_PIN_CFG
START_RX/TX
42
Requirements/Notes
WUT Interrupt Enable
Interrupt enable property
CHIP_INT_STATUS_EN—Enables chip status
interrupt.
Chip interrupt enable property WUT_EN—Enables WUT interrupt.
32 kHz Clock Source Selection
Clock configuration options
CLK_32K_SEL[2:0]—Configuring the source of
WUT.
WUT Interrupt Output
Host can enable interrupt on
WUT expire
GPIOx_MODE[5:0] = 14 and
NIRQ_MODE[5:0] = 39.
RX/TX Operation
START RX/TX when wake up START = 1.
timer expire
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
8.2. Low Duty Cycle Mode (Auto RX Wake-Up)
WUT_R
42
LDC = WUT_LDC ----------------------------- ms
32 768
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The low duty cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid signal is
available or to enable the transmitter to send a packet. It allows low average current polling operation by the Si446x
for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via the
GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined by the
following formula:
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where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in
conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section.
Figure 18. RX and TX LDC Sequences
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The basic operation of RX LDC mode is shown in Figure 19. The receiver periodically wakes itself up to work on
RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is detected, or an entire
packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at the end of LDC mode duration
and remains in that mode until the beginning of the next wake-up period. If a valid preamble or sync word is
detected, the receiver delays the LDC mode duration to receive the entire packet. If a packet is not received during
two LDC mode durations, the receiver returns to the WUT state at the last LDC mode duration until the beginning
of the next wake-up period.
Figure 19. Low Duty Cycle Mode for RX
N
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In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a
packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After
transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time
expires.
Rev 1.3
43
Si4 464/63/ 61/ 60
8.3. Temperature, Battery Voltage, and Auxiliary ADC
GET_ADC_READING
Command
7
6
5
4
3
CMD
2
0
0
GPIO_ATT[3:0]
Stream
GET_ADC_READING Reply
7
6
5
CTS
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UDTIME[3:0]
4
3
2
1
GPIO_ADC
GPIO_ADC[15:8]
GPIO_ADC[7:0]
BATTERY_ADC[15:8]
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BATTERY_ADC
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CTS[7:0]
GPIO_ADC
BATTERY_ADC
BATTERY_ADC[7:0]
TEMP_ADC
TEMP_ADC[15:8]
TEMP_ADC
TEMP_ADC[7:0]
RESERVED
Reserved
RESERVED
Reserved
Parameters
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TEMPERATURE_EN
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0 = Do not perform ADC conversion of temperature. This will read 0 value in reply TEMPERATURE.
1 = Perform ADC conversion of temperature. This results in TEMP_ADC.
Temp (°C) = TEMP_ADC[15:0] x 568/2560 – 297
BATTERY_VOLTAGE_EN
0 = Don't do ADC conversion of battery voltage, will read 0 value in reply BATTERY_ADC
1 = Do ADC conversion of battery voltage, results in BATTERY_ADC. Vbatt = 3*BATTERY_ADC/1280
ADC_GPIO_EN
0 = Don't do ADC conversion on GPIO, will read 0 value in reply
1 = Do ADC conversion of GPIO, results in GPIO_ADC. Vgpio = GPIO_ADC/GPIO_ADC_DIV where
GPIO_ADC_DIV is defined by GPIO_ATT selection.
ADC_GPIO_PIN[1:0] - Select GPIOx pin. The pin must be set as input.
0 = Measure voltage of GPIO0
1 = Measure voltage of GPIO1
2 = Measure voltage of GPIO2
3 = Measure voltage of GPIO3
UDTIME[7:4] - ADC conversion Time = SYS_CLK / 12 / 2^(UDTIME + 1). Defaults to 0xC if ADC_CFG is 0.
44
0
0 TEMPERATURE_EN BATTERY_VOLTAGE_EN ADC_GPIO_EN ADC_GPIO_PIN[1:0]
ADC_CFG
Reply
1
D
0x14
ADC_EN
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The Si446x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal
temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves
11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input
voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first
sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or
temp. The temperature sensor accuracy at 25 °C is typically ±2 °C.
Command Stream
Rev 1.3
0
S i4 4 6 4 /6 3 /6 1/60
GPIO_ADC[15:0]
- ADC value of voltage on GPIO
- ADC value of battery voltage
TEMP_ADC[15:0] - ADC value of temperature sensor voltage
RESERVED[7:0] - RESERVED FOR FUTURE USE
RESERVED[7:0] - RESERVED FOR FUTURE USE
BATTERY_ADC[15:0]
8.4. Low Battery Detector
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Response
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Selecting shorter conversion times will result in lower ADC resolution and longer times will result in higher ADC
resolution.
GPIO_ATT[3:0] - Sets attenuation of gpio input voltage when vgpio measured. Defaults to 0xC if ADC_CFG is 0.
0x0 = ADC range 0 to 0.8V. GPIO_ADC_DIV = 2560
0x4 = ADC range 0 to 1.6V. GPIO_ADC_DIV = 1280
0x8 = ADC range 0 to 2.4V. GPIO_ADC_DIV = 853.33
0x9 = ADC range 0 to 3.6V. GPIO_ADC_DIV = 426.66
0xC = ADC range 0 to 3.2V. GPIO_ADC_DIV = 640
8.5. Antenna Diversity
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The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not
available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the
auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will
be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in
GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of
1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the
nIRQ pin or enabled as a direct function on one of the GPIOs.
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To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use
a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX
mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the
preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of
that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports
antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an
external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of
these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The
antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna
diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to
forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth
between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna
selection is 8 bytes.
Rev 1.3
45
Si4 464/63/ 61/ 60
Pin Name
SDN
I
2
RXp
I
3
RXn
I
4
TX
5
NC
6
VDD
7
TXRAMP
8
VDD
N
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10
11
O
GPIO1
nIRQ
Shutdown Input Pin.
0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode.
When SDN = 1, the chip will be completely shut down, and the contents of the
registers will be lost.
Differential RF Input Pins of the LNA.
See application schematic for example matching network.
Transmit Output Pin.
The PA output is an open-drain connection, so the L-C match must supply
VDD (+3.3 VDC nominal) to this pin.
No Connect. Not connected internally to any circuitry.
VDD
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GPIO0
Description
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1
9
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I/0
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Pin
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9. Pin Descriptions: Si4464/63/61/60
VDD
I/O
I/O
O
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
Programmable Bias Output with Ramp Capability for External FET PA.
See "5.4. Transmitter (TX)" on page 34.
+1.8 to +3.6 V Supply Voltage Input to Internal Regulators.
The recommended VDD supply voltage is +3.3 V.
General Purpose Digital I/O.
May be configured through the registers to perform various functions including:
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
General Microcontroller Interrupt Status Output.
When the Si4463/61 exhibits any one of the interrupt events, the nIRQ pin will
be set low = 0. The Microcontroller can then determine the state of the interrupt by reading the interrupt status. No external resistor pull-up is required, but
it may be desirable if multiple interrupt lines are connected.
Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
Pin
Pin Name
I/0
Description
SCLK
I
13
SDO
O
0–VDD V Digital Output.
Provides a serial readback function of the internal control registers.
I
Serial Data Input.
0–VDD V digital input. This pin provides the serial data stream for the 4-line
serial data bus.
I
Serial Interface Select Input.
0–VDD V digital input. This pin provides the Select/Enable function for the
4-line serial data bus.
15
nSEL
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12
Serial Clock Input.
0–VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si4463/61 on positive edge transitions.
XOUT
O
17
XIN
I
Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal, or connect to an external source.
18
GND
GND
19
GPIO2
20
GPIO3
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PADDLE_GND
Connect to PCB ground.
I/O
I/O
GND
General Purpose Digital I/O.
May be configured through the registers to perform various functions, including
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
The exposed metal paddle on the bottom of the Si446x supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si446x.
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Crystal Oscillator Output.
Connect to an external 25 to 32 MHz crystal, or leave floating when driving
with an external source on XIN.
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Si4 464/63/ 61/ 60
10. Ordering Information
Package Type
ISM EZRadioPRO Transceiver
QFN-20
Pb-free
–40 to 85 °C
Si4463-Bxx-FM
ISM EZRadioPRO Transceiver
QFN-20
Pb-free
–40 to 85 °C
Si4461-Bxx-FM
ISM EZRadioPRO Transceiver
QFN-20
Pb-free
–40 to 85 °C
Si4460-Bxx-FM
ISM EZRadioPRO Transceiver
QFN-20
Pb-free
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Notes:
1. Add an “(R)” at the end of the device part number to denote tape and reel option.
2. For Bxx, the first “x” indicates the ROM version, and the second “x” indicates the FW version in OTP.
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Operating
Temperature
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Description
Part Number1,2
Rev 1.3
–40 to 85 °C
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11. Package Outline: Si4464/63/61/60
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Figure 20 illustrates the package details for the Si446x. Table 17 lists the values for the dimensions shown in the
illustration.
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Figure 20. 20-Pin Quad Flat No-Lead (QFN)
Rev 1.3
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Si4 464/63/ 61/ 60
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
0.18
0.25
D
D2
4.00 BSC
2.45
2.60
e
0.50 BSC
E
4.00 BSC
2.45
2.60
L
0.30
0.40
2.75
2.75
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0.15
bbb
0.15
ccc
0.10
ddd
0.10
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0.30
D
b
0.20 REF
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Table 17. Package Dimensions
0.50
0.08
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Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
Variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
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Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
12. PCB Land Pattern: Si4464/63/61/60
Figure 21. PCB Land Pattern
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Figure 21 illustrates the PCB land pattern details for the Si446x. Table 18 lists the values for the dimensions shown
in the illustration.
Rev 1.3
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Si4 464/63/ 61/ 60
Table 18. PCB Land Pattern Dimensions
Min
3.90
3.90
Max
4.00
4.00
0.50 REF
0.20
2.55
0.65
2.55
0.30
2.65
0.75
2.65
D
C1
C2
E
X1
X2
Y1
Y2
Millimeters
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Symbol
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Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 μm minimum, all
the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for the
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for small body components.
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Rev 1.3
S i4 4 6 4 /6 3 /6 1/60
13. Top Marking
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13.1. Si4464/63/61/60 Top Marking
Mark Method
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13.2. Top Marking Explanation
YAG Laser
Part Number
Line 2 Marking
TTTTT = Internal Code
Internal tracking code.2
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Line 1 Marking
44641B = Si4464 Rev 1B1
44631B = Si4463 Rev 1B1
44611B = Si4461 Rev 1B1
44601B = Si4460 Rev 1B1
Line 3 Marking
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
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Notes:
1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware
revision.
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2. The first letter of this line is part of the ROM revision.
Rev 1.3
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Si4 464/63/ 61/ 60
DOCUMENT CHANGE LIST
Revision 0.4 to Revision 1.0
Updated Figure 11 on page 36.
Updated Table 2, Table 3, and Table 4 Max
frequency from 639 to 479 for Synthesizer
Frequency Range (Si4464).
Updated Table 4 to remove delta 639 line from
Modulation Deviation Range (Si4464) and
Modulation Resolution Range (Si4464).
Updated Table 14 to remove Outdiv 6 line.
Updated Table 3 on page 6.
Updated Table 6 on page 12.
Updated Figure 13 on page 37.
Replaced Table 12 on page 28.
Updated "11. Package Outline: Si4464/63/61/60" on
page 49.
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Updated all instances of frequency range for
Si4463/61/60 and Si4464, primarily in the electrical
specifications Tables.
Removed emissions and harmonics specifications
from the electrical specifications.
Updated Tables 13 and 14 to reflect frequency
coverage.
Updated sections 5.2.3 and 5.2.4.
Updated “13.1. Si4464/63/61/60 Top Marking”.
Updated “9. Pin Descriptions: Si4464/63/61/60” for
pins 16 and 17.
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Updated RX Mode Current in Table 1 on page 4.
Updated Synthesizer Frequency Range in Table 2
on page 5.
Updated RX Frequency Range and RX Sensitivity in
Table 3 on page 6.
Updated TX Frequency Range in Table 4 on page 9.
Updated Temperature Sensor Sensitivity in Table 5
on page 11.
Updated Drive Strength in Table 6 on page 12.
Updated Figure 1 and Figure 2 on page 16.
Updated "3.2. Fast Response Registers" on page
19.
Updated Table 9 on page 20.
Updated Figure 9 on page 29.
Updated "5.2.4. Received Signal Strength Indicator"
on page 31.
Updated "5.4. Transmitter (TX)" on page 34.
Updated "8.3. Temperature, Battery Voltage, and
Auxiliary ADC" on page 44.
Updated "9. Pin Descriptions: Si4464/63/61/60" on
page 46.
Updated "11. Package Outline: Si4464/63/61/60" on
page 49.
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Revision 1.0 to Revision 1.1
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CONTACT INFORMATION
Silicon Laboratories Inc.
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400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
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Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering
team.
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
Rev 1.3
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