SI4467-A2A-IM

Si4468/7 H I G H - P ERFORMANCE , L O W -C U R R E N T T RANSCEIVER Features XIN XOUT 20 19 18 17 16 RXp 2 Applications        1 15 nSEL RXn 3 Smart metering (802.15.4g and WMBus) 802.15.4 mesh networking Home security and alarm Telemetry Garage and gate openers Star and point-to-point networks Home automation       Ultra narrowband, long range applications Industrial control Sensor networks Health monitors Electronic shelf labels Low power wireless sensor nodes Description 14 SDI GND PAD TX 4 13 SDO NC 5 12 SCLK 6 7 8 9 10 GPIO1  SDN GND  Pin Assignments GPIO0  GPIO2  VDD   GPIO3  Fast wake and hop times Power supply = 1.8 to 3.8 V Excellent selectivity performance 69 dB adjacent channel 79 dB blocking at 1 MHz Antenna diversity and T/R switch control Highly configurable packet handler TX and RX 64 byte FIFOs 129 bytes dedicated Tx or Rx FIFO Auto frequency control (AFC) Automatic gain control (AGC) Low BOM Low battery detector Temperature sensor 20-Pin QFN package Sub-GHz 802.15.4 mesh network ready IEEE 802.15.4g, and WMBus compliant Suitable for FCC Part 90 Mask D, FCC part 15.247, 15,231, 15,249, ARIB T-108, T-96, T-67, RCR STD-30, China regulatory ETSI Category I Operation EN 300 220 TXRamp  Frequency range = 142–1050 MHz  Receive sensitivity = –133 dBm @  100 bps plus fast-scanning AFC for  standard TCXO applications Modulation (G)FSK, 4(G)FSK, (G)MSK  OOK  Max output power  +20 dBm (Si4468) +13 dBm (Si4467)  PA support for +27 or +30 dBm  Low active power consumption  10/13 mA RX  18 mA TX at +10 dBm (Si4467)  Ultra low current powerdown modes 30 nA shutdown, 40 nA standby  Preamble sense mode  6 mA average RX current at  1.2 kbps 10 µA average RX current at 50 kbps and 1 sec sleep interval Fast preamble detection  1 byte preamble detection  Data rate = 100 bps to 1 Mbps VDD   11 nIRQ Patents pending Silicon Laboratories' Si446x devices are high-performance, low-current transceivers covering the sub-GHz frequency bands from 142 to 1050 MHz. The radios are part of the EZRadioPRO® family, which includes a complete line of transmitters, receivers, and transceivers covering a wide range of applications. A high level of integration including support for IEEE 802.15.4 features enables standards based sub GHz networking solutions. All parts offer outstanding sensitivity of –133 dBm while achieving extremely low active and standby current consumption. The Si4468/7 offers frequency coverage in all major bands. The Si446x includes optimal phase noise, blocking, and selectivity performance for narrow band and licensed band applications, such as FCC Part90 and 169 MHz wireless MBus. The 69 dB adjacent channel selectivity with 12.5 kHz channel spacing ensures robust receive operation in harsh RF conditions, which is particularly important for narrow band operation. The Si4468 offers exceptional output power of up to +20 dBm with outstanding TX efficiency. The high output power and sensitivity results in an industry-leading link budget of 155 dB allowing extended ranges and highly robust communication links. The Si4467 active mode TX current consumption of 18 mA at +10 dBm and RX current of 10 mA coupled with extremely low standby current and fast wake times ensure extended battery life in the most demanding applications. The Si4468 can achieve up to +27 dBm output power with built-in ramping control of a low-cost external FET. The devices can meet worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g and WMBus smart metering standards. The devices are highly flexible and can be configured via the Wireless Development Suite (WDS) available at www.silabs.com. Rev 1.0 10/14 Copyright © 2014 by Silicon Laboratories Si4468/7 Si4468/7 Functional Block Diagram GPIO3 GPIO2 XIN XOUT Loop Filter PFD / CP VCO FBDIV TX DIV SDN RXN TX LO Gen Bootup OSC IF PKDET RF PKDET LNA PGA PA ADC MODEM FIFO Packet Handler nSEL SDI SDO SCLK nIRQ LDOs PowerRamp Cntl POR LBD 32K LP OSC PA LDO TXRAMP 2 30 MHz XO SPI Interface Controller RXP Frac-N Div VDD Digital Logic GPIO0 GPIO1 Product Freq. Range Max Output Power Ultra Narrow Band Support IEEE 802.15.4 / 4g Ready Si4468 Major bands 142–1050 MHz +20 dBm   Si4467 Major bands 142–1050 MHz +13 dBm   Rev 1.0 Si4468/7 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2. Fast Response Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.3. Operating Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.4. Application Programming Interface (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.6. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. Modulation and Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1. Modulation Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.2. Hardware Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.1. RX Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.2. RX Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.3. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.4. Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 6.1. RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 6.2. Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8. Auxiliary Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.1. Wake-up Timer and 32 kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.2. Low Duty Cycle Mode (Auto RX Wake-Up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 8.3. Temperature, Battery Voltage, and Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 8.4. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 8.5. Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 8.6. Preamble Sense Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 9. Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.1. Wireless MBus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.2. ETSI EN300 220 Category 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.3. IEEE 802.15.4 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 10. Packet Trace Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11. Pin Descriptions: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 12. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 13. Package Outline: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 14. PCB Land Pattern: Si4468/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 15. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 15.1. Si4468/7 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 15.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Rev 1.0 3 Si4468/7 1. Electrical Specifications Table 1. DC Characteristics1 Parameter Supply Voltage Range Symbol Min Typ Max Unit 1.8 3.3 3.8 V RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF — 30 1300 nA IStandby Register values maintained and RC oscillator/WUT OFF — 40 2900 nA ISleepRC RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF — 740 3800 nA ISleepXO Sleep current using an external 32 kHz crystal — 1.7 — µA ISensor Low battery detector ON, register values maintained, and all other blocks OFF — 1 — µA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF — 1.8 — mA Ipsm Duty cycling during preamble search, 1.2 kbps, 4 byte preamble (no sensitivity degradation) — 6 — mA Ipsm Fixed 1 s wakeup interval, 50 kbps, 5 byte preamble — 10 — µA ITune_RX RX Tune, High Performance Mode — 7.6 — mA ITune_TX TX Tune, High Performance Mode — 7.8 — mA IRXH High Performance Mode Measured at 915 MHz and 40 kbps data rate. — 13.7 22 mA IRXL Low Power Mode Measured at 315 MHz and 40 kbps data — 10.9 — mA ITX_+20 +20 dBm output power, Class-E match, 915 MHz, 3.3 V — 88 108 mA +20 dBm output power, square-wave match, 169 MHz, 3.3 V — 68.5 80 mA +13 dBm output power, Class-E match, 915 MHz, 3.3 V — 44.5 60 mA ITX_+10 +10 dBm output power, Class-E match, 915/868 MHz, 3.3 V2 — 19.7 — mA ITX_+10 +10 dBm output power, Class-E match, 169 MHz, 3.3 V2 — 18 — mA ITX_+13 +13 dBm output power, Class-E match, 915/868 MHz, 3.3 V — 24 — mA VDD Power Saving Modes IShutdown -LBD Preamble Sense Mode Current TUNE Mode Current RX Mode Current TX Mode Current (Si4468) TX Mode Current (Si4467) Test Condition Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. Measured on direct tie RF evaluation board. 4 Rev 1.0 Si4468/7 Table 2. Synthesizer AC Electrical Characteristics Parameter Synthesizer Frequency Range Synthesizer Frequency Resolution Symbol Test Condition FSYN Min Typ Max Unit 850 — 1050 MHz 350 — 525 MHz 284 — 350 MHz 142 — 175 MHz FRES-960 850–1050 MHz — 28.6 — Hz FRES-525 420–525 MHz — 14.3 — Hz FRES-420 350–420 MHz — 11.4 — Hz FRES-350 283–350 MHz — 9.5 — Hz FRES-175 142–175 MHz — 4.7 — Hz Synthesizer Settling Time tLOCK Measured from exiting Ready mode with XOSC running to any frequency. Including VCO Calibration. — 50 — µs Phase Noise L(fM) F = 10 kHz, 169 MHz, High Perf Mode — –117 –108 dBc/Hz F = 100 kHz, 169 MHz, High Perf Mode — –120 –115 dBc/Hz F = 1 MHz, 169 MHz, High Perf Mode — –138 –135 dBc/Hz F = 10 MHz, 169 MHz, High Perf Mode — –148 –143 dBc/Hz F = 10 kHz, 915 MHz, High Perf Mode — –102 –94 dBc/Hz F = 100 kHz, 915 MHz, High Perf Mode — –105 –97 dBc/Hz F = 1 MHz, 915 MHz, High Perf Mode — –125 –122 dBc/Hz F = 10 MHz, 915 MHz, High Perf Mode — –138 –135 dBc/Hz Note: All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. Rev 1.0 5 Si4468/7 Table 3. Receiver AC Electrical Characteristics1,2 Parameter RX Frequency Range RX Sensitivity 169 MHz3 Symbol Test Condition FRX Min Typ Max Unit 850 — 1050 MHz 350 — 525 MHz 284 — 350 MHz 142 — 175 MHz PRX_0.1 (BER < 0.1%) (100 bps, GFSK, BT = 0.5, f = 100 Hz) — –133 — dBm PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz) — –110 –108 dBm PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz) — –106 –104 dBm PRX_500 (BER < 0.1%) (500 kbps, GFSK, BT = 0.5, f = 250 kHz) — –98 –96 dBm PRX_9.6 (PER 1%) (9.6 kbps, 4GFSK, BT = 0.5, f = ±2.4 kHz) — –110 — dBm PRX_1M (PER 1%) (1 Mbps, 4GFSK, BT = 0.5, inner deviation = 83.3 kHz) — –89 — dBm PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW, OOK, PN15 data) — –110 –107 dBm (BER < 0.1%, 40 kbps, 350 kHz BW, OOK, PN15 data) — –103 –100 dBm (BER < 0.1%, 120 kbps, 350 kHz BW, OOK, PN15 data) — –97 –93 dBm Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. 3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better if reading data from packet handler FIFO especially at higher data rates. 4. Conducted emissions measured on RF evaluation boards. 6 Rev 1.0 Si4468/7 Table 3. Receiver AC Electrical Characteristics1,2 (Continued) Parameter RX Sensitivity 915/868 MHz3 RX Channel Bandwidth RSSI Resolution Symbol Test Condition Min Typ Max Unit PRX_0.1 (BER < 0.1%) (100 bps, GFSK, BT = 0.5, f = 100 Hz) — –132 — dBm PRX_40 (BER < 0.1%) (40 kbps, GFSK, BT = 0.5, f = 20 kHz) — –109 –107 dBm PRX_100 (BER < 0.1%) (100 kbps, GFSK, BT = 0.5, f = 50 kHz) — –104 –102 dBm PRX_500 (BER < 0.1%) (500 kbps, GFSK, BT = 0.5, f = 250 kHz) — –97 –92 dBm PRX_9.6 (PER 1%) (9.6 kbps, 4GFSK, BT = 0.5, f =  kHz) — –109 — dBm PRX_1M (PER 1%) (1 Mbps, 4GFSK, BT = 0.5, inner deviation = 83.3 kHz) — –88 — dBm PRX_OOK (BER < 0.1%, 4.8 kbps, 350 kHz BW, OOK, PN15 data) — –108 –104 dBm (BER < 0.1%, 40 kbps, 350 kHz BW, OOK, PN15 data) — –101 –97 dBm (BER < 0.1%, 120 kbps, 350 kHz BW, OOK, PN15 data) — –96 –91 dBm 0.2 — 850 kHz — ±0.5 — dB BW RESRSSI Valid from –110 dBm to –90 dBm 1-Ch Offset Selectivity, 169 MHz3 C/I1-CH –69 –59 dB 1-Ch Offset Selectivity, 450 MHz3 C/I1-CH –60 –50 dB 1-Ch Offset Selectivity, 868 / 915 MHz3 C/I1-CH Desired Ref Signal 3 dB above sensitivity, BER < 0.1%. Interferer is CW, and desired is modulated with 2.4 kbps F = 1.2 kHz GFSK with BT = 0.5, RX channel BW = 4.8 kHz, channel spacing = 12.5 kHz –55 –45 dB Desired Ref Signal 3 dB above sensitivity, BER = 0.1%. Interferer is CW, and desired is modulated with 2.4 kbps, F = 1.2 kHz GFSK with BT = 0.5, RX channel BW = 4.8 kHz –79 –68 dB –86 –75 dB Blocking 1 MHz Offset 1MBLOCK Blocking 8 MHz Offset 8MBLOCK Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. 3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better if reading data from packet handler FIFO especially at higher data rates. 4. Conducted emissions measured on RF evaluation boards. Rev 1.0 7 Si4468/7 Table 3. Receiver AC Electrical Characteristics1,2 (Continued) Parameter Image Rejection (IF = 468.75 kHz) Symbol Test Condition Min Typ Max Unit ImREJ No image rejection calibration. Rejection at the image frequency. RF = 460 MHz 30 40 — dB With image rejection calibration in Si446x. Rejection at the image frequency. RF = 460 MHz 40 55 — dB No image rejection calibration. Rejection at the image frequency. RF = 915 MHz 30 45 — dB With image rejection calibration in Si446x. Rejection at the image frequency. RF = 915 MHz 40 52 — dB No image rejection calibration. Rejection at the image frequency. RF = 169 MHz 35 45 — dB With image rejection calibration in Si446x. Rejection at the image frequency. RF = 169 MHz 45 60 — dB Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. For PER tests, 48 preamble symbols, 4 byte sync word, 10 byte payload and CRC-32 was used. 3. Measured over 50000 bits using PN9 data sequence and data and clock on GPIOs. Sensitivity is expected to be better if reading data from packet handler FIFO especially at higher data rates. 4. Conducted emissions measured on RF evaluation boards. 8 Rev 1.0 Si4468/7 Table 4. Transmitter AC Electrical Characteristics Parameter TX Frequency Range Symbol Test Condition FTX Min Typ Max Unit 850 — 1050 MHz 350 — 525 MHz 284 — 350 MHz 142 — 175 MHz (G)FSK Data Rate DRFSK 0.1 — 500 kbps 4(G)FSK Data Rate DR4FSK 0.2 — 1000 kbps OOK Data Rate DROOK 0.1 — 120 kbps Modulation Deviation Range f960 850–1050 MHz — 1.5 — MHz f525 420–525 MHz — 750 — kHz f420 350–420 MHz — 600 — kHz f350 283–350 MHz — 500 — kHz f175 142–175 MHz — 250 — kHz FRES-960 850–1050 MHz — 28.6 — Hz FRES-525 420–525 MHz — 14.3 — Hz FRES-420 350–420 MHz — 11.4 — Hz FRES-350 283–350 MHz — 9.5 — Hz FRES-175 142–175 MHz — 4.7 — Hz Output Power Range (Si4468) PTX68 Typical range at 3.3 V –20 — +20 dBm Output Power Range (Si4467) PTX67 Typical range at 3.3 V with Class E match optimized for best PA efficiency –20 — +12.5 dBm Output Power Variation (Si4468) At 20 dBm PA power setting, 915 MHz, Class E match, 3.3 V, 25 °C 19 20 21 dBm Output Power Variation (Si4467) At 10 dBm PA power setting, 915 MHz, Class E match, 3.3 V, 25 °C 9 10 11 dBm Modulation Deviation Resolution Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula: Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz). 3. Default API setting for modulation deviation resolution is double the typical value specified. 4. Output power is dependent on matching components and board layout. Rev 1.0 9 Si4468/7 Table 4. Transmitter AC Electrical Characteristics (Continued) Parameter Test Condition Min Typ Max Unit Output Power Variation (Si4468) At 20 dBm PA power setting, 169 MHz, Square Wave match, 3.3 V, 25 °C 18.5 20 21 dBm Output Power Variation (Si4467) At 10 dBm PA power setting, 169 MHz, Class E match, 3.3 V, 25 °C 9.5 10 10.5 dBm PRF_OUT Using switched current match within 6 dB of max power using CLE match within 6 dB of max power — 0.25 0.4 dB TX RF Output Level Variation vs. Temperature PRF_TEMP –40 to +85 C — 2.3 3 dB TX RF Output Level Variation vs. Frequency PRF_FREQ Measured across 902–928 MHz — 0.6 1.7 dB BT Gaussian Filtering Bandwith Time Product — 0.5 — TX RF Output Steps Transmit Modulation Filtering Symbol Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. 2. The maximum data rate is dependent on the XTAL frequency and is calculated as per the formula: Maximum Symbol Rate = Fxtal/60, where Fxtal is the XTAL frequency (typically 30 MHz). 3. Default API setting for modulation deviation resolution is double the typical value specified. 4. Output power is dependent on matching components and board layout. 10 Rev 1.0 Si4468/7 Table 5. Auxiliary Block Specifications1 Parameter Symbol Test Condition Min Typ Max Unit Temperature Sensor Sensitivity TSS — 4.5 — ADC Codes/ °C Low Battery Detector Resolution LBDRES — 50 — mV Microcontroller Clock Output Frequency Range2 Temperature Sensor Conversion XTAL Range3 30 MHz XTAL Start-Up Time 30 MHz XTAL Cap Resolution 32 kHz XTAL Start-Up Time 32 kHz Accuracy using Internal RC Oscillator POR Reset Time FMC Configurable to Fxtal or Fxtal divided by 2, 3, 7.5, 10, 15, or 30 where Fxtal is the reference XTAL frequency. In addition, 32.768 kHz is also supported. 32.768K — Fxtal Hz TEMPCT Programmable setting — 3 — ms 25 — 32 MHz — 300 — µs 30MRES — 70 — fF t32k — 2 — sec 32KRCRES — 2500 — ppm tPOR — — 6 ms XTALRange t30M Start-up time will vary with XTAL type and board layout. Notes: 1. All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from –45 to +85 °C unless otherwise stated. All typical values apply at Vdd=3.3V and 25C unless otherwise stated. 2. Microcontroller clock frequency tested in production at 1 MHz, 30 MHz, 32 MHz, and 32.768 kHz. Other frequencies tested by bench characterization. 3. XTAL Range tested in production using an external clock source (similar to using a TCXO). Rev 1.0 11 Si4468/7 Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ, SDN)1 Parameter Rise Time 2,3 Fall Time3,4 Symbol Test Condition Min Typ Max Unit TRISE 0.1 x VDD to 0.9 x VDD, CL = 10 pF, DRV = LL — 2.3 — ns TFALL 0.9 x VDD to 0.1 x VDD, CL = 10 pF, DRV = LL — 2 — ns Input Capacitance CIN — 2 — pF Logic High Level Input Voltage VIH VDD x 0.7 — — V Logic Low Level Input Voltage VIL — — VDD x 0.3 V Input Current IIN 0 3.3 V. When Vdd < 3.3 V, the Vhi will be closely following the Vdd, and ramping time will be smaller also. Vlo = 0 V when NO current needed to be sunk into TXRAMP pin. If 10uA need to be sunk into the chip, Vlo will be 10 µA x 10k = 100 mV. 34 Number Command Summary 0x2200 PA_MODE 0x2201 PA_PWR_LVL 0x2202 PA_BIAS_CLKDUTY Adjust TX power in coarse steps and optimizes for different match configurations. 0x2203 PA_TC Changes the ramp up/down time of the PA. Sets PA type. Adjust TX power in fine steps. Rev 1.0 Si4468/7 5.4.1. Si4468: +20 dBm PA The +20 dBm configuration utilizes a class-E matching configuration for all frequency bands except 169 MHz where it uses a Square Wave match..Typical performance for the 915 MHz band for output power steps, voltage, and temperature are shown in Figures 10–12. The output power is changed in 128 steps through PA_PWR_LVL API. For detailed matching values, BOM, and performance at other frequencies, refer to “AN648: PA Matching”. TXPowervs.PA_PWR_LVL 25 20 15 10 5 Ͳ5 Ͳ10 Ͳ15 Ͳ20 Ͳ25 Ͳ30 Ͳ35 Ͳ40 0 20 40 60 80 100 120 PA_PWR_LVL Figure 10. +20 dBm TX Power vs. PA_PWR_LVL TX Power vs. VDD 22 TX Power (dBm) TXPower(dBm) 0 20 18 16 14 12 10 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Supply Voltage (VDD) Figure 11. +20 dBm TX Power vs. VDD Rev 1.0 35 Si4468/7 TX Power vs Temp TX Power (dBm) 20.5 20 19.5 19 18.5 18 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (C) Figure 12. +20 dBm TX Power vs. Temp 5.5. Crystal Oscillator The Si446x includes an integrated crystal oscillator with a fast start-up time of less than 250 µs. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the crystal. The default crystal is 30 MHz, but the circuit is designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30 MHz is used, the POWER_UP API boot command must be modified. The WDS calculator crystal frequency field must also be changed to reflect the frequency being used. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the GLOBAL_XO_TUNE API property. The total internal capacitance is 11 pF and is adjustable in 127 steps (70 fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances. The frequency offset characteristics of the capacitor bank are demonstrated in Figure 13. Figure 13. Capacitor Bank Frequency Offset Characteristics 36 Rev 1.0 Si4468/7 Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. A TCXO or external signal source can easily be used in place of a conventional XTAL and should be connected to the XIN pin. The incoming clock signal is recommended to have a peak-to-peak swing in the range of 600 mV to 1.4 V and ac-coupled to the XIN pin. If the peak-to-peak swing of the TCXO exceeds 1.4 V peak-to-peak, then dc coupling to the XIN pin should be used. The maximum allowed swing on XIN is 1.8 V peak-to-peak. The XO capacitor bank should be set to 0 whenever an external drive is used on the XIN pin. In addition, the POWER_UP command should be invoked with the TCXO option whenever external drive is used. Rev 1.0 37 Si4468/7 6. Data Handling and Packet Handler 6.1. RX and TX FIFOs Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 14. For dedicated TX or RX, the FIFO size is up to 129 bytes. Writing to command Register 66h loads data into the TX FIFO, and reading from command Register 77h reads data from the RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty, which is set by the “TX_FIFO_EMPTY” property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty threshold. If more data is not loaded into the FIFO, the chip automatically exits the TX state after the PACKET_SENT interrupt occurs. The RX FIFO has one programmable threshold, which is programmed by setting the “RX_FIFO_FULL” property. When the incoming RX data crosses the Almost Full Threshold, an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX Almost Full Threshold indication implies that the host can read at least the threshold number of bytes from the RX FIFO at that time. Both the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command. RX FIFO TX FIFO RX FIFO Almost Full Threshold TX FIFO Almost Empty Threshold Figure 14. TX and RX FIFOs 6.2. Packet Handler Config 0, 2, o r 4 Bytes Con fig 0, 2, o r 4 Bytes Rev 1.0 0, 2, o r 4 B ytes C RC Field 5 (op t) Field 5 (opt) Data C RC Field 4 (op t) Con fig Figure 15. Packet Handler Structure 38 Field 4 (opt) Data C RC Field 3 (op t) Field 3 (opt) Data Con fig C RC Field 2 (op t) 1-4 Bytes F ield 2 (o pt) Pkt Len gth or Data Field 1 Header or Data 1-255 Bytes C RC Field 1 (op t) Preamble Sync Word When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual fields for network communication, such as preamble, synchronization word, headers, packet length, and CRC, can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload in TX mode and automatically checking them in RX mode greatly reduces the amount of communication between the microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The general packet structure is shown in Figure 15. Any or all of the fields can be enabled and checked by the internal packet handler. Con fig 0, 2, or 4 Bytes 0, 2, or 4 Bytes Si4468/7 The fields are highly programmable and can be used to check any kind of pattern in a packet structure. The general functions of the packet handler include the following: Detection/validation of Preamble quality in RX mode (PREAMBLE_VALID signal) of Sync word in RX mode (SYNC_OK signal) Detection of valid packets in RX mode (PKT_VALID signal) Detection of CRC errors in RX mode (CRC_ERR signal) Data de-whitening and/or Manchester decoding (if enabled) in RX mode Match/Header checking in RX mode Storage of Data Field bytes into FIFO memory in RX mode Construction of Preamble field in TX mode Construction of Sync field in TX mode Construction of Data Field from FIFO memory in TX mode Construction of CRC field (if enabled) in TX mode Data whitening and/or Manchester encoding (if enabled) in TX mode For details on how to configure the packet handler, see “AN626: Packet Handler Operation for Si446x RFICs”. Detection Rev 1.0 39 Si4468/7 7. RX Modem Configuration The Si446x can easily be configured for different data rate, deviation, frequency, etc. by using the Radio Configuration Application (RCA) GUI which is part of the Wireless Development Suite (WDS) program. 8. Auxiliary Blocks 8.1. Wake-up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer that can be used to periodically wake the chip from sleep mode. The wake-up timer runs from either the internal 32 kHz RC Oscillator, or from an external 32 kHz XTAL. The wake-up timer can be configured to run when in sleep mode. If WUT_EN = 1 in the GLOBAL_WUT_CONFIG property, prior to entering sleep mode, the wake-up timer will count for a time specified defined by the GLOBAL_WUT_R and GLOBAL_WUT_M properties. At the expiration of this period, an interrupt will be generated on the nIRQ pin if this interrupt is enabled in the INT_CTL_CHIP_ENABLE property. The microcontroller will then need to verify the interrupt by reading the chip interrupt status either via GET_INT_STATUS or a fast response register. The formula for calculating the Wake-Up Period is as follows: WUT_R 42 WUT = WUT_M  -----------------------------  ms  32.768 The RC oscillator frequency will change with temperature; so, a periodic recalibration is required. The RC oscillator is automatically calibrated during the POWER_UP command and exits from the Shutdown state. To enable the recalibration feature, CAL_EN must be set in the GLOBAL_WUT_CONFIG property, and the desired calibration period should be selected via WUT_CAL_PERIOD[2:0] in the same API property. During the calibration, the 32 kHz RC oscillator frequency is compared to the 30 MHz XTAL and then adjusted accordingly. The calibration needs to start the 30 MHz XTAL, which increases the average current consumption; so, a longer CAL_PERIOD results in a lower average current consumption. The 32 kHz XTAL accuracy is comprised of both the XTAL parameters and the internal circuit. The XTAL accuracy can be defined as the XTAL initial error + XTAL aging + XTAL temperature drift + detuning from the internal oscillator circuit. The error caused by the internal circuit is typically less than 10 ppm. Refer to API documentation for details on WUT related commands and properties. 8.2. Low Duty Cycle Mode (Auto RX Wake-Up) The low duty cycle (LDC) mode is implemented to automatically wake-up the receiver to check if a valid signal is available or to enable the transmitter to send a packet. It allows low average current polling operation by the Si446x for which the wake-up timer (WUT) is used. RX and TX LDC operation must be set via the GLOBAL_WUT_CONFIG property when setting up the WUT. The LDC wake-up period is determined by the following formula: WUT_R 42 LDC = WUT_LDC  -----------------------------  ms  32.768 where the WUT_LDC parameter can be set by the GLOBAL_WUT_LDC property. The WUT period must be set in conjunction with the LDC mode duration; for the relevant API properties, see the wake-up timer (WUT) section. 40 Rev 1.0 Si4468/7 Figure 16. RX and TX LDC Sequences The basic operation of RX LDC mode is shown in Figure 17. The receiver periodically wakes itself up to work on RX_STATE during LDC mode duration. If a valid preamble is not detected, a receive error is detected, or an entire packet is not received, the receiver returns to the WUT state (i.e., ready or sleep) at the end of LDC mode duration and remains in that mode until the beginning of the next wake-up period. If a valid preamble or sync word is detected, the receiver delays the LDC mode duration to receive the entire packet. If a packet is not received during two LDC mode durations, the receiver returns to the WUT state at the last LDC mode duration until the beginning of the next wake-up period. Figure 17. Low Duty Cycle Mode for RX In TX LDC mode, the transmitter periodically wakes itself up to transmit a packet that is in the data buffer. If a packet has been transmitted, nIRQ goes low if the option is set in the INT_CTL_ENABLE property. After transmitting, the transmitter immediately returns to the WUT state and stays there until the next wake-up time expires. Rev 1.0 41 Si4468/7 8.3. Temperature, Battery Voltage, and Auxiliary ADC The Si446x family contains an integrated auxiliary ADC for measuring internal battery voltage, an internal temperature sensor, or an external component over a GPIO. The ADC utilizes a SAR architecture and achieves 11-bit resolution. The Effective Number of Bits (ENOB) is 9 bits. When measuring external components, the input voltage range is 1 V, and the conversion rate is between 300 Hz to 2.44 kHz. The ADC value is read by first sending the GET_ADC_READING command and enabling the inputs that are desired to be read: GPIO, battery, or temp. The temperature sensor accuracy at 25 °C is typically ±2 °C. Refer to API documentation for details on the command and reply stream. 8.4. Low Battery Detector The low battery detector (LBD) is enabled and utilized as part of the wake-up-timer (WUT). The LBD function is not available unless the WUT is enabled, but the host MCU can manually check the battery voltage anytime with the auxiliary ADC. The LBD function is enabled in the GLOBAL_WUT_CONFIG API property. The battery voltage will be compared against the threshold each time the WUT expires. The threshold for the LBD function is set in GLOBAL_LOW_BATT_THRESH. The threshold steps are in increments of 50 mV, ranging from a minimum of 1.5 V up to 3.05 V. The accuracy of the LBD is ±3%. The LBD notification can be configured as an interrupt on the nIRQ pin or enabled as a direct function on one of the GPIOs. 8.5. Antenna Diversity To mitigate the problem of frequency-selective fading due to multipath propagation, some transceiver systems use a scheme known as antenna diversity. In this scheme, two antennas are used. Each time the transceiver enters RX mode the receive signal strength from each antenna is evaluated. This evaluation process takes place during the preamble portion of the packet. The antenna with the strongest received signal is then used for the remainder of that RX packet. The same antenna will also be used for the next corresponding TX packet. This chip fully supports antenna diversity with an integrated antenna diversity control algorithm. The required signals needed to control an external SPDT RF switch (such as a PIN diode or GaAs switch) are available on the GPIOx pins. The operation of these GPIO signals is programmable to allow for different antenna diversity architectures and configurations. The antdiv[2:0] bits are found in the MODEM_ANT_DIV_CONTROL API property descriptions and enable the antenna diversity mode. The GPIO pins are capable of sourcing up to 5 mA of current; so, it may be used directly to forward-bias a PIN diode if desired. The antenna diversity algorithm will automatically toggle back and forth between the antennas until the packet starts to arrive. The recommended preamble length for optimal antenna selection is 8 bytes. 8.6. Preamble Sense Mode This mode of operation is suitable for extremely low power applications where power consumption is important. The preamble sense mode (PSM) takes advantage of the Digital Signal Arrival detector (DSA), which can detect a preamble within eight bit times with no sensitivity degradation. This fast detection of an incoming signal can be combined with duty cycling of the receiver during the time the device is searching or sniffing for packets over the air. The average receive current is lowered significantly when using this mode. In applications where the timing of the incoming signal is unknown, the amount of power savings is primarily dependent on the data rate and preamble length as the RX inactive time is determined by these factors. In applications where the sleep time is fixed and the timing of the incoming signal is known, the average current also depends on the sleep time. The PSM mode is similar to the low duty cycle mode but has the benefit of faster signal detection and autonomous duty cycling of the receiver to achieve even lower average receive currents. This mode can be used with the low power mode (LP) which has an active RX current of 10 mA or with the high-performance (HP) mode which has an active RX current of 13 mA. 42 Rev 1.0 Si4468/7 Figure 18. Preamble Sense Mode Table 16. Data Rates Data Rate 1.2 kbps 9.6 kbps 50 kbps 100 kbps PM length = 4 bytes 6.48 6.84 8.44 10.43 mA PM length = 8 bytes 3.83 3.96 4.57 5.33 mA Note: Typical values. Active RX current is 13 mA. Rev 1.0 43 Si4468/7 9. Standards Support 9.1. Wireless MBus Support Wireless MBus is a widely accepted standard for smart meter communication in Europe. The radio supports all WMBus modes per the latest draft specification of the EN13757-4 standard. This includes a much wider deviation error tolerance of ±30% and frequency error tolerance of ±4 kHz, short preamble support (16-bit preamble for 2 and 4 level FSK modes), 3-of-6 encoding and decoding and 169 MHz N modes including N2g. In addition, Silicon Labs has a production-ready wireless MBus stack available at no additional cost that supports S, T, C, and N modes and runs on the EFM32 (32-bit ARM) family of energy friendly microcontrollers. This stack and complete documentation including PHY configuration and test results are available for download from the EZRadioPRO page at www.silabs.com. 9.2. ETSI EN300 220 Category 1 The radio is capable of supporting ETSI Category 1 applications (social alarms, healthcare applications, etc.) in the 169 MHz and 868 MHz bands under certain modem conditions. Blocking performance is improved at the 2 MHz and 10 MHz offsets allowing for additional margin from the regulatory limits. The radio complies with ACS limits at the 25 kHz offset in both, 169 MHz and 868 MHz bands. In the 169 MHz band, there is no need for an external SAW filter for 2 MHz and 10 MHz blocking resulting in a lower system cost. In the 868 MHz band, an external SAW filter is still required to meet the Cat 1 blocking limits. An RF Pico board is available for evaluation specifically for ETSI Cat 1 applications. Test conditions for ETSI Cat 1 specifications are different from the typical conditions and are stated below. Data Rate: 3 kbps Deviation: 2 kHz Modulation: 2 GFSK IF mode: Fixed and/or Scaled IF RX bandwidth: 13 kHz BER target: 0.1% Blocker signal: CW ETSI Cat 1 limits 169 MHz band (no SAW) 868 MHz band (no SAW) ±25 kHz ACS 54 dB 62 dB 58 dB ±2 MHz blocking 84 dB 88 dB 76 dB ±10 MHz blocking 84 dB 90 dB 82 dB RX sensitivity –107 dBm –108 dBm –108 dBm Spurious response 35 dB 40 dB 40 dB For further details on configuring the radio for ETSI Cat 1 applications, refer to the application notes available on the Silicon Labs website. 44 Rev 1.0 Si4468/7 9.3. IEEE 802.15.4 Support Si4468/7 supports the mandatory features of MR-FSK PHY specified in IEEE 802.15.4g as well as some key features from IEEE 802.15.4. The high level of integration makes it easy to use and offloads the host microcontroller from these tasks. To support the 802.15.4 MAC, the device has a specific 802.15.4 boot mode. In this mode, the device only processes 802.15.4 / 4g packets and no customization is possible at the packet level. This mode is supported by an 802.15.4 stack running on a Silicon Labs MCU or SoC. In this mode, the device only supports the packet format defined in the 802.15.4 standard. There is no flexibility to support non-802.15.4 packet formats in this boot mode. Custom packets, including those based on the 802.15.4g PHY standard, are fully supported in the EZRadioPRO boot mode. 802.15.4g PHY modes including CRC handling and dual sync word are supported in the PRO boot mode as well. The key features are described below. 9.3.1. CCA Functionality Basic clear channel assessment (CCA) functionality is supported in any boot mode and relies on RSSI being above or below a user defined threshold. In addition, the chip supports CSMA / CA and Energy Detection (ED) as defined in IEEE 802.15.4. 9.3.2. CSMA/CA The carrier sense feature is fully supported in the 802.15.4 boot mode of the device and is specific to the 802.15.4 packet format. Support for CSMA/CA in the EZRadioPRO boot mode requires host microcontroller support to implement the back-off timer. The device can send an IEEE 802.15.4 packet with a CSMA/CA algorithm before the packet and reception of an ACK packet afterwards without host interaction. The host loads the IEEE 802.15.4 packet into the TX FIFO via the WRITE_TX_FIFO command. The CSMA/CA algorithm must pass before sending the packet configured, the transceiver will listen for an ACK after successful transmission of the packet The CSMA/CA algorithm listens on the transmit channel to see if the channel is clear before transmitting the packet. The period in which the transceiver listens is defined in units of symbols. If the RSSI measured is greater than a user-defined threshold, the transceiver deems that the channel is busy and does a backoff for a random amount of time up to five backoff periods. The units of the backoff are defined in symbol times. If the channel is clear during the listening period, then the transceiver will proceed to transmit the IEEE 802.15.4 packet. If the transceiver exhausts all of the backoff periods, the transceiver will post a TX_ERROR interrupt with a TX_ERROR_STATUS of CCA_FAIL. If Below is an example of a transmit operation where the first CSMA check fails and the second one passes. Rev 1.0 45 Si4468/7 Figure 19. Transmit Operation where first CSMA Check Fails and Second Passes The device also supports Listen Before Talk (LBT) as defined by the ETSI EN 300 220-1 specification, which adds a minimum (fixed) 5 ms delay in addition to a random backoff before transmission. 9.3.3. Auto-ACK After the packet is transmitted, the transceiver has the ability to automatically receive an ACK if configured to do so. The transceiver will listen for a properly formatted acknowledgement frame with a set timeout period. If the ACK is received in time, the transceiver will post an interrupt depending on if the frame pending bit is set in the ACK. If the ACK is not received in the timeout window, the transceiver will post a TX_ERROR interrupt. 9.3.4. 802.15.4 Packet Format The device supports the frame format defined in IEEE 802.15.4 and is able to parse the field information autonomously without host interaction. All the host needs to do is boot up in the 802.15.4 boot mode and load the packet into the TX FIFO for transmission. For details on the 802.15.4 packet formats, please refer to the standard’s documentation. 9.3.5. 802.15.4g CRC The device natively supports both 2 byte and 4 byte FCS as defined in IEEE 802.15.4g in both boot modes. 9.3.6. Simultaneous Dual Sync Word The device is capable of simultaneously searching for two sync words with each sync word being user defined and up to 4 bytes each. One application of this is to detect packets that use forward error correction (FEC) as defined in IEEE 802.15.4g. FEC is an optional feature in the standard is indicated in the sync word. The transceiver does not natively support FEC. It can pass on the information on whether FEC is used or not to the host microcontroller for further processing. 9.3.7. Address Filtering The device supports 8 byte (EUI-64) address filtering per IEEE 802.15.4. This is a unique identifier that is used for each node in a network. The device also supports the short address filtering defined in the 802.15.4 standard. 46 Rev 1.0 Si4468/7 10. Packet Trace Port The device integrates a true PHY-level Packet Trace Interface (PTI) for effective network-level debugging. PTI monitors all the PHY Tx and Rx packets without affecting their normal operation. This asynchronous interface provides a trace of all over-the-air packet data as well as packet status via a single user-selectable GPIO. PTI can be disabled in software and cannot be used to inject packets into the modem interface. The default baud rate of the PTI interface is 500 kbaud, which is optimal to support a 250 kbps data rate. PTI is supported on Si4468/7 in the 15.4 boot mode only and is supported by Silicon Labs Development tools. Rev 1.0 47 Si4468/7 GND XIN XOUT 1 GPIO2 SDN GPIO3 11. Pin Descriptions: Si4468/7 20 19 18 17 16 RXp 2 15 nSEL RXn 3 14 SDI GND PAD TX 4 13 SDO Pin Pin Name 6 7 8 9 10 TXRamp VDD GPIO0 GPIO1 12 SCLK VDD NC 5 11 nIRQ I/0 Description 1 SDN I Shutdown Input Pin. 0–VDD V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN = 1, the chip will be completely shut down, and the contents of the registers will be lost. 2 RXp I Differential RF Input Pins of the LNA. 3 RXn I See application schematic for example matching network. 4 TX O 5 NC 6 VDD VDD 7 TXRAMP O 8 VDD VDD 9 GPIO0 I/O General Purpose Digital I/O. I/O May be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. Transmit Output Pin. 10 GPIO1 The PA output is an open-drain connection, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. It is recommended to connect to GND per the reference design schematic. Not connected internally to any circuitry. +1.8 to +3.8 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. Programmable Bias Output with Ramp Capability for External FET PA. See "5.4. Transmitter (TX)" on page 33. +1.8 to +3.8 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. General Microcontroller Interrupt Status Output. 11 48 nIRQ O When the Si446X exhibits any one of the interrupt events, the nIRQ pin will be set low = 0. The Microcontroller can then determine the state of the interrupt by reading the interrupt status. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. Rev 1.0 Si4468/7 Pin Pin Name I/0 Description Serial Clock Input. 12 SCLK I 13 SDO O 0–VDD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si446x on positive edge transitions. 0–VDD V Digital Output. Provides a serial readback function of the internal control registers. Serial Data Input. 14 SDI I 0–VDD V digital input. This pin provides the serial data stream for the 4-line serial data bus. Serial Interface Select Input. 15 nSEL I 0–VDD V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. Crystal Oscillator Output. 16 XOUT O 17 XIN I Connect to an external 25 to 32 MHz crystal, or leave floating when driving with an external source on XIN. Crystal Oscillator Input. Connect to an external 25 to 32 MHz crystal, or connect to an external source. When using an XTAL, leave floating per the reference design schematic. When using a TCXO, connect to TCXO GND, which should be separate from the board’s reference ground plane. 18 GND GND 19 GPIO2 I/O General Purpose Digital I/O. 20 GPIO3 I/O May be configured through the registers to perform various functions, including Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. GND The exposed metal paddle on the bottom of the Si446x supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si446x. PKG PADDLE_GND Rev 1.0 49 Si4468/7 12. Ordering Information Part Number Description Package Type Operating Temperature Si4468-A2A-IM ISM EZRadioPRO Transceiver QFNPb-free –40 to 125 °C Si4467-A2A-IM ISM EZRadioPRO Transceiver QFNPb-free –40 to 125 °C Note: Add an “(R)” at the end of the device part number to denote tape and reel option. 50 Rev 1.0 Si4468/7 13. Package Outline: Si4468/7 Figure 20 illustrates the package details for the Si446x. Table 17 lists the values for the dimensions shown in the illustration.   2X bbb C B A D D2 Pin 1 (Laser) e 20 20x L 1 E E2 2X aaa C A1 20x b ccc C ddd C A B eee C A SEATING PLANE A3 C Figure 20. 20-Pin Quad Flat No-Lead (QFN) Rev 1.0 51 Si4468/7 Table 17. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 A3 b 0.20 REF 0.18 0.25 D D2 0.30 4.00 BSC 2.45 2.60 e 0.50 BSC E 4.00 BSC 2.75 E2 2.45 2.60 2.75 L 0.30 0.40 0.50 aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.08 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 52 Rev 1.0 Si4468/7 14. PCB Land Pattern: Si4468/7 Figure 21 illustrates the PCB land pattern details for the Si446x. Table 18 lists the values for the dimensions shown in the illustration. Figure 21. PCB Land Pattern Rev 1.0 53 Si4468/7 Table 18. PCB Land Pattern Dimensions Symbol Millimeters Min Max C1 3.90 4.00 C2 3.90 4.00 E 0.50 REF X1 0.20 0.30 X2 2.55 2.65 Y1 0.65 0.75 Y2 2.55 2.65 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125 mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad. Card Assembly 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. 54 Rev 1.0 Si4468/7 15. Top Marking 15.1. Si4468/7 Top Marking 15.2. Top Marking Explanation Mark Method YAG Laser Line 1 Marking Part Number 44682A = Si4468 Rev A21 44672A = Si4467 Rev A21 Line 2 Marking TTTTTT = Internal Code Internal tracking code.2 Line 3 Marking YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Notes: 1. The first letter after the part number is part of the ROM revision. The last letter indicates the firmware revision. 2. The first letter of this line is part of the ROM revision. Rev 1.0 55 Si4468/7 DOCUMENT CHANGE LIST Revision 0.1 to Revision 1.0 Updated parameters and notes in “1. Electrical Specifications”.  Updated Table 15.  Updated “11. Pin Descriptions: Si4468/7”.  Minor updates to text descriptions.  56 Rev 1.0 Simplicity Studio One-click access to MCU tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! www.silabs.com/simplicity MCU Portfolio www.silabs.com/mcu SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Trademark Information Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Silicon Laboratories: SI4467-A2A-IMR SI4467-A2A-IM SI4468-A2A-IMR SI4468-A2A-IM