Si 4 7 0 3 - B17
B R O A D C A S T F M R A D I O TU N E R FOR P O R TA B L E A P P L I C A T I O N S
Features
ns
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control
interface
2.7 to 5.5 V supply voltage
Integrated LDO regulator
allows direct connection to
battery
3 x 3 mm 20-pin QFN package
ig
Ordering Information:
See page 35.
D
es
This data sheet applies to
Si4703 Firmware 17 and greater
Worldwide FM band support
(76–108 MHz)
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
Seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis
(50/75 µs)
Pin Assignments
(Top View)
Pb-free/RoHS compliant
ew
RDS/RBDS Processor
Integrated crystal oscillator
RFGND
LNA
PGA
Q
ADC
32.768 kHz
N
ot
RCLK
2.7–5.5 V
0 / 90
R
AGC
VA
VD
REG
Confidential Rev. 1.0 1/07
XTAL
OSC
LOW-IF
DAC
DAC
GPIO
LOUT
ROUT
GPIO
VIO
AFC
TUNE
FILTER
DEMOD
MPX
AUDIO
RDS
RSSI
GND
4
RST
5
VA
3
GPIO3
RFGND
GPIO2
2
19
18
17
16
15 GND
14 LOUT
GND
PAD
13 ROUT
12 GND
6
7
8
9
10
11 VD
Si4703
AMPLIFIER
FMIP
DSP
RST
SDIO
SCLK
SEN
CONTROLLER
I
ADC
CONTROL
INTERFACE
Headphone
Cable
ec
om
m
Functional Block Diagram
FMIP
20
VIO
en
The Si4703 integrates the complete tuner function from antenna input to
stereo audio output for FM broadcast radio reception.
1
RCLK
de
d
Description
NC
GPIO1
fo
Portable navigation
Automotive
Consumer electronics
SDIO
USB FM radio
PDAs
Notebook PCs
SCLK
Cellular handsets
MP3 players
Portable radios
SEN
NC
rN
Si4703-GM
Applications
Copyright © 2007 by Silicon Laboratories
Patents pending
Notes:
1. To ensure proper operation and FM
receiver performance, follow the
guidelines in “AN231: Si4700/01/02/03
Headphone and Antenna Interface.”
Silicon Laboratories will evaluate
schematics and layouts for qualified
customers.
2. Place Si4703 as close as possible to
antenna jack and keep the FMIP trace
as short as possible.
Si4703-B17
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Si4703-B17
2
Confidential Rev. 1.0
Si4703-B17
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7. Pin Descriptions: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10. Package Outline: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11. PCB Land Pattern: Si4703-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Confidential Rev. 1.0
3
Si4703-B17
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VD
2.7
—
5.5
V
Analog Supply Voltage
VA
2.7
—
5.5
V
Interface Supply Voltage
VIO
1.5
—
3.6
V
Digital Power Supply Power-Up
Rise Time
VDRISE
25
—
—
µs
Analog Power Supply Power-Up
Rise Time
VARISE
25
—
—
Interface Power Supply Power-Up
Rise Time
VIORISE
25
—
—
TA
–20
25
ig
µs
D
es
Ambient Temperature
ns
Digital Supply Voltage
85
µs
°C
rN
ew
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VD = VA = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Value
Unit
–0.5 to 5.8
V
–0.5 to 5.8
V
fo
Symbol
VD
Analog Supply Voltage
VA
Interface Supply Voltage
VIO
–0.5 to 3.9
V
Input Current3
IIN
±10
mA
VIN
–0.3 to (VIO + 0.3)
V
TOP
–40 to 95
°C
TSTG
–55 to 150
°C
0.4
VpK
Input Voltage
de
d
Digital Supply Voltage
en
Parameter
3
m
Operating Temperature
om
Storage Temperature
RF Input Level4
N
ot
R
ec
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4703 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling and
assembly of this device should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
4. At RF input pins.
4
Confidential Rev. 1.0
Si4703-B17
Table 3. DC Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Analog Powerdown Current1,5,6
Digital Supply
Current1
Digital Supply Current1,2,3,4
Digital Powerdown Current1,5,6
Interface Supply Current1
Interface Powerdown
Current1,5,6,7
Min
Typ
Max
Unit
IA
ENABLE = 1
—
13.4
15.3
mA
IA
ENABLE = 1
Low SNR level
—
14.2
15.9
mA
IPDA
ENABLE = 0
—
2.4
5
µA
ID
ENABLE = 1
—
5.3
8.5
mA
ID
ENABLE = 1
Low SNR level
—
5.0
8.0
IPDD
ENABLE = 0
—
2.1
5
IIO
ENABLE = 1
—
400
650
µA
IIO
SCLK, RCLK inactive
ENABLE = 0
—
0.5
5
µA
ns
Analog Supply
Current1,2,3,4
Test Condition
mA
ig
Analog Supply Current1
Symbol
D
es
Parameter
µA
VIH
0.7 x VIO
—
VIO + 0.3
V
Voltage8
VIL
–0.3
—
0.3 x VIO
V
High Level Input Current8
IIH
VIN = VIO = 3.6 V
—
10
µA
Current8
IIL
VIN = 0 V,
VIO = 3.6 V
—
10
µA
High Level Output Voltage9
VOH
IOUT = 500 µA
0.8 x VIO
—
—
V
9
VOL
IOUT = –500 µA
—
—
0.2 x VIO
V
–10
d
Low Level Output Voltage
rN
Low Level Input
–10
fo
Low Level Input
ew
High Level Input Voltage8
N
ot
R
ec
om
m
en
de
Notes:
1. Refer to Register 02h, "Power Configuration" on page 21 for ENABLE bit description.
2. The LNA is automatically switched to higher current mode for optimum sensitivity in low SNR conditions.
3. Analog and digital supply currents are simultaneously adjusted based on SNR level.
4. Stereo and RDS functionality are disabled at low SNR levels.
5. Specifications are guaranteed by characterization.
6. Refer to Section 4.9. "Reset, Powerup, and Powerdown" on page 17.
7. All GPIO pins are grounded.
8. For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
9. For output pins SDIO, GPIO1, GPIO2, and GPIO3.
Confidential Rev. 1.0
5
Si4703-B17
Table 4. Reset Timing Characteristics
Test Condition
Min
Typ
Max
Unit
RST, GPIO3 Input to RSTSetup
tSRST
100
—
—
µs
SEN, SDIO Input to RSTSetup
tSRST
Busmode Select
Method 1*
30
—
—
ns
SEN, SDIO, GPIO3 Input to RST
Hold
tHRST
30
—
—
ns
GPIO1, GPIO3 Input to RST
Setup
tSRST
30
—
—
ns
GPIO1, GPIO3 Input to RSTHold
tHRST
30
—
—
Busmode Select
Method 2
ns
Symbol
ns
ig
Parameter
RST
70%
SEN
70%
fo
rN
30%
30%
de
70%
d
30%
en
GPIO3
SDIO
tHRST
ew
tSRST
D
es
*Note: In Busmode Select Method 1, GPIO3 may be left high-Z (minimum pullup 10 M), be left floating, or pulled low to be
backwards compatible with Si4700/01 silicon revision A. If GPIO3 is pulled low then the minimum tSRST for RST,
GPIO3 input to RSTsetup is only 30 nS.
om
m
Figure 1. Reset Timing Parameters for Busmode Select Method 1
70%
GPIO1
70%
GPIO3
70%
N
ot
R
ec
RST
tSRST
tHRST
30%
30%
30%
Figure 2. Reset Timing Parameters for Busmode Select Method 2
6
Confidential Rev. 1.0
Si4703-B17
Table 5. 3-Wire Control Interface Characteristics
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN1
10
—
—
SEN Input to SCLKHold
tHSEN2
10
—
—
tCDV
Read
2
—
SCLKto SDIO Output High Z
tCDZ
Read
2
—
SCLK
70%
SEN
70%
SDIO
70%
ns
25
ns
25
ns
ew
SCLKto SDIO Output Valid
ns
ig
SDIO Input, SEN to SCLKSetup
ns
SCLK Frequency
D
es
Parameter
t HSDIO
tS
tHIGH
tHSEN1
tHSEN2
d
de
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
en
30%
tLOW
fo
tS
30%
A7
rN
30%
Address In
D0
Data In
SCLK
70%
SEN
70%
om
m
Figure 3. 3-Wire Control Interface Write Timing Parameters
ec
30%
tHSDIO
tS
80%
SDIO
20%
A7
t HSEN1
tS
R
N
ot
30%
tCDV
A6-A5,
R/W,
A4-A1
Address In
tCDZ
tHSEN2
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 4. 3-Wire Control Interface Read Timing Parameters
Confidential Rev. 1.0
7
Si4703-B17
Table 6. 2-Wire Control Interface Characteristics1
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO Hold (START)
tHD:STA
0.6
—
—
SDIO Input to SCLK Setup
tSU:DAT
100
—
—
SDIO Input to SCLK Hold2,3
tHD:DAT
0
—
SCLK input to SDIO Setup (STOP)
tSU:STO
0.6
—
STOP to START Time
tBUF
1.3
—
SDIO Output Fall Time
tf:OUT
20 + 01.Cb
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
20 + 01.Cb
SCLK, SDIO Capacitive Loading
Cb
Input Filter Pulse Suppression
tSP
ns
SCLK Frequency
D
es
ig
µs
ns
ns
—
µs
—
µs
—
250
ns
—
300
ns
—
—
50
pF
—
—
50
ns
fo
rN
ew
900
N
ot
R
ec
om
m
en
de
d
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. As a transmitter, the Si4703 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the
0 ns tHD:DAT specification.
3. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated so long as all other timing parameters are met.
8
Confidential Rev. 1.0
Si4703-B17
SCLK
70%
SDIO
70%
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
30%
STOP
START
D
es
Figure 5. 2-Wire Control Interface Read and Write Timing Parameters
ig
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
ns
30%
A6-A0,
R/W
START
D7-D0
ADDRESS + R/W
ACK
D7-D0
fo
SDIO
rN
ew
SCLK
DATA
ACK
DATA
ACK
STOP
N
ot
R
ec
om
m
en
de
d
Figure 6. 2-Wire Control Interface Read and Write Timing Diagram
Confidential Rev. 1.0
9
Si4703-B17
Table 7. FM Receiver Characteristics1,2
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Symbol
Parameter
Input Frequency
Test Condition
fRF
Sensitivity3,4,5,6,7
Min
Typ
Max
Unit
76
—
108
MHz
—
2.2
3.5
µVEMF
f = 2 kHz,
RDS BLER < 5%
—
15
—
µVEMF
RDS Sensitivity in Performance
Mode8,9
f = 2 kHz,
RDS BLER < 5%
RDSPRF = 1
—
12
—
µVEMF
3
4
5
4
5
6
104
108
—
dBµVEMF
m = 0.3
40
55
—
dB
Adjacent Channel Selectivity
±200 kHz
35
50
—
dB
Alternate Channel Selectivity
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
—
32.768
—
kHz
SPACE[1:0] = 00 or 01
–200
—
200
ppm
SPACE[1:0] = 10
–50
—
50
72
80
90
mVRMS
—
—
1
dB
30
—
15 k
Hz
LNA Input Capacitance
AM Suppression
3,4,5,8,10
Spurious Response Rejection8
RCLK Frequency
fo
RCLK Frequency Tolerance
12
Audio Output Voltage3,4,5,10
d
3,4,10,13
de
Audio Output L/R Imbalance
Audio Band Limits
rN
Input IP38,11
3,4,8,10
±1.5 dB
Notes:
k
ig
8,10
D
es
LNA Input Resistance8,10
ew
RDS Sensitivity
ns
(S+N)/N = 26 dB
8
pF
N
ot
R
ec
om
m
en
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN231: Si4700/
01/02/03 Headphone and Antenna Interface.” Silicon Laboratories will evaluate schematics and layouts for qualified
customers.
3. FMOD = 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with matching network.
8. Guaranteed by characterization.
9. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 20.
10. Measured at VEMF = 1 mV, fRF = 76 to 108 MHz.
11. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
20.
12. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
13. f = 75 kHz.
14. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
15. At LOUT and ROUT pins.
16. Min and Max at room temperature (25 C°).
10
Confidential Rev. 1.0
Si4703-B17
Table 7. FM Receiver Characteristics1,2 (Continued)
(VD = VA = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Test Condition
Min
Typ
Max
Unit
25
—
—
dB
—
34
—
dBµVEMF
55
63
—
dB
—
58
—
dB
—
0.1
0.5
%
DE = 0
70
75
80
Audio Stereo Separation3,10,13
BLNDADJ = 10
10 dB stereo separation
Mono/Stereo Switching Level3,13
Audio Mono S/N3,4,5,6,10
Audio Stereo S/N
Audio
5
BLNDADJ = 10
THD3,4,10,13
14
De-emphasis Time Constant
ns
Symbol
Parameter
µs
45
50
54
ENABLE = 1
0.7
0.8
0.9
Audio Common Mode Voltage15
ENABLE = 0
AHIZEN = 1
—
0.5 x VIO
—
V
V
RL
Single-ended
10
—
—
k
Audio Output Load Capacitance8,15
CL
Single-ended
—
—
50
pF
SPACE[1:0] = 0x,
RCLK
tolerance = 200 ppm,
(x = 0 or 1)
—
—
60
ms/
channel
Powerup Time
From powerdown
(Write ENABLE bit to 1)
—
—
110
ms
RSSI Offset16
Input levels of 8 and
60 dBµV at RF input
–3
—
3
dB
rN
fo
d
de
Seek/Tune
Time8,12
ew
Audio Output Load Resistance8,15
D
es
Audio Common Mode Voltage
µs
ig
DE = 1
15
Notes:
N
ot
R
ec
om
m
en
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN231: Si4700/
01/02/03 Headphone and Antenna Interface.” Silicon Laboratories will evaluate schematics and layouts for qualified
customers.
3. FMOD = 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with matching network.
8. Guaranteed by characterization.
9. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 20.
10. Measured at VEMF = 1 mV, fRF = 76 to 108 MHz.
11. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page
20.
12. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 20. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
13. f = 75 kHz.
14. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 20.
15. At LOUT and ROUT pins.
16. Min and Max at room temperature (25 C°).
Confidential Rev. 1.0
11
Si4703-B17
2. Typical Application Schematic
GPIO1
19
GPIO1
18
GPIO2
17
GPIO3
16
VA
VBATTERY
2.7 to 5.5 V
6
C1
SEN
SCLK
SDIO
ew
RST
X1
rN
GPIO3
C2
RCLK
C3
fo
RCLK
VIO
1.5 to 3.6 V
ig
LOUT
ROUT
D
es
GND
PAD
SEN
FMIP
RFGND
15
GND
14
LOUT
13
ROUT
12
GND
11
VD
7
SCLK
8
SDIO
9
RCLK
10
VIO
1
NC
2
FMIP
3
RFGND
4
GND
5
RST
ns
NC
20
GPIO2
GPIO3
d
Optional: for crystal oscillator option
ec
om
m
en
de
Notes:
1. Place C1 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. Important Note: FM Receiver performance is subject to adherence to antenna design guidelines in “AN231: Si4700/01/
02/03 Headphone and Antenna Interface.” Failure to use these guidelines will negatively affect the performance of the
Si4703, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
5. Pin 2 connects to the antenna interface, refer to “AN231: Si4700/01/02/03 Headphone and Antenna Interface.”
6. Place Si4703 as close as possible to antenna jack and keep the FMIP trace as short as possible.
7. Refer to Si4702/03 Internal Crystal Oscillator Errata.
8. Refer to "AN299: External 32.768 kHz Crystal Oscillator."
C1
U1
C2, C3
X1
12
Value/Description
Supplier(s)
N
ot
Component(s)
R
3. Bill of Materials
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
Si4703 FM Radio Tuner
Silicon Laboratories
Crystal load capacitors, 22 pF, ±5%, COG (Optional: for
crystal oscillator option)
Venkel
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
Confidential Rev. 1.0
Si4703-B17
4. Functional Description
PGA
Q
ADC
AGC
0 / 90
FILTER
DEMOD
MPX
AUDIO
LOW-IF
DAC
GPIO
32.768 kHz
ROUT
GPIO
VIO
VA
REG
XTAL
OSC
RSSI
RST
SDIO
SCLK
SEN
ew
VD
RDS
D
es
AFC
TUNE
CONTROL
INTERFACE
RCLK
2.7 - 5.5 V
LOUT
ns
LNA
RFGND
DAC
ig
FMIP
DSP
CONTROLLER
I
ADC
AMPLIFIER
Si4703
Headphone
Cable
Figure 7. Si4703 FM Receiver Block Diagram
rN
fo
The Si4703 is based on the superior, proven
performance of Silicon Laboratories' Aero architecture
offering unmatched interference rejection and leading
sensitivity. The device uses the same programming
interface as the Si4701 and supports multiple
bus-modes. Power management is also simplified with
an integrated regulator allowing direct connection to a
2.7 to 5.5 V battery.
om
m
en
de
The Si4703 extends Silicon Laboratories Si4700 FM
tuner family, and further increases the ease and
attractiveness of adding FM radio reception to mobile
devices through small size and board area, minimum
component count, flexible programmability, and
superior, proven performance. Si4703 software is
backwards compatible to existing Si4701 FM Tuner
designs and leverages Silicon Laboratories' highly
successful and patented Si4701 FM tuner. The Si4703
benefits from proven digital integration and 100%
CMOS process technology, resulting in a completely
integrated solution. It is the industry's smallest footprint
FM tuner IC requiring only 10 mm2 board space and
one external bypass capacitor.
RDS status, data, and block errors. Si4703 software is
backwards compatible to the proven Si4701, adopted
by leading cell-phone and MP3 manufacturers
world-wide.
d
4.1. Overview
R
ec
The device offers significant programmability, and
caters to the subjective nature of FM listeners and
variable FM broadcast environments world-wide
through a simplified programming interface and mature
functionality.
N
ot
The Si4703 incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS enables data such as station identification and
song name to be displayed to the user. The Si4703
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
The Si4703 device’s high level of integration and
complete FM system production testing increases
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
4.2. FM Receiver
The Si4703’s patented digital low-IF architecture
reduces external components and eliminates the need
for factory adjustments. The receive (RX) section
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers. For testing purposes, the AGC can be
disabled with the AGCD bit. Refer to Section 6.
"Register Descriptions" on page 20 for additional
programming and configuration information.
The Si4703 architecture and antenna design increases
Confidential Rev. 1.0
13
Si4703-B17
ns
ig
D
es
ew
The Si4703 offers an RDS high-performance mode for
RDS-only applications such as TMC (traffic message
channel) coupled with a GPS device. The RDS
performance bit RDSPRF 06h[9] is disabled by default
for backwards compatibility with previous RDS firmware
releases. When RDSPRF is enabled the device
increases power to the LNA, sets RDS to
unconditionally remain enabled, and disables FM
impulse detection, thereby avoiding RDS shutdown and
allowing the device to continue to track and decode
RDS in very poor SNR environments.
om
4.4. RDS/RBDS Processor and
Functionality
m
en
de
The pins GPIO1–3 can serve multiple functions. GPIO1
and GPIO3 can be used to select between 2-wire and
3-wire modes for the control interface as the device is
brought out of reset. See Section “4.9. Reset, Powerup,
and Powerdown”. After powerup of the device, the
GPIO1–3 pins can be used as general purpose inputs/
outputs, and the GPIO2–3 pins can be used as interrupt
request pins for the seek/tune or RDS ready functions
and as a stereo/mono indicator respectively. See
register 04h, bits [5:0] in Section “6. Register
Descriptions” for information on the control of these
pins. It is recommended that the GPIO2–3 pins not be
used as interrupt request outputs until the powerup time
has completed (see Section “4.9. Reset, Powerup, and
Powerdown”). The GPIO3 pin has an internal, 1 M,
±15% pull-down resistor that is only active while RST is
low. General purpose input/output functionality is
available regardless of the state of the VA and VD
supplies, or the ENABLE and DISABLE bits.
rN
4.3. General Purpose I/O Pins
Setting the RDS mode bit high places the device in RDS
verbose mode. The device sets RDSS high when
synchronized and low when synchronization is lost. If
the device is synchronized, RDS ready (RDSR) will be
set for a minimum of 40 ms when a RDS group has
been received. Setting the RDS interrupt enable
(RDSIEN) bit and GPIO2[1:0] = 10 will configure GPIO2
to pulse low for a minimum of 5 ms if the device is
synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide
block-error levels for the RDS group. The number of bit
errors in each block within the group is encoded as
follows: 00 = no errors, 01 = one to two errors, 10 =
three to five errors, 11 = six or more errors. Six or more
errors in a block indicate the block is uncorrectable and
should not be used.
fo
An image-reject mixer downconverts the RF signal to
low-IF. The quadrature mixer output is amplified,
filtered,
and
digitized
with
high
resolution
analog-to-digital converters (ADCs). This advanced
architecture achieves superior performance by using
digital signal processing (DSP) to perform channel
selection, FM demodulation, and stereo audio
processing
compared
to
traditional
analog
architectures.
when a valid RDS group has been received. If an invalid
group is received, RDSR will not be set and GPIO2 will
not pulse low. In standard mode RDS synchronization
(RDSS) and block error rate A, B, C and D (BLERA,
BLERB, BLERC, and BLERD) are unused and will read
0. This mode is backward compatible with earlier
firmware revisions.
d
system performance. To ensure proper performance
and operation, designers should refer to the guidelines
in "AN231: Si4700/01/02/03 Headphone and Antenna
Interface". Conformance to these guidelines will help to
ensure excellent performance even in weak signal or
noisy environments.
N
ot
R
ec
The Si4703 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction. RDS functionality is
enabled by setting the RDS bit. The device offers two
RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS
block-error levels and synchronization status with
verbose mode.
The Si4703-B17 device possesses an enhanced RDS/
TMC algorithm to improve RDS/TMC reception.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Today's MPX
signal format consists of left + right (L+R) audio, left –
right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS
data as shown in Figure 8.
Setting the RDS mode (RDSM) bit low places the
device in standard RDS mode (default). The device will
set the RDS ready (RDSR) bit for a minimum of 40 ms
when a valid RDS group has been received. Setting the
RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 10
will configure GPIO2 to pulse low for a minimum of 5 ms
14
Confidential Rev. 1.0
57
Figure 8. MPX Signal Spectrum
The Si4703's integrated stereo decoder automatically
decodes the MPX signal. The 0 to 15 kHz (L+R) signal
is the mono output of the FM tuner. Stereo is generated
from the (L+R), (L-R), and a 19 kHz pilot tone. The pilot
tone is used as a reference to recover the (L-R) signal.
Separate left and right channels are obtained by adding
and subtracting the (L+R) and (L-R) signals,
respectively. The Si4703 uses frequency information
from the 19 kHz stereo pilot to recover the 57 kHz RDS/
RBDS signal.
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. The signal level range over which
the stereo to mono blending occurs can be adjusted by
setting the BLNDADJ[1:0] register. Stereo/mono status
can be monitored with the ST register bit and mono
operation can be forced with the MONO register bit.
Freq (MHz) = Spacing (kHz) Channel + Bottom of Band (MHz)
Channel spacing of 50, 100 or 200 kHz is selected with
bits SPACE[1:0]. The channel is selected with bits
CHAN[9:0]. Band selection for Japan, Japan wideband,
or Europe/U.S./Asia is set with BAND[1:0]. The tuning
operation begins by setting the TUNE bit. After tuning
completes, the seek/tune complete (STC) bit will be set
and the RSSI level is available by reading bits
RSSI[7:0]. The TUNE bit must be set low after the STC
bit is set high in order to complete the tune operation
and clear the STC bit.
Seek tuning searches up or down for a channel with an
RSSI greater than or equal to the seek threshold set
with the SEEKTH[7:0] bits. In addition, optional SNR
and/or impulse noise detector criteria may be used to
qualify valid stations. The SKSNR[3:0] bits set the SNR
threshold required. The SKCNT[3:0] bits set the impulse
noise threshold. Using the extra seek qualifiers can
reduce false stops and, in combination with lowering the
RSSI seek threshold, increase the number of found
stations. The SNR and impulse noise detectors are
disabled by default for backwards compatibility.
ec
om
m
en
de
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants, 50 or 75 µs, are used in various regions.
The de-emphasis time constant is programmable with
the DE bit.
The tuning frequency is defined as:
ns
53
ig
38
Frequency (kHz)
The Si4703 uses Silicon Laboratories’ patented and
proven frequency synthesizer technology including a
completely integrated VCO. The frequency synthesizer
generates the quadrature local oscillator signal used to
downconvert the RF input to a low intermediate
frequency. The VCO frequency is locked to the
reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception.
D
es
15 19 23
4.6. Tuning
RDS/
RBDS
ew
Stereo Audio
Left - Right
rN
0
Stereo
Pilot
fo
Mono Audio
Left + Right
adjusted with the SMUTEA[1:0] bits where 00 is the
most attenuated. The soft mute disable (DSMUTE) bit
may be set high to disable this feature.
d
Modulation Level
Si4703-B17
N
ot
R
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted with the DMUTE
bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be
set to either –28 dBFS (default) or –58 dBFS by setting
VOLEXT=1.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in weak signal
conditions. The soft mute attack and decay rate can be
adjusted with the SMUTER[1:0] bits where 00 is the
fastest setting. The soft mute attenuation level can be
Two seek modes are available. When the seek mode
(SKMODE) bit is low and a seek is initiated, the device
seeks through the band, wraps from one band edge to
the other, and continues seeking. If the seek operation
is unable to find a valid channel, the seek failure/band
limit (SF/BL) bit is set high and the device returns to the
channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated,
the device seeks through the band until the band limit is
reached and the SF/BL bit is set high. A seek operation
is initiated by setting the SEEK and SEEKUP bits. After
the seek operation completes, the STC bit is set, and
the RSSI level and tuned channel are available by
reading bits RSSI[7:0] and bits READCHAN[9:0]. During
a seek operation READCHAN[9:0] is also updated and
may be read to determine and report seek progress.
Confidential Rev. 1.0
15
Si4703-B17
The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and
the SF/BL bit is set low. At other times, such as before a
seek operation or after a seek completes and the SF/BL
bit is set high, the channel is valid if the AFC Rail
(AFCRL) bit is set low and the value of RSSI[7:0] is
greater than or equal to SEEKTH[7:0]. Note that if a
valid channel is found but the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation. Setting the STC bit high
clears STC status and SF/BL bits. The seek operation
may be aborted by setting the SEEK bit low at any time.
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Please refer to the Si4703-B17 data sheet for specified
seek/tune times and register use guidelines.
The device can be configured to generate an interrupt
on GPIO2 when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low
interrupt when the STC bit is set by the device.
4.8. Control Interface
ns
ig
D
es
ew
For three-wire operation, a transfer begins when the
SEN pin is set low on a rising SCLK edge. The control
word is latched internally on rising SCLK edges and is
nine bits in length, comprised of a four bit chip address
A7:A4 = 0110b, a read/write bit (write = 0 and read = 1),
and a four bit register address, A3:A0. The ordering of
the control word is A7:A5, R/W, A4:A0. Refer to Section
5. "Register Summary" on page 19 for a list of all
registers and their addresses.
om
m
en
de
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to 2. "Typical Application
Schematic" on page 12. The oscillator must be enabled
or disabled while in powerdown (ENABLE = 0) as shown
in Figure 9, “Initialization Sequence,” on page 18.
Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown.
4.8.1. 3-Wire Control Interface
rN
The Si4703 accepts a 32.768 kHz reference clock to the
RCLK pin. The reference clock is required whenever the
ENABLE bit is set high. Refer to Table 3, “DC
Characteristics,” on page 5 for switching voltage levels
and Table 7, "FM Receiver Characteristics," on page 10
for frequency tolerance information.
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the VIO supply
is applied regardless of the state of the VD or VA
supplies. RCLK is not required for proper register
operation.
fo
4.7. Reference Clock
Please refer to the posted Si4702/03 Internal Crystal
Oscillator Errata for more information.
d
For additional recommendations on optimizing the seek
function, consult "AN284: Si4700/01/02/03 Seek
Adjustability and Settings."
The layout guidelines in Si4700/01/02/03 Evaluation
Board User’s Guide, Section 8.3 Si4703 Daughter Card
should be followed to help ensure robust FM
performance.
4.7.1. Si4703 Internal Crystal Oscillator Errata
N
ot
R
ec
The Si4703-B17 seek/tune performance may be
affected by data activity on the SDIO bus when using
the integrated internal oscillator. SDIO activity results
from polling the tuner for status or communicating with
other devices that share the SDIO bus. If there is SDIO
bus activity while the Si4703-B17 is performing the
seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops.
SDIO activity during all other operational states does
not affect performance.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 3, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 4, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4703-B17 seek and tune operations. This is
16
Confidential Rev. 1.0
Si4703-B17
ns
ig
D
es
ew
Table 8. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation1
Busmode
SEN SDIO GPIO1 GPIO32
Select Method
1
0
0
X
03
1
1
0
X
03
1
0
0
X
04
Xtal Oscillator
1
1
0
X
04
Xtal Oscillator
2
X
X
0
15
2
X
X
1
15
2
NA
NA
NA
NA
Xtal Oscillator
2
NA
NA
NA
NA
Xtal Oscillator
m
en
de
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC should return an acknowledge if an
additional byte of data will be requested. Data transfer
ceases with the STOP command. After every STOP
command, the internal address counter is reset.
Busmode select method 2 only requires the use of the
GPIO3 and GPIO1 pins. The GPIO3 pin should be
driven high on the rising edge of RST. Using this control
interface bus selection method, a 100 k or lower
pull-up resistor should be used on the GPIO3 pin. To
select 2-wire operation of the control interface, the
GPIO1 and GPIO3 pins should be externally driven high
on the rising edge of RST. To select 3-wire operation of
the control interface, the GPIO1 pin should be externally
driven low on the rising edge of RST. Refer to Table 4,
“Reset Timing Characteristics,” on page 6 and Figure 2,
“Reset Timing Parameters for Busmode Select Method
2,” on page 6. Table 8 below summarizes the two bus
selection methods.
rN
For write operations, the device acknowledge is
followed by an eight bit data word latched internally on
rising edges of SCLK. The device always acknowledges
the data by setting SDIO low on the next falling SCLK
edge. An internal address counter automatically
increments to allow continuous data byte writes, starting
with the upper byte of register 02h, followed by the
lower byte of register 02h, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous writes cease. Data transfer ceases with the
STOP command. After every STOP command, the
internal address counter is reset.
fo
For two-wire operation, a transfer begins with the
START condition. The control word is latched internally
on rising SCLK edges and is eight bits in length,
comprised of a seven bit device address equal to
0010000b and a read/write bit (write = 0 and read = 1).
The device acknowledges the address by setting SDIO
low on the next falling SCLK edge.
externally driven low, set to hi-Z or left floating, and the
SDIO pin should be externally driven low on the rising
edge of RST. The GPIO3 pin has an internal 1 M
pulldown resistor to ensure proper bus mode selection.
To select 2-wire operation of the control interface, the
SEN pin should be externally driven high on the rising
edge of RST. To select 3-wire operation of the control
interface, the SEN pin should be externally driven low
on the rising edge of RST. Refer to Table 4, “Reset
Timing Characteristics,” on page 6 and Figure 1, “Reset
Timing Parameters for Busmode Select Method 1,” on
page 6.
d
4.8.2. 2-wire Control Interface
ec
om
For details on timing specifications and diagrams, refer
to Table 6, “2-Wire Control Interface Characteristics1,”
on page 8, Figure 5, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 9 and Figure 6,
“2-Wire Control Interface Read and Write Timing
Diagram,” on page 9.
R
4.9. Reset, Powerup, and Powerdown
N
ot
Driving the RST pin low will disable the Si4703 and its
control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
one of two methods may be used to select between
2-wire and 3-wire control interface operation.
Busmode select method 1 requires the use of the
GPIO3, SEN, and SDIO pins. The GPIO3 pin should be
Bus
mode
3-wire
2-wire
3-wire
2-wire
3-wire
2-wire
NA
NA
Notes:
1. All parameters applied on rising edge of RST.
2. GPIO3 is internally pulled down with a 1 M resistor.
3. GPIO3 should be externally driven low, set to high-Z
(10 M or greater pull-up) or float.
4. GPIO3 should be left floating.
5. GPIO3 should be externally driven high (100 kor
smaller pull-up).
Confidential Rev. 1.0
17
Si4703-B17
3. (Optional) Remove RCLK.
4. Remove VA and VD supplies as needed.
To power up the device (after power down):
ns
1. Note that VIO is still supplied in this scenario. If VIO is not
supplied, refer to device initialization procedure above.
D
es
ig
2. (Optional) Set the AHIZEN bit low to disable the dc bias of
0.5 x VIO volts at the LOUT and ROUT pins, but preserve
the states of the other bits in Register 07h. Note that in
powerup the LOUT and ROUT pins are set to the common
mode voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
ew
3. Supply VA and VD.
4. Provide RCLK. Wait 500 ms for oscillator startup when
using internal oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device.
VA,VD Supply
VIO Supply
d
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x VIO on the LOUT and ROUT pins to prevent the
ESD diodes from clamping to the VIO or GND rail in
response to the output swing of the other device. The
bias point is set with a 370 k resistor to VIO and GND.
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and VIO is supplied. In
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics1,2,” on page 10, regardless of
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
2. Set the ENABLE bit high and the DISABLE bit high to
place the device in powerdown mode. Note that all register
states are maintained so long as VIO is supplied and the
RST pin is high.
rN
4.10. Audio Output Summation
Register 07h. Note that in powerup the LOUT and ROUT
pins are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of AHIZEN.
fo
When proper voltages are applied to the Si4703, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE = 0
and DISABLE = 0. Setting ENABLE = 1 and DISABLE
= 0 puts the device in powerup mode. To power down
the device, the ENABLE and DISABLE bits should both
be written to 1. After being written to 1, both bits will be
cleared as part of the internal device powerdown
sequence. To put the device back into powerup mode,
set ENABLE = 1 and DISABLE = 0 as described above.
The ENABLE bit should never be written to a 0.
RST Pin
de
4.11. Initialization Sequence
RCLK Pin
Refer to Figure 9, “Initialization Sequence,” on page 18.
ENABLE Bit
en
To initialize the device:
1. Supply VA and VD.
om
m
2. Supply VIO while keeping the RST pin low. Note that steps
1 and 2 may be reversed. Power supplies may be
sequenced in any order.
ec
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset, Powerup,
and Powerdown" on page 17.
3
4
5
4.12. Programming Guide
Refer to "AN230: Si4700/01 Programming Guide" for
control interface programming information.
N
ot
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the powerup
time (as specified by Table 7, “FM Receiver
Characteristics1,2,” on page 10) before continuing with
normal part operation.
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc bias of
0.5 x VIO volts at the LOUT and ROUT pins while in
powerdown, but preserve the states of the other bits in
18
2
Figure 9. Initialization Sequence
R
4. Provide RCLK. Steps 3 and 4 may be reversed when using
an external oscillator. Wait 500 ms for oscillator startup
when using internal oscillator.
1
Confidential Rev. 1.0
R
ec
Confidential Rev. 1.0
BOOTCONFIG
STATUSRSSI
READCHAN
RDSA
RDSB
RDSC
RDSD
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
STC
BLERB[1:0]2
RDSR
XOSCEN AHIZEN
D9
d
BLERD[1:0]2
0
SEEK
fo
READCHAN[9:0]
D
es
ig
ns
D2
0
ENABLE
D0
GPIO1[1:0]
0
D1
SKCNT[3:0]
VOLUME[3:0]
GPIO2[1:0]
0
FIRMWARE[5:0]
D3
RSSI[7:0]
SPACE[1:0]
GPIO3[1:0]
0
D4
CHAN[9:0]
SKSNR[3:0]
BAND[1:0]
ew
RDSD[15:0]
RDSC[15:0]
rN
RDSB[15:0]
RDSA[15:0]
ST
DISABLE
0
D5
MFGID[11:0]
D6
BLNDADJ[1:0]
0
D7
DEV[3:0]
D8
RDSPRF VOLEXT
0
BLERA[1:0]2
AGCD
0
SKMODE SEEKUP
D10
de
RDSS2
en
AFCRL
m
BLERC[1:0]2
SF/BL
DE
0
RDSM
SEEKTH[7:0]
RDS
0
0
SMUTEA[1:0]
om
0
0
MONO
D11
Notes:
1. Any register not listed is reserved and should not be written. Writing to reserved registers may result in unpredictable behavior.
2. Available in RDS verbose mode only.
TEST2
TEST1
07h
08h
SYSCONFIG3
06h
SMUTER[1:0]
SYSCONFIG2
0
05h
TUNE
SYSCONFIG1 RDSIEN STCIEN
CHANNEL
04h
03h
D12
REV[5:0]
D13
PN[3:0]
D14
POWERCFG DSMUTE DMUTE
CHIPID
01h
02h
DEVICEID
00h
D15
N
ot
Name
Reg1
5. Register Summary
Si4703-B17
19
Si4703-B17
6. Register Descriptions
Register 00h. Device ID
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
Name
PN[3:0]
MFGID[11:0]
Type
R
R
D3
D2
D1
15:12
PN[3:0]
Part Number.
0x01 = Si4702/03
11:0
MFGID[11:0]
Manufacturer ID.
0x242
ig
Function
D
es
Name
ew
Bit
ns
Reset value = 0x1242
D14
D13
D12
D11
D10
D9
D8
D7
Name
REV[5:0]
DEV[3:0]
Type
R
R
de
d
Reset value = 0x0800 for Si4703 Revision B.
D6
Name
15:10
REV[5:0]
Chip Version.
0x02 = Rev B
9:6
DEV[3:0]
Device.
0 before powerup.
0001 after powerup = Si4702.
1001 after powerup = Si4703.
Function
FIRMWARE[6:0] Firmware Version.
0 before powerup.
Firmware version after powerup.
N
ot
R
ec
5:0
om
m
en
Bit
20
D5
fo
D15
rN
Register 01h. Chip ID
Bit
D0
Confidential Rev. 1.0
D4
D3
D2
FIRMWARE[6:0]
R
D1
D0
Si4703-B17
Register 02h. Power Configuration
Bit
D15
D14
D13 D12 D11
Name DSMUTE DMUTE MONO
Type
R/W
R/W
R/W
0
D10
D9
D8
D7
D6
0
DISABLE
R/W
R/W
RDSM SKMODE SEEKUP SEEK
R/W
R/W
R/W
R/W
R/W
D5 D4 D3 D2 D1
0
0
0
0
0
D0
ENABLE
R/W R/W R/W R/W R/W
R/W
Reset value = 0x0000
Name
Function
15
DSMUTE
14
DMUTE
Mute Disable.
0 = Mute enable (default).
1 = Mute disable.
13
MONO
Mono Select.
0 = Stereo (default).
1 = Force mono.
12
Reserved
11
RDSM
10
SKMODE
Seek Mode.
0 = Wrap at the upper or lower band limit and continue seeking (default).
1 = Stop seeking at the upper or lower band limit.
9
SEEKUP
Seek Direction.
0 = Seek down (default).
1 = Seek up.
8
SEEK
ns
Bit
ew
D
es
ig
Softmute Disable.
0 = Softmute enable (default).
1 = Softmute disable.
rN
Reserved.
Always write to 0.
m
en
de
d
fo
RDS Mode.
0 = Standard (default).
1 = Verbose.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
om
Seek.
0 = Disable (default).
1 = Enable.
N
ot
R
ec
Notes:
1. Seek begins at the current channel, and goes in the direction specified with the SEEKUP
bit. Seek operation stops when a channel is qualified as valid according to the seek
parameters, the entire band has been searched (SKMODE = 0), or the upper or lower
band limit has been reached (SKMODE = 1).
2. The STC bit is set high when the seek operation completes and/or the SF/BL bit is set
high if the seek operation was unable to find a channel qualified as valid according to the
seek parameters. The STC and SF/BL bits must be set low by setting the SEEK bit low
before the next seek or tune may begin.
3. Seek performance for 50 kHz channel spacing varies according to RCLK tolerance.
Silicon Laboratories recommends ±50 ppm RCLK crystal tolerance for 50 kHz seek
performance.
4. A seek operation may be aborted by setting SEEK = 0.
Confidential Rev. 1.0
21
Si4703-B17
Function
7
Reserved
Reserved.
Always write to 0.
6
DISABLE
Powerup Disable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
5:1
Reserved
Reserved.
Always write to 0.
0
ENABLE
Powerup Enable.
Refer to “4.9. Reset, Powerup, and Powerdown”.
Default = 0.
ns
Name
Register 03h. Channel
D15
Name TUNE
Type
R/W
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
0
CHANNEL[9:0]
R/W
R/W
R/W
R/W
R/W
R/W
D3
D2
D1
D0
ew
Bit
D
es
ig
Bit
rN
Reset value = 0x0000
Name
Function
15
TUNE
Tune.
0 = Disable (default).
1 = Enable.
The tune operation begins when the TUNE bit is set high. The STC bit is set high
when the tune operation completes. The STC bit must be set low by setting the TUNE
bit low before the next tune or seek may begin.
14:10
Reserved
Reserved.
Always write to 0.
9:0
CHAN[9:0]
Channel Select.
Channel value for tune operation.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
CHAN[9:0] is not updated during a seek operation. READCHAN[9:0] provides the
current tuned channel and is updated during a seek operation and after a seek or
tune operation completes. Channel spacing is set with the bits SPACE 05h[5:4].
N
ot
R
ec
om
m
en
de
d
fo
Bit
22
Confidential Rev. 1.0
Si4703-B17
Register 04h. System Configuration 1
Bit
D15
D14
Name RDSIEN STCIEN
Type
R/W
R/W
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
RDS
DE
AGCD
0
0
BLNDADJ[1:0]
GPIO3[1:0]
GPIO2[1:0]
GPIO1[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value = 0x0000
Name
Function
15
RDSIEN
RDS Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting RDSIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when
the RDSR 0Ah[15] bit is set.
14
STCIEN
Seek/Tune Complete Interrupt Enable.
0 = Disable Interrupt (default).
1 = Enable Interrupt.
Setting STCIEN = 1 and GPIO2[1:0] = 01 will generate a 5 ms low pulse on GPIO2 when
the STC 0Ah[14] bit is set.
13
Reserved
12
RDS
11
DE
10
AGCD
9:8
Reserved
ew
rN
Reserved.
Always write to 0.
fo
RDS Enable.
0 = Disable (default).
1 = Enable.
om
m
Reserved.
Always write to 0.
en
AGC Disable.
0 = AGC enable (default).
1 = AGC disable.
de
d
De-emphasis.
0 = 75 µs. Used in USA (default).
1 = 50 µs. Used in Europe, Australia, Japan.
BLNDADJ[1:0] Stereo/Mono Blend Level Adjustment.
Sets the RSSI range for stereo/mono blend.
00 = 31–49 RSSI dBµV (default).
01 = 37–55 RSSI dBµV (+6 dB).
10 = 19–37 RSSI dBµV (–12 dB).
11 = 25–43 RSSI dBµV (–6 dB).
ST bit set for RSSI values greater than low end of range.
R
ec
6:7
D
es
ig
ns
Bit
GPIO3[1:0]
General Purpose I/O 3.
00 = High impedance (default).
01 = Mono/Stereo indicator (ST). The GPIO3 will output a logic high when the device is in
stereo, otherwise the device will output a logic low for mono.
10 = Low.
11 = High.
N
ot
5:4
Confidential Rev. 1.0
23
Si4703-B17
Name
Function
3:2
GPIO2[1:0]
General Purpose I/O 2.
00 = High impedance (default).
01 = STC/RDS interrupt. A logic high will be output unless an interrupt occurs as
described below.
10 = Low.
11 = High.
Setting STCIEN = 1 will generate a 5 ms low pulse on GPIO2 when the STC 0Ah[14] bit is
set. Setting RDSIEN = 1 will generate a 5 ms low pulse on GPIO2 when the RDSR
0Ah[15] bit is set.
1:0
GPIO1[1:0]
General Purpose I/O 1.
00 = High impedance (default).
01 = Reserved.
10 = Low.
11 = High.
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Bit
24
Confidential Rev. 1.0
Si4703-B17
Register 05h. System Configuration 2
Bit
D15
D14
D13
D12
D11
Name
SEEKTH[7:0]
Type
R/W
D10
D9
D8
D7
D6
D5
D4
D3
BAND[1:0] SPACE[1:0]
R/W
D2
D1
D0
VOLUME[3:0]
R/W
R/W
Reset value = 0x0000
Name
Function
15:8
SEEKTH[7:0]
RSSI Seek Threshold.
0x00 = min RSSI (default).
0xFF = max RSSI.
SEEKTH presents the logarithmic RSSI threshold for the seek operation. The Si4703
will not validate channels with RSSI below the SEEKTH value. SEEKTH is one of
multiple parameters that can be used to validate channels. For more information, see
"AN284: Si4700/01 Firmware 15 Seek Adjustability and Settings."
7:6
BAND[1:0]
Band Select.
00 = 87.5–108 MHz (USA,Europe) (Default).
01 = 76–108 MHz (Japan wide band).
10 = 76–90 MHz (Japan).
11 = Reserved.
5:4
SPACE[1:0]
Channel Spacing.
00 = 200 kHz (USA, Australia) (default).
01 = 100 kHz (Europe, Japan).
10 = 50 kHz.
3:0
VOLUME[3:0]
d
fo
rN
ew
D
es
ig
ns
Bit
om
m
en
de
Volume.
Relative value of volume is shifted –30 dBFS with the VOLEXT 06h[8] bit.
VOLEXT = 0 (default).
0000 = mute (default).
0001 = –28 dBFS.
:
:
1110 = –2 dBFS.
1111 = 0 dBFS.
N
ot
R
ec
VOLEXT = 1.
0000 = mute.
0001 = –58 dBFS.
:
:
1110 = –32 dBFS.
1111 = –30 dBFS.
FS = full scale.
Volume scale is logarithmic.
Confidential Rev. 1.0
25
Si4703-B17
Register 06h. System Configuration 3
Bit
D15
D14
D13
D12
Name SMUTER[1:0] SMUTEA[1:0]
Type
R/W
R/W
D11 D10
0
0
D9
D8
D7
RDSPRF VOLEXT
R/W R/W
R/W
D6
D5
D4
D3
D2
D1
SKSNR[3:0]
SKCNT[3:0]
R/W
R/W
R/W
D0
Name
Function
15:14
SMUTER[1:0]
Softmute Attack/Recover Rate.
00 = fastest (default).
01 = fast.
10 = slow.
11 = slowest.
13:12
SMUTEA[1:0]
Softmute Attenuation.
00 = 16 dB (default).
01 = 14 dB.
10 = 12 dB.
11 = 10 dB.
11:10
Reserved
Reserved.
Always write to zero.
9
RDSPRF
RDS High-Performance Mode.
0 = disabled (default).
1 = enabled.
Refer to 4.4. "RDS/RBDS Processor and Functionality" on page 14.
Refer to "AN281: Si4700/01/02/03 Firmware Change List."
8
VOLEXT
Extended Volume Range.
0 = disabled (default).
1 = enabled.
This bit attenuates the output by 30 dB. With the bit set to 0, the 15 volume settings
adjust the volume between 0 and –28 dBFS. With the bit set to 1, the 15 volume settings adjust the volume between –30 and –58 dBFS.
Refer to 4.5. "Stereo Audio Processing" on page 14.
Refer to "AN281: Si4700/01/02/03 Firmware Change List."
7:4
SKSNR[3:0]
3:0
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Bit
N
ot
Reset value = 0x0000
R
ec
Seek SNR Threshold.
0000 = disabled (default).
0001 = min (most stops).
1111 = max (fewest stops).
Required channel SNR for a valid seek channel.
26
SKCNT[3:0]
Seek FM Impulse Detection Threshold.
0000 = disabled (default).
0001 = max (most stops).
1111 = min (fewest stops).
Allowable number of FM impulses for a valid seek channel.
Confidential Rev. 1.0
Si4703-B17
Register 07h. Test 1
Bit
D15
D14
D13
D12
D11 D10
D9
D8
Name XOSCEN AHIZEN
Type
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
R/W
R/W
Reset value = 0x0100
Name
Function
15
XOSCEN
Crystal Oscillator Enable.
0 = Disable (default).
1 = Enable.
The internal crystal oscillator requires an external 32.768 kHz crystal as shown in
2. "Typical Application Schematic" on page 12. The oscillator must be enabled before
powerup (ENABLE = 1) as shown in Figure 9, “Initialization Sequence,” on page 18. It
should only be disabled after powerdown (ENABLE = 0). Bits 13:0 of register 07h
must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup.
Refer to Si4702/03 Internal Crystal Oscillator Errata.
14
AHIZEN
Audio High-Z Enable.
0 = Disable (default).
1 = Enable.
Setting AHIZEN maintains a dc bias of 0.5 x VIO on the LOUT and ROUT pins to prevent the ESD diodes from clamping to the VIO or GND rail in response to the output
swing of another device. Register 07h containing the AHIZEN bit must not be written
during the powerup sequence and high-Z only takes effect when in powerdown and
VIO is supplied. Bits 13:0 of register 07h must be preserved as 0x0100 while in powerdown and as 0x3C04 while in powerup.
13:0
Reserved
de
d
fo
rN
ew
D
es
ig
ns
Bit
N
ot
R
ec
om
m
en
Reserved.
If written, these bits should be read first and then written with their pre-existing values. Do not write during powerup.
Confidential Rev. 1.0
27
Si4703-B17
Register 08h. Test 2
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Type
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
15:0
Reserved
Function
ns
Name
Reserved.
If written, these bits should be read first and then written with their pre-existing values. Do not write during powerup.
D
es
ig
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Type
R/W
D7
Reserved
en
m
om
ec
R
N
ot
28
D3
D2
D1
D0
Reserved.
If written, these bits should be read first and then written with their pre-existing values. Do not write during powerup.
d
15:0
D4
Function
de
Name
D5
fo
Reset value = 0x0000
Bit
D6
rN
Bit
ew
Register 09h. Boot Configuration
Confidential Rev. 1.0
Si4703-B17
Register 0Ah. Status RSSI
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
Name RDSR STC SF/BL AFCRL RDSS BLERA[1:0]
ST
RSSI[7:0]
Type
R
R
R
R
R
R
R
R
D2
D1
D0
Reset value = 0x0000
Name
Function
15
RDSR
14
STC
Seek/Tune Complete.
0 = Not complete (default).
1 = Complete.
The seek/tune complete flag is set when the seek or tune operation completes. Setting
the SEEK 02h[8] or TUNE 03h[15] bit low will clear STC.
13
SF/BL
Seek Fail/Band Limit.
0 = Seek successful.
1 = Seek failure/Band limit reached.
The SF/BL flag is set high when SKMODE 02h[10] = 0 and the seek operation fails to
find a channel qualified as valid according to the seek parameters.
The SF/BL flag is set high when SKMODE 02h[10] = 1 and the upper or lower band limit
has been reached.
The SEEK 02h[8] bit must be set low to clear SF/BL.
12
AFCRL
AFC Rail.
0 = AFC not railed.
1 = AFC railed, indicating an invalid channel. Audio output is softmuted when set.
AFCRL is updated after a tune or seek operation completes and indicates a valid or
invalid channel. During normal operation, AFCRL is updated to reflect changing RF environments.
11
RDSS
RDS Synchronized.
0 = RDS decoder not synchronized (default).
1 = RDS decoder synchronized.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
10:9
BLERA[1:0]
ig
D
es
ec
om
m
en
de
d
fo
rN
ew
RDS Ready.
0 = No RDS group ready (default).
1 = New RDS group ready.
Refer to “4.4. RDS/RBDS Processor and Functionality”.
ns
Bit
N
ot
R
RDS Block A Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM 02h[11] = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
Confidential Rev. 1.0
29
Si4703-B17
Bit
Name
Function
8
ST
7:0
RSSI[7:0]
Stereo Indicator.
0 = Mono.
1 = Stereo.
Stereo indication is also available on GPIO3 by setting GPIO3 04h[5:4] = 01.
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
RSSI (Received Signal Strength Indicator).
RSSI is measured units of dBµV in 1 dB increments with a maximum of approximately
75 dBµV. Si4703-B17 does not report RSSI levels greater than 75 dBuV.
30
Confidential Rev. 1.0
Si4703-B17
Register 0Bh. Read Channel
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
Name BLERB[1:0] BLERC[1:0] BLERD[1:0]
Type
R
R
D5
D4
D3
D2
D1
D0
READCHAN[9:0]
R
R
Reset value = 0x0000
BLERB[1:0]
RDS Block B Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
13:12
BLERC[1:0]
RDS Block C Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
11:10
BLERD[1:0]
RDS Block D Errors.
00 = 0 errors requiring correction.
01 = 1–2 errors requiring correction.
10 = 3–5 errors requiring correction.
11 = 6+ errors or error in checkword, correction not possible.
Available only in RDS Verbose mode (RDSM = 1).
Refer to “4.4. RDS/RBDS Processor and Functionality”.
ig
15:14
ns
Function
D
es
Name
R
ec
om
READCHAN[9:0] Read Channel.
If BAND 05h[7:6] = 00, then Freq (MHz) = Spacing (MHz) x Channel + 87.5 MHz.
If BAND 05h[7:6] = 01, BAND 05h[7:6] = 10, then
Freq (MHz) = Spacing (MHz) x Channel + 76 MHz.
READCHAN[9:0] provides the current tuned channel and is updated during a seek
operation and after a seek or tune operation completes. Spacing and channel are set
with the bits SPACE 05h[5:4] and CHAN 03h[9:0].
N
ot
9:0
m
en
de
d
fo
rN
ew
Bit
Confidential Rev. 1.0
31
Si4703-B17
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSA[15:0]
Type
R
D6
D5
D4
D3
D5
D4
D
es
Register 0Ch. RDSA
D2
D1
D0
Reset value = 0x0000
15:0
RDSA
Function
ns
Name
RDS Block A Data.
ig
Bit
Register 0Dh. RDSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
RDSB[15:0]
Type
R
rN
Name
Reset value = 0x0000
15:0
RDSB
Function
fo
Name
RDS Block B Data.
N
ot
R
ec
om
m
en
de
d
Bit
32
D6
Confidential Rev. 1.0
D3
ew
Bit
D2
D1
D0
Si4703-B17
Register 0Eh. RDSC
Bit
D15
D14
D13
D12
D11
D10
D9
D8
D7
Name
RDSC[15:0]
Type
R
D6
D5
D4
D5
D4
D3
D2
D1
D0
Reset value = 0x0000
15:0
RDSC
Function
ns
Name
RDS Block C Data.
Register 0Fh. RDSD
D15
D14
D13
D12
D11
D10
D9
D8
D7
RDSD[15:0]
Type
R
Reset value = 0x0000
15:0
RDSD
D1
D0
Function
fo
Name
D2
RDS Block D Data.
N
ot
R
ec
om
m
en
de
d
Bit
D3
rN
Name
D6
ew
Bit
D
es
ig
Bit
Confidential Rev. 1.0
33
Si4703-B17
16
15 GND
8
9
10
11 VD
Name
1, 20
NC
2
FMIP
3
RFGND
4, 12, 15, PAD
GND
Ground. Connect to ground plane on PCB.
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
10
VIO
11
14
LOUT
N
ot
16
ROUT
R
13
VD
17, 18, 19
34
VA
Description
FM RF inputs.
fo
Pin Number(s)
ec
rN
Top View
No Connect. Leave floating.
D
es
7
ig
13 ROUT
12 GND
6
ns
14 LOUT
GND
PAD
ew
5
VA
RST
GPIO3
4
17
VIO
GND
GPIO2
3
18
RCLK
RFGND
GPIO1
2
19
SDIO
FMIP
20
SCLK
1
SEN
NC
NC
7. Pin Descriptions: Si4703-GM
om
m
en
de
d
RF ground. Connect to ground plane on PCB.
External reference oscillator input.
I/O supply voltage.
Digital supply voltage. May be connected directly to battery.
Right audio output.
Left audio output.
Analog supply voltage. May be connected directly to battery.
GPIO3, GPIO2, General purpose input/output.
GPIO1
Confidential Rev. 1.0
Si4703-B17
8. Ordering Guide
Part
Number*
Description
Si4703-B17-GM Portable Broadcast Radio Tuner
FM Stereo with RDS
Firmware Revision 16
Package
Type
Operating
Temperature
QFN
Pb-free
–20 to 85 °C
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
Confidential Rev. 1.0
35
Si4703-B17
9. Package Markings (Top Marks)
D
es
ig
ns
9.1. Si4703 Top Mark
9.2. Top Mark Explanation
YAG Laser
Font Size:
1.5 point (0.53 mm) Right Justified
Line 1 Marking:
Part Number
03 = Si4703
Firmware Revision
17 = Firmware Revision 17
B = Die Revision
B = Revision B Die
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date.
N
ot
R
ec
om
m
en
de
Y = Year
WW = Workweek
36
rN
fo
Line 3 Marking:
d
Line 2 Marking:
ew
Mark Method:
Confidential Rev. 1.0
Si4703-B17
10. Package Outline: Si4703-GM
fo
rN
ew
D
es
ig
ns
Figure 10 illustrates the package details for the Si4703-GM. Table 9 lists the values for the dimensions shown in
the illustration.
de
d
Figure 10. 20-Pin Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Millimeters
en
Symbol
Symbol
Millimeters
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.18
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
E
E2
om
1.70
1.75
0.50 BSC
R
e
1.65
3.00 BSC
1.65
N
ot
D2
3.00 BSC
ec
D
1.70
Min
m
Min
Nom
Max
2.53 BSC
1.75
Notes:
1. All dimensions are shown in millimeters unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Confidential Rev. 1.0
37
Si4703-B17
11. PCB Land Pattern: Si4703-GM
de
d
fo
rN
ew
D
es
ig
ns
Figure 11 illustrates the PCB land pattern details for the Si4703-GM. Table 10 lists the values for the dimensions
shown in the illustration.
N
ot
R
ec
om
m
en
Figure 11. PCB Land Pattern
38
Confidential Rev. 1.0
Si4703-B17
Table 10. PCB Land Pattern Dimensions
Min
D
Symbol
Max
2.71 REF
D2
1.60
Min
Max
GE
2.10
—
W
—
0.34
—
1.80
e
0.50 BSC
X
E
2.71 REF
Y
E2
1.60
f
1.80
2.53 BSC
GD
Millimeters
2.10
0.28
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
ew
D
es
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
ns
Millimeters
ig
Symbol
rN
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
de
d
fo
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
N
ot
R
ec
om
m
en
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Confidential Rev. 1.0
39
Si4703-B17
ADDITIONAL REFERENCE RESOURCES
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
AN230: Si4700/01/02/03 Programming Guide
AN231: Si4700/01/02/03 Headphone and Antenna Interface
Si4700/01/02/03 EVB User’s Guide
AN234: Si4700/01/02/03 EVB Test Procedure
AN235: Si4700/01/02/03 EVB Quick Start Guide
AN243: Using RDS/RBDS with the Si4701/03
AN281: Si4700/01/02/03 Firmware Change List
AN284: Si4700/01/02/03 Seek Adjustability and Settings
AN299: External 32.768 kHz Crystal Oscillator
Si4702/03 Internal Crystal Oscillator Errata
Si4700/01/02/03 Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs
recommends an all lower case user name.
ns
ig
40
Confidential Rev. 1.0
Si4703-B17
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
NOTES:
Confidential Rev. 1.0
41
Si4703-B17
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, Texas 78701
Tel:1+ (512) 416-8500
Fax:1+ (512) 416-9669
Toll Free:1+ (877) 444-3032
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
ns
Email: FMinfo@silabs.com
Internet: www.silabs.com
N
ot
R
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume
any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holder
42
Confidential Rev. 1.0