SI4730-B20-GMR

Si 4 7 3 x - B20 B ROADCAST M ULTI -B AND R ADIO R ECEIVER Features  FM band support: 76–108 MHz  Adaptive noise suppression  AM band support: 520–1710 kHz  AM/FM digital tuning  SW band support: 2.3–21.85 MHz  EN55020 compliant        RDS/RBDS processor       (Si4731/35/37/39) Optional digital audio output (Si4731/35/37/39) 2-wire control interface 2.7 to 5.5 V supply voltage Firmware upgradeable Wide range of ferrite loop sticks and air loop antennas supported 3 x 3 x 0.55 mm 20-pin QFN package  Pb-free/RoHS compliant Ordering Information: See page 18. Pin Assignments Si473x-GM (Top View) Applications     FM AM Si4730 76 – 108 MHz  Si4731 76 – 108 MHz  Si4734 64 – 108 MHz  Si4735 64 – 108 MHz  Si4736 76 – 108 MHz  Si4737 76 – 108 MHz  Si4738 76 – 108 MHz Si4739 76 – 108 MHz Rev. 0.5 10/08 RDS 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD AMI 4 13 ROUT RST 5 Si473x Product Selector Guide Part 20 SW/LW 12 GND 6 7 8 9 10 VIO   1 RCLK   NC Cellular handsets Emergency radios Clock radios Modules Mini HiFi Boom boxes SDIO   SCLK  Table and portable radios Audio video receivers Stereos Mini/micro systems CD/DVD players Portable media players SEN  DFS   Programmable soft mute control GPO3/DCLK   Volume control GPO2/INT   Programmable reference clock GPO1   No manual alignment necessary NC  (Si4734/35) LW band support: 153–279 kHz (Si4734/35) Weather band support: 162.4– 162.55 MHz (Si4736/37/38/39) 1050 Hz alert tone detection (Si4736/37/38/39) Excellent real-world performance Freq synthesizer with integrated VCO Advanced seek tuning Automatic frequency control (AFC) Automatic gain control (AGC) Integrated LDO regulator Digital FM stereo decoder Programmable de-emphasis 11 VDD WB Patents Pending          Notes: 1. Place Si473x as close as possible to antenna jack and keep the FMI and AMI traces as short as possible. 2. Contact your local sales representatives for more information or to obtain application notes.  Copyright © 2008 by Silicon Laboratories Si473x-B20 Si473x-B20 2 Rev. 0.5 Si473x-B20 TABLE O F C ONTENTS Section Page 1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Typical AM/FM Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions: Si473x-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline: Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. PCB Land Pattern: Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 0.5 3 Si473x-B20 1. Product Overview The Si473x receivers are the industry's first fully-integrated multiband radio receiver ICs from antenna input to audio output. They require minimal external components with no factory alignment. The Si473x receivers reduce the receiver footprint by >90% versus traditional AM/FM solutions. The Si473x also offer best-in-class performance with the most features. The high integration and complete system production test simplifies design-in, increases system quality, and improves manufacturability. The Si473x receivers include advanced seek algorithms, adjustable soft mute, auto-calibrated digital tuning, and FM stereo processing. In addition, the Si473x ICs provide a programmable reference clock and an I2C-compatible 2-wire control interface. The Si4731/35/37/39 incorporates a digital processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS), including all required symbol decoding, block synchronization, error detection, and error correction functions. Using these features, the Si4731/35/37/39 enables broadcast data such as station identification and song name to be displayed to the end user. 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Supply Voltage VDD 2.7 — 5.5 V Interface Supply Voltage VIO 1.5 — 3.6 V Power Supply Powerup Rise Time VDDRISE 10 — — µs Interface Power Supply Powerup Rise Time VIORISE 10 — — µs TA –20 25 85 C Ambient Temperature Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. 4 Rev. 0.5 Si473x-B20 Table 2. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Supply Voltage VDD –0.5 to 5.8 V Interface Supply Voltage VIO –0.5 to 3.9 V Input Current3 IIN 10 mA Voltage3 VIN –0.3 to (VIO + 0.3) V Operating Temperature TOP –40 to 95 C Storage Temperature TSTG –55 to 150 C 0.4 VPK Input RF Input Level4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si473x devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. At RF input pins, FMI and AMI. Rev. 0.5 5 Si473x-B20 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit — 19.2 22 mA — 19.8 23 mA IFM — 19.9 23 mA Supply Current IFM — 19.2 22 mA Supply Current1 IFM — 19.8 23 mA IAM — 17.3 20.5 mA Interface Supply Current IIO — 320 600 µA VDD Powerdown Current IDDPD — 10 20 µA VIO Powerdown Current IIOPD — 1 10 µA FM Mode Supply Current Supply Current IFM 1 IFM RDS Supply Current2 Low SNR level WB Mode (Si4736/37/38/39 only) Low SNR level AM Mode (Si4730/31/34/35/36/37 only) Supply Current Supplies and Interface SCLK, RCLK inactive High Level Input Voltage3 VIH 0.7 x VIO — VIO + 0.3 V 3 VIL –0.3 — 0.3 x VIO V High Level Input Current3 IIH VIN = VIO = 3.6 V –10 — 10 µA 3 IIL VIN = 0 V, VIO = 3.6 V –10 — 10 µA High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V 4 VOL IOUT = –500 µA — — 0.2 x VIO V Low Level Input Voltage Low Level Input Current Low Level Output Voltage Notes: 1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions. 2. Specifications are guaranteed by characterization. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. 6 Rev. 0.5 Si473x-B20 Table 4. Reset Timing Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 3. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and GPO2 low. tSRST RST 70% GPO1 70% GPO2/ INT tHRST 30% 30% 70% 30% Figure 1. Reset Timing Parameters for Busmode Select Rev. 0.5 7 Si473x-B20 Table 5. 2-Wire Control Interface Characteristics1,2,3 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 — 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO  Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO  Hold (START) tHD:STA 0.6 — — µs SDIO Input to SCLK  Setup tSU:DAT 100 — — ns SDIO Input to SCLK  Hold4,5 tHD:DAT 0 — 900 ns SCLK input to SDIO  Setup (STOP) tSU:STO 0.6 — — µs STOP to START Time tBUF 1.3 — — µs SDIO Output Fall Time tf:OUT — 250 ns — 300 ns Cb 20 + 0.1 ----------1pF SDIO Input, SCLK Rise/Fall Time tf:IN tr:IN Cb 20 + 0.1 ----------1pF SCLK, SDIO Capacitive Loading Cb — — 50 pF Input Filter Pulse Suppression tSP — — 50 ns Notes: 1. When VIO = 0 V, SCLK and SDIO are low impedance. 2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si473x delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT specification. 5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be violated as long as all other timing parameters are met. 8 Rev. 0.5 Si473x-B20 SCLK 70% SDIO 70% tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 30% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK STOP Figure 3. 2-Wire Control Interface Read and Write Timing Diagram Rev. 0.5 9 Si473x-B20 Table 6. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 — 1000 ns DCLK Pulse Width High tDCH 10 — — ns DCLK Pulse Width Low tDCL 10 — — ns DFS Set-up Time to DCLK Rising Edge tSU:DFS 5 — — ns DFS Hold Time from DCLK Rising Edge tHD:DFS 5 — — ns tPD:DOUT 0 — 12 ns DOUT Propagation Delay from DCLK Falling Edge tDCH tDCL DCLK tDCT DFS tHD:DFS tSU:DFS DOUT tPD:OUT Figure 4. Digital Audio Interface Timing Parameters, I2S Mode 10 Rev. 0.5 Si473x-B20 Table 7. FM Receiver Characteristics1,2 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Input Frequency Test Condition fRF Min Typ Max Unit 76 — 108 MHz Sensitivity with Headphone Network3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF Sensitivity with 50  Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF RDS Sensitivity6 f = 2 kHz, RDS BLER < 5% — 15 — µV EMF 3 4 5 k 4 5 6 pF 100 105 — dBµV EMF m = 0.3 40 50 — dB Adjacent Channel Selectivity ±200 kHz 35 50 — dB Alternate Channel Selectivity ±400 kHz 60 70 — dB In-band 35 — — dB 72 80 90 mVRMS — — 1 dB LNA Input Resistance6,7 LNA Input Capacitance Input 6,7 IP36,8 AM Suppression3,4,6,7 Spurious Response Rejection6 Audio Output Voltage3,4,7 3,7,9 Audio Output L/R Imbalance Low6 –3 dB — — 30 Hz Audio Frequency Response High6 –3 dB 15 — — kHz 25 — — dB 55 63 — dB — 58 — dB — 0.1 0.5 % FM_DEEMPHASIS = 2 70 75 80 µs FM_DEEMPHASIS = 1 45 50 54 µs RL Single-ended 10 — — k CL Single-ended — — 50 pF Audio Frequency Response Audio Stereo Separation7,9 Audio Mono S/N 3,4,5,7,10 Audio Stereo S/N 4,5,7,10,11 Audio THD3,7,9 De-emphasis Time Constant6 Audio Output Load Resistance6,10 Audio Output Load Capacitance6,10 Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Test Board Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. At temperature (25°C). Rev. 0.5 11 Si473x-B20 Table 7. FM Receiver Characteristics1,2 (Continued) (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Seek/Tune Time6 Powerup Time6 12 RSSI Offset Test Condition Min Typ Max Unit RCLK tolerance = 100 ppm — — 80 ms/channel From powerdown — — 110 ms Input levels of 8 and 60 dBµV at RF Input –3 — 3 dB Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Test Board Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz. 2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise. 4. f = 22.5 kHz. 5. BAF = 300 Hz to 15 kHz, A-weighted. 6. Guaranteed by characterization. 7. VEMF = 1 mV. 8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. 9. f = 75 kHz. 10. At LOUT and ROUT pins. 11. Analog audio output mode. 12. At temperature (25°C). 12 Rev. 0.5 Si473x-B20 Table 8. AM/SW/LW Receiver Characteristics1 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Input Frequency Sensitivity 2,3,4,5, 6 Large Signal Voltage Handling5,7 Power Supply Rejection Ratio Symbol fRF Test Condition Min Typ Max Unit Long Wave (LW) 153 — 279 kHz Medium Wave (AM) 520 — 1710 kHz Short Wave (SW) 2.3 — 21.85 MHz (S+N)/N = 26 dB — 25 35 µV EMF THD < 8% — 300 — mVRMS ΔVDD = 100 mVRMS, 100 Hz — 40 — dB 54 60 67 mVRMS 50 56 — dB — 0.1 0.5 % Long Wave (LW) — 2800 — Medium Wave (AM) 180 — 450 From powerdown — — 110 Audio Output Voltage2,8 Audio S/N 2,3,4,6,8 Audio THD2,4,8 Antenna Inductance Powerup Time µH ms Notes: 1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter. 3. BAF = 300 Hz to 15 kHz, A-weighted. 4. fRF = 1000 kHz, f = 10 kHz. 5. Guaranteed by characterization. 6. Analog audio output mode. 7. See “AN388: Si470X/1X/2X/3X/4X Evaluation Board Test Procedure” for evaluation method. 8. VIN = 5 mVrms. 9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels. Rev. 0.5 13 Si473x-B20 Table 9. WB Receiver Characteristics1 (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6V, TA = 25 °C) Parameter Symbol Test Condition Min Typ Max Unit 162.4 — 162.55 MHz SINAD = 12 dB — 0.9 — µV EMF ±25 kHz — 52 — dB Audio S/N2,3,4,5 Mono — 45 — dB Audio Frequency Response Low6 –3 dB — — 300 Hz Audio Frequency Response High6 –3 dB 3 — — kHz fR Input Frequency Sensitivity2,3 Adjacent Channel Selectivity Notes: 1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 2. FMOD = 1 kHz. 3. f = 3 kHz. 4. VEMF = 1 mV. 5. A-weighted. 6. Guaranteed by characterization Table 10. Reference Clock and Crystal Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40,000 kHz –100 — 100 ppm 1 — 4095 31.130 32.768 34.406 kHz — 32.768 — kHz –50 — 50 ppm — — 3.5 pF Reference Clock RCLK Supported Frequencies1 2 RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Crystal Oscillator Frequency Crystal Frequency Tolerance2 Board Capacitance Notes: 1. The Si473x divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si47xx Programming Guide,” Table 6 for more details. 2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing, SW seek/tune, and WB tune. 14 Rev. 0.5 Si473x-B20 3. Typical AM/FM Application Schematic GPO1 GPO2/INT R1 R2 GPO3/DCLK 2 FMI 3 RFGND FMIP L1 C5 4 AMI 5 GPO3/DCLK DFS U1 Si473x-GM DOUT 15 R3 DOUT Optional: Digital Audio Output 14 13 ROUT/DOUT 12 LOUT/DFS GND VDD RST LOUT ROUT 11 VBATTERY 2.7 to 5.5 V C1 RST 6 7 8 9 10 SEN SCLK SDIO RCLK VIO AM antenna NC GPO2/INT 1 GPO1 NC 20 19 18 17 16 DFS X1 GPO3 SEN SCLK SDIO C2 RCLK VIO 1.5 to 3.6 V RCLK C3 Optional: for crystal oscillator option L2 RFGND AMI T1 C5 Optional: AM air loop antenna Notes: 1. Place C1 close to VDD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 1 and 20 are no connects, leave floating. 4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface and pin 4 connects to the AM antenna interface. 6. RFGND should be locally isolated from GND. 7. Place Si473x as close as possible to antenna jack and keep the FMI and AMI traces as short as possible. Rev. 0.5 15 Si473x-B20 4. Bill of Materials Component(s) Value/Description Supplier C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata L1 Ferrite loop stick, 180–450 µH Jiaxin U1 Si473x AM/FM Radio Tuner Silicon Laboratories Optional Components T1 Transformer, 1–5 turns ratio Jiaxin, UMEC L2 Air loop antenna, 10–20 µH Various Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) Venkel X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson R1 Resistor, 2 k(Optional: for digital audio) Venkel R2 Resistor, 2 k(Optional: for digital audio) Venkel R3 Resistor, 600 (Optional: for digital audio) Venkel C2, C3 16 Rev. 0.5 Si473x-B20 GPO2/INT GPO3/DCLK DFS 1 GPO1 NC NC 5. Pin Descriptions: Si473x-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT GND PAD AMI 4 13 ROUT 6 7 8 9 10 SCLK SDIO RCLK VIO 12 GND SEN RST 5 11 VDD Pin Number(s) Name Description 1, 20 NC No connect. Leave floating. 2 FMI FM/WB/SW RF inputs. FMI should be connected to the antenna trace. 3 RFGND 4 AMI AM/SW/LW RF input. AMI should be connected to the AM antenna. 5 RST Device reset (active low) input. 6 SEN Serial enable input (active low). 7 SCLK Serial clock input. 8 SDIO Serial data input/output. 9 RCLK External reference oscillator input. 10 VIO I/O supply voltage. 11 VDD Supply voltage. May be connected directly to battery. 12, GND PAD GND Ground. Connect to ground plane on PCB. 13 ROUT Right audio line output in analog output mode. 14 LOUT Left audio line output in analog output mode. 15 DOUT Digital output data in digital output mode. 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 RF ground. Connect to ground plane on PCB. Digital frame synchronization input in digital output mode. General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode. General purpose output or interrupt pin. General purpose output. Rev. 0.5 17 Si473x-B20 6. Ordering Guide Part Number* Description Package Type Operating Temperature Si4730-B20-GM AM/FM Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4731-B20-GM AM/FM Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C Si4734-B20-GM AM/FM/SW/LW Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4735-B20-GM AM/FM/SW/LW Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C Si4736-B20-GM AM/FM/WB Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4737-B20-GM AM/FM/WB Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C Si4738-B20-GM FM/WB Broadcast Radio Receiver QFN Pb-free –20 to 85 °C Si4739-B20-GM FM/WB Broadcast Radio Receiver with RDS/RBDS QFN Pb-free –20 to 85 °C *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 18 Rev. 0.5 Si473x-B20 7. Package Outline: Si473x QFN Figure 5 illustrates the package details for the Si473x. Table 11 lists the values for the dimensions shown in the illustration. Figure 5. 20-Pin Quad Flat No-Lead (QFN) Table 11. Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max A 0.50 0.55 0.60 f A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 bbb — — 0.05 ccc — — 0.08 ddd — — 0.10 eee — — 0.10 D D2 3.00 BSC 1.65 e 1.70 1.75 0.50 BSC E E2 Min 3.00 BSC 1.65 1.70 Nom Max 2.53 BSC 1.75 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. Rev. 0.5 19 Si473x-B20 8. PCB Land Pattern: Si473x QFN Figure 6 illustrates the PCB land pattern details for the Si473x family. Table 12 lists the values for the dimensions shown in the illustration. Figure 6. PCB Land Pattern 20 Rev. 0.5 Si473x-B20 Table 12. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF 1.60 1.80 Min Max GE 2.10 — W — 0.34 — e 0.50 BSC X E 2.71 REF Y E2 f GD 1.60 1.80 2.53 BSC 2.10 Millimeters 0.28 0.61 REF ZE — 3.31 ZD — 3.31 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes: Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes: Stencil Design 1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 0.5 21 Si473x-B20 9. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references:  EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide  AN383: Si47xx Antenna, Schematic, Layout, and Design Layout Guidelines  AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure  22 Rev. 0.5 Si473x-B20 NOTES: Rev. 0.5 23 Si473x-B20 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 24 Rev. 0.5