Si4730/31/34/35-D60
B R O A D C A S T A M / F M / S W / LW R A D I O R EC EIVER
Features
Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support (Si4734/35)
(2.3–26.1 MHz)
LW band support (Si4734/35)
(153–279 kHz)
Excellent real-world performance
Integrated VCO
Advanced AM/FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable de-emphasis
Advanced Audio Processing
Seven selectable AM channel filters
AM/FM/SW/LW digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Adjustable soft mute control
RDS/RBDS processor (Si4731/35)
Digital audio out
2-wire and 3-wire control interface
Integrated LDO regulator
Wide range of ferrite loop sticks and
air loop antennas supported
QFN and SSOP packages
RoHS compliant
Ordering Information:
See page 30.
Pin Assignments
NC
GPO1
GPO2/[INT]
GPO3/[DCLK]
DFS
Si473x-D60 (QFN)
20
19
18
17
16
Applications
NC
FM / SW
ANT
Si473x-D 60
RDS
(Si4731/
35)
FM I
LN A
AMI
ADC
ADC
R OU T
DAC
LO U T
C O N TR O L
IN TER FA C E
A FC
RCLK
LD O
DAC
VD
1.62 - 3.6 V
RST
Mux
VA
GN D
G PO /D C LK
SDIO
AGC
D FS
D SP
SEN
2.7~5.5 V (Q FN )
2.0~5.5 V (SSO P )
Mux
LN A
SCLK
R FGN D
D IG ITA L
A U D IO
LO W -IF
AGC
A M / LW
ANT
D OU T
13 ROUT/[DOUT]
RST 5
SEN
Functional Block Diagram
14 LOUT/[DFS]
GND
PAD
AMI 4
6
The Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete
broadcast tuner and receiver function from antenna input to digital audio output.
The device leverages the Skyworks broadcast proven digital low-IF architecture,
enabling a cost-effective, digital audio platform for consumer electronic
applications with high TDMA noise immunity, superior radio performance, and
high fidelity audio power amplification.
15 DOUT
RFGND 3
Description
+
1
FMI 2
12 GND
7
8
9
10
VD
Modules for consumer electronics
Clock radios
Mini HiFi and docking stations
Entertainment systems
RCLK
Table and portable radios
Mini/micro systems
CD/DVD and Blu-ray players
Stereo boom boxes
SDIO
SCLK
11 VA
Si473x-D60(SSOP)
DOUT
1
24
LOUT/[DFS]
DFS
2
23
ROUT/[DOUT]
GPO3/[DCLK]
3
22
DBYP
GPO2/[INT]
4
21
VA
GPO1
5
20
VD
NC
6
19
RCLK
NC
7
18
SDIO
FMI
8
17
SCLK
RFGND
9
16
SEN
NC
10
15
RST
NC
11
14
GND
AMI
12
13
GND
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
7,272,373;
7,272,375;
7,321,324;
7,355,476;
7,426,376;
7,471,940;
7,339,503; 7,339,504.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 10, 2021
Si4730/31/34/35-D60
TA B L E O F C O N T E N T S
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. QFN Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. SSOP Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. QFN/SSOP Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.7. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.11. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.12. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.13. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.14. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.15. RDS/RBDS Processor (Si4731/35 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.16. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.17. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.18. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.19. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.20. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.21. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.22. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.23. 2 V Operation (SSOP Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.24. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1. Si473x-D60-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2. Si473x-D60-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8.1. Si473x-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2. Si473x-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2
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Si4730/31/34/35-D60
9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
9.1. Si473x-D60 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2. Top Marking Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3. Si473x-D60 Top Marking (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.4. Top Marking Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
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1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Analog Supply Voltage
VA
2.72
—
5.5
V
Digital and I/O Supply Voltage
VD
1.62
—
3.6
V
Power Supply Powerup Rise Time
VDDRISE
10
—
—
µs
Interface Power Supply Powerup Rise Time
VIORISE
10
—
—
µs
TA
–20
25
85
C
Ambient Temperature
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VA = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to 2 V at 25 °C. See section “4.23. 2 V Operation (SSOP Only)” for details.
4
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Table 2. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
—
8.2
9.5
—
10.5
13.5
—
18.5
21.5
Unit
FM Mode
VAQFN Supply Current
IFMVA
VDQFN Supply Current
IFMVD
VASSOP Supply Current
IFMVA
VDSSOP Supply Current
IFMVD
—
0.15
0.6
VAQFN Supply Current
IFMVA
—
9.1
10.3
VDQFN Supply Current
IFMVD
—
9.9
12.8
VASSOP Supply Current
IFMVA
—
19.1
21.3
VDSSOP Supply Current
IFMVD
0.1
0.6
—
6.5
7.5
—
8.5
11.0
—
14.5
16.5
Digital Output Mode1
Analog Output Mode2
mA
AM Mode
VAQFN Supply Current
IAMVA
VDQFN Supply Current
IAMVD
VASSOP Supply Current
IAMVA
VDSSOP Supply Current
IAMVD
—
0.15
0.50
VAQFN Supply Current
IAMVA
—
7.5
8.5
VDQFN Supply Current
IAMVD
—
8
10.2
VASSOP Supply Current
IAMVA
—
15.3
17.2
VDSSOP Supply Current
IAMVD
—
0.1
0.4
—
4
15
—
9.5
15
SCLK, RCLK inactive
—
3
10
SCLK, RCLK inactive
—
3
10
Digital Output Mode
Analog Output Mode
mA
Powerdown
VAQFN Powerdown Current
VASSOP Powerdown Current
VDQFN Powerdown Current
VDSSOP Powerdown Current
IAPD
IDPD
µA
µA
High Level Input Voltage3
VIH
0.7 x VD
—
VD + 0.3
V
Voltage3
VIL
–0.3
—
0.3 x VD
V
High Level Input Current3
IIH
VIN = VD = 3.6 V
–10
—
10
µA
Current3
IIL
VIN = 0 V,
VD = 3.6 V
–10
—
10
µA
High Level Output Voltage4
VOH
IOUT = 500 µA
0.8 x VD
—
—
V
Voltage4
VOL
IOUT = –500 µA
—
—
0.2 x VD
V
Low Level Input
Low Level Input
Low Level Output
Notes:
1. Guaranteed by characterization.
2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
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Table 3. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST
tSRST
100
—
—
µs
GPO1, GPO2/INT Hold from RST
tHRST
30
—
—
ns
RST Pulse Release time before VDD/VIO turn off
tRRST
30
—
—
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
5. RST must be held low for at least 100 µs after all voltage supplies have been ramped up.
6. RST needs to be asserted (pulled low) prior to any supply voltage being ramped down.
Figure 1. Reset Timing Parameters for Busmode Select
6
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Table 4. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO Hold
(START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK Hold4,5
tHD:DAT
0
—
900
ns
SCLK input to SDIO Setup
(STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
—
250
ns
—
300
ns
Cb
20 + 0.1 ----------1pF
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
Cb
20 + 0.1 ----------1pF
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si473x-D60 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
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SCLK
70%
SDIO
70%
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
30%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
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Table 5. 3-Wire Control Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLKHold
tHSDIO
10
—
—
ns
SEN Input to SCLKHold
tHSEN
10
—
—
ns
SCLKto SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLKto SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLKSetup
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tR
tF
tHSDIO
tS
SEN
70%
SDIO
70%
tHIGH
tLOW
tHSEN
tS
30%
A7
30%
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
SEN
70%
30%
tHSDIO
tS
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
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Table 6. Digital Audio Interface Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
DCLK Cycle Time
tDCT
26
—
1000
ns
DCLK Pulse Width High
tDCH
10
—
—
ns
DCLK Pulse Width Low
tDCL
10
—
—
ns
DFS Set-up Time to DCLK Rising Edge
tSU:DFS
5
—
—
ns
DFS Hold Time from DCLK Rising Edge
tHD:DFS
5
—
—
ns
tPD:DOUT
0
—
50
ns
DOUT Propagation Delay from DCLK Falling
Edge
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
10
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Table 7. FM Receiver Characteristics1,2
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
76
—
108
MHz
(S+N)/N = 26 dB
—
2.2
3.5
µV EMF
f = 2 kHz,
RDS BLER < 5%
—
10
—
µV EMF
3
4
5
k
4
5
6
pF
100
105
—
dBµV EMF
m = 0.3
40
50
—
dB
Adjacent Channel Selectivity
±200 kHz
35
50
—
dB
Alternate Channel Selectivity
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
72
80
90
mVRMS
—
—
1
dB
Input Frequency
fRF
Sensitivity3,4,5,6
RDS
Test Condition
Sensitivity6,7
LNA Input Resistance7,8
7,8
LNA Input Capacitance
Input IP37,9
AM
Suppression3,4,7,8
Spurious Response Rejection7
3,4,8
Audio Output Voltage
3,8,10
Audio Output L/R Imbalance
Audio Frequency Response Low7
–3 dB
—
—
30
Hz
Audio Frequency Response High7
–3 dB
15
—
—
kHz
35
42
—
dB
55
63
—
dB
—
58
—
dB
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
f = ±400 kHz
—
34
—
dBµV
f = ±4 MHz
—
30
—
dBµV
Audio Stereo Separation
Audio Mono
8,10
S/N3,4,5,8
Audio Stereo S/N4,5,7,8
Audio THD3,8,10
7
De-emphasis Time Constant
3,4,5,6,7,11,12
Blocking Sensitivity
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Skyworks will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Analog audio output mode.
7. Guaranteed by characterization.
8. VEMF = 1 mV.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBuV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.
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Table 7. FM Receiver Characteristics1,2 (Continued)
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
f = ±400 kHz, ±800 kHz
—
40
—
dBµV
f = ±4 MHz, ±8 MHz
—
35
—
dBµV
RL
Single-ended
10
—
—
k
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
Powerup Time7
From powerdown
—
—
110
ms
RSSI Offset12,13
Input levels of 8 and
60 dBµV at RF Input
–3
—
3
dB
Intermod Sensitivity3,4,5,6,7,11,12
Audio Output Load
Resistance7,11,14
Audio Output Load Capacitance7,11,14
Seek/Tune Time7
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Skyworks will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Analog audio output mode.
7. Guaranteed by characterization.
8. VEMF = 1 mV.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBuV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.
12
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Table 8. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
64
—
75.9
MHz
—
3.5
—
µV EMF
3
4
5
k
4
5
6
pF
—
105
—
dBµV EMF
m = 0.3
—
50
—
dB
Adjacent Channel Selectivity
±200 kHz
—
50
—
dB
Alternate Channel Selectivity
±400 kHz
—
70
—
dB
72
80
90
mVRMS
—
—
1
dB
Input Frequency
fRF
Sensitivity
4,5,6,8
LNA Input
Resistance3,7
(S+N)/N = 26 dB
LNA Input Capacitance
Input IP3
Test Condition
3,7
9
AM Suppression3,4,5,7
Audio Output Voltage4,5,7
Audio Output L/R Imbalance4,7,10
3
–3 dB
—
—
30
Hz
3
–3 dB
15
—
—
kHz
Audio Mono S/N4,3,5,7,11
—
63
—
dB
Audio THD4,7,10
—
0.1
—
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
Audio Frequency Response Low
Audio Frequency Response High
De-emphasis Time Constant
Audio Output Load Resistance3,11
RL
Single-ended
10
—
—
k
Audio Output Load Capacitance3,11
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV EMF
–3
—
3
dB
Seek/Tune Time
Powerup Time3
12
RSSI Offset
3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Skyworks will evaluate schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. BAF = 300 Hz to 15 kHz, A-weighted.
7. VEMF = 1 mV.
8. Analog output mode.
9. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled.
10. f = 75 kHz.
11. At LOUT and ROUT pins.
12. At temperature (25 °C).
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Table 9. AM/SW/LW Receiver Characteristics1,2
(VA = 2.7 to 5.5 V, VA = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Input Frequency
Sensitivity
3,4,5
Large Signal Voltage Handling5,6
Power Supply Rejection Ratio5
Symbol
Test Condition
Min
Typ
Max
Unit
fRF
Long Wave (LW)
153
—
279
kHz
Medium Wave (AM)
520
—
1710
kHz
Short Wave (SW)
2.3
—
26.1
MHz
(S+N)/N = 26 dB
—
25
35
µV EMF
THD < 8%
—
300
—
mVRMS
ΔVDD = 100 mVRMS, 100 Hz
—
40
—
dB
Audio Output Voltage3,7
54
60
67
mVRMS
S/N3,4,7
—
60
—
dB
Audio THD3,7
—
0.1
0.5
%
Long Wave (LW)
—
2800
—
µH
Medium Wave (AM)
180
—
450
µH
From powerdown
—
—
110
ms
Audio
Antenna Inductance5,8
Powerup Time
5
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 520 kHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Skyworks will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 30% modulation, 2 kHz channel filter.
4. BAF = 300 Hz to 15 kHz, A-weighted.
5. Guaranteed by characterization.
6. See “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure” for evaluation method.
7. VIN = 5 mVrms.
8. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
14
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Table 10. Reference Clock and Crystal Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
31.130
32.768
40,000
kHz
–100
—
100
ppm
1
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator Frequency
—
32.768
—
kHz
Crystal Frequency Tolerance2
–100
—
100
ppm
Board Capacitance
—
—
3.5
pF
ESR
—
—
50
CL3
7
12
22
pF
CL–single ended3
14
24
44
pF
Reference Clock
RCLK Supported Frequencies1
RCLK Frequency Tolerance2
REFCLK_PRESCALE
REFCLK
Crystal Oscillator
Notes:
1. The Si473x-D60 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing and AM seek/tune in SW
frequencies.
3. Guaranteed by characterization.
Table 11. Thermal Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance*
JA
—
80
—
°C/W
Ambient Temperature
TA
–20
25
85
°C
Junction Temperature
TJ
—
—
92
°C
*Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
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Table 12. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Analog Supply Voltage
VA
–0.5 to 5.8
V
Digital and I/O Supply Voltage
VD
–0.5 to 3.9
V
Input Current3
IIN
10
mA
3
Input Voltage
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
C
Storage Temperature
TSTG
–55 to 150
C
0.4
Vpk
RF Input Level4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si473x-D60 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pins FMI and AMI.
16
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2. Typical Application Schematic
2.1. QFN Typical Application Schematic
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Notes:
1. Place C1 close to VA pin and C4 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Skyworks will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. Place Si473x-D60 as close as possible to antenna and keep the FMI and AMI traces as short as possible.
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Si4730/31/34/35-D60
2.2. SSOP Typical Application Schematic
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