SI5010

Si5010 OC-12/3, STM-4/1 SONET/SDH C LOCK A ND D ATA R ECOVERY I C Features Complete CDR solution includes the following: Supports OC-12/3, STM-4/1 Low power, 293 mW (TYP OC-12) Small footprint: 4x4 mm DSPLL™ eliminates external loop filter components 3.3 V tolerant control inputs Exceeds All SONET/SDH jitter specifications Jitter generation 1.6 mUIrms (typ) Device powerdown Loss-of-lock indicator Single 2.5 V supply Ordering Information: See page 16. Applications SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links SONET/SDH test equipment Optical transceiver modules SONET/SDH regenerators Pin Assignments Si5010 CLKOUT+ CLKOUT– 15 RATESEL GND Description The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data rates. DSPLL® technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance in the application. The Si5010 represents an industry-leading combination of low-jitter, low-power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C). REXT VDD GND REFCLK+ REFCLK– 1 2 3 4 5 NC 20 19 18 17 16 PWRDN/CAL VDD DOUT+ DOUT– VDD GND Pad Connection 6 LOL 7 VDD 8 GND 9 DIN+ 10 DIN– 14 13 12 11 Top View Functional Block Diagram LOL DIN+ DIN– 2 B UF DSPLL TM Phase-Locked Loop Retim er B UF 2 DOUT+ DOUT– PW RDN/CAL Bias 2 B UF 2 CLKOUT+ CLKOUT– REXT RATESEL REFCLK+ REFCLK– Rev. 1.3 12/04 Copyright © 2004 by Silicon Laboratories Si5010 S i5010 2 Rev. 1.3 S i5010 TA B L E O F C O N T E N TS Section Page 1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1. DSPLL® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.4. Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.6. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. Package Outline: Si5010-BM/GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Rev. 1.3 3 S i5010 1. Detailed Block Diagram Retim e DOUT+ DOUT– c DIN+ DIN– Phase Detector A/D DSP n VCO CLK Divider CLKOUT+ c CLKOUT– REFCLK+ REFCLK– Lock Detector LOL RATESEL REXT Bias G eneration Calibration PWRDN/CAL 4 Rev. 1.3 S i5010 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5010 Supply Voltage2 Symbol TA VDD Test Condition Min1 –40 2.375 Typ 25 2.5 Max1 85 2.625 Unit °C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "3. Typical Application Schematic" on page 9. V SIGNAL + Differential VICM, VOCM SIGNAL – I/Os VIS Single Ended Voltage (SIGNAL+) – (SIGNAL–) Differential Voltage Swing VID,VOD Differential Peak-to-Peak Voltage t Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) t C-D DOUT CLKOUT Figure 2. Differential Clock to Data Timing DOUT, CLKOUT tF tR 80% 20% Figure 3. Differential DOUT and CLKOUT Rise/Fall Times Rev. 1.3 5 S i5010 Table 2. DC Characteristics (VDD = 2.5 V ±5%, TA = –40°C to 85°C) Parameter Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Single Ended Input Voltage (DIN, REFCLK) Differential Input Voltage Swing* (DIN, REFCLK) Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Short to GND (DOUT,CLKOUT) Output Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current Symbol IDD Test Condition Min — — — — Typ 117 124 293 310 .80 x VDD — — 100 970 970 VDD – 0.23 100 25 –14.5 — — — — — — — 25 Max 131 138 344 362 — 750 1500 116 1260 1260 — 116 31 — .8 — 10 10 0.4 — — 35 Unit mA PD mW V mVPP mVPP Ω mVPP mVPP V Ω mA mA V V µA µA V V kΩ µA VICM VIS VID RIN VOD VOD VOCM ROUT ISC(–) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN varies with VDD See Figure 1 See Figure 1 Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line Single-ended — 200 200 84 780 780 — 84 — –17.5 — 2.0 — — IO = 2 mA IO = 2 mA VPWRDN ≥ 0.8 V — 2.0 10 15 *Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (VID min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified maximum Input Voltage Range (VIS max). 6 Rev. 1.3 S i5010 Table 3. AC Characteristics (Clock & Data) (VA 2.5 V ±5%, TA = –40 to 85 °C) Parameter Output Clock Rate Output Rise/Fall Time (differential) Clock to Data Delay OC-12 OC-3 Input Return Loss Symbol fCLK tR,tF t(c-d) Test Condition Min .15 Typ — 80 880 4090 20 Max 666 110 930 4140 — Unit MHz ps ps ps dB Figure 3 Figure 2 — 835 4040 100 kHz–1 GHz — Table 4. AC Characteristics (PLL Characteristics) (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Jitter Tolerance (OC-12 Mode)* Symbol JTOL(PP) Test Condition f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz Min 40 4 4 0.4 40 4 4 0.4 — — — — — 1.45 40 40 19.44 –100 450 Typ — — — — — — — — 1.6 25 — — .03 1.5 60 50 — 600 Max — — — — — — — — 3.0 55 500 130 0.1 1.7 150 60 155.52 100 750 Unit UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP mUI mUI kHz kHz dB ms µs % MHz ppm ppm Jitter Tolerance (OC-3 Mode)* JTOL(PP) f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz RMS Jitter Generation* Peak-to-Peak Jitter Generation Jitter Transfer Bandwidth Jitter Transfer Peaking* Acquisition Time * JGEN(rms) JGEN(PP) JBW JP TAQ with no jitter on serial data with no jitter on serial data OC-12 Mode OC-3 Mode f < 2 MHz After falling edge of PWRDN/CAL From the return of valid data Input Reference Clock Duty Cycle Reference Clock Range Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) CDUTY CTOL LOL LOCK 150 300 450 ppm *Note: Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 –1 data pattern. Rev. 1.3 7 S i5010 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) TJCT TSTG Symbol VDD VDIG VDIF Value –0.5 to 2.8 –0.3 to 3.6 –0.3 to (VDD+ 0.3) ±50 –55 to 150 –55 to 150 1 Unit V V V mA °C °C kV Note: Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol ϕJA Test Condition Still Air Value 38 Unit °C/W 8 Rev. 1.3 S i5010 3. Typical Application Schematic LVTTL Control Inputs Loss-of-Lock Indicator 2 RATESEL1-0 PWRDN/CAL LOL High-Speed Serial Input System Reference Clock DIN+ DIN– DOUT+ DOUT– Recovered Data REFCLK+ REFCLK– Si5010 CLKOUT+ CLKOUT– Recovered Clock REXT 10 kΩ (1%) 0.1 µF VDD 2200 pF 20 pF Rev. 1.3 GND VDD 9 S i5010 4. Functional Description The Si5010 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLL® technology to eliminate the noise entry points caused by external PLL filter components. desired data rate. The RATESEL configuration and associated data rates are given in Table 7. Table 7. Data-Rate Configuration RATESEL SONET/SDH 0 1 622.08 Mbps 155.52 Mbps 4.1. DSPLL® The PLL structure (shown in "3. Typical Application Schematic" on page 9) utilizes Silicon Laboratories' DSPLL technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain. 4.4. Reference Clock Detect The Si5010 CDR requires an external reference clock applied to the REFCLK input for normal device operation. When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5010 uses the reference clock to center the VCO operating frequency so that clock and data can be recovered from the input data stream. The VCO operates at an integer multiple of the REFCLK frequency. (See “Lock Detect” section.) The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The REFCLK frequency should be 19.44 MHz, 77.76 MHz, or 155.52 MHz with a frequency accuracy of ±100 ppm. 4.2. PLL Self-Calibration The Si5020 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on power-up. A self-calibration can be initiated by forcing a high-to-low transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 µs before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories application note “AN42: Controlling DSPLL Self-Calibration for the Si5020/5018/5010 CDR Devices and Si531x Clock Multiplier/Regenerator Devices”. 4.5. Lock Detect The Si5010 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out-of-lock, and the loss-of-lock (LOL) pin is asserted high. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock may drift over a ±600 ppm range relative to the applied reference clock, and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, under the condition where data is removed from the inputs, there is the possibility that the PLL will not drift enough to render an out-of-lock condition. If REFCLK is removed, the LOL output alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the frequency lock status of the PLL is unknown. Note: LOL is not asserted during PWRDN/CAL. 4.3. Multi-Rate Operation The Si5010 supports clock and data recovery for OC-12/3 and STM-4/1 data streams. Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the 10 Rev. 1.3 S i5010 4.6. PLL Performance The PLL implementation used in the Si5010 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. 4.6.1. Jitter Tolerance Jitter Transfer 0.1 dB Acceptable Range 20 dB/Decade Slope The Si5010’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 4. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. Sinusoidal Input Jitter (UI p-p) Fc Frequency Slope = 20 dB/Decade SONET Data Rate OC-12 OC-3 Fc (kHz) 500 130 15 1.5 0.15 f0 f1 f2 Frequency Figure 5. Jitter Transfer Specification 4.7. Powerdown f3 ft SONET Data Rate OC-12 OC-3 F0 (Hz) 10 10 F1 (Hz) 30 30 F2 (Hz) 300 300 F3 (kHz) 25 6.5 Ft (kHz) 250 65 Figure 4. Jitter Tolerance Specification 4.6.2. Jitter Transfer The Si5010 provides a powerdown pin, PWRDN/CAL, that disables the device. When the PWRDN/CAL pin is driven high, the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. When PWRDN/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL®, and will begin to lock to the data stream. Note: LOL is not asserted when the device is in the powerdown state. The Si5010 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 5). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 4. 4.6.3. Jitter Generation 4.8. Device Grounding The Si5010 uses the GND pad on the bottom of the 20-pin QFN package for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. 4.9. Bias Generation Circuitry The Si5010 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. The Si5010 meets all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5010 typically generates less than 1.6 mUIrms of jitter when presented with jitter-free input data. Rev. 1.3 11 S i5010 4.10. Differential Input Circuitry The Si5010 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6. Differential Driver DIN+, REFCLK+ Si5010 VDD 2.5 k¬ 0.1 µF Zo = 50 ¬ 10 k¬ 0.1 µF Zo = 50 ¬ DIN–, REFCLK– 2.5 k¬ 102 ¬ 10 k¬ GND Figure 6. Input Termination for DIN and REFCLK (AC Coupled) Si5010 Clock source 0.1 µF Zo = 50 Ω REFCLK + 10 kΩ 100 Ω REFCLK – 10 kΩ 0.1 µF 2.5 kΩ VDD 2.5 kΩ 102 Ω GND Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled) Si5010 Clock source 0.1 µF Zo = 50 Ω DIN + 10 kΩ 100 Ω DIN – 10 kΩ 0.1 µF 2.5 kΩ VDD 2.5 kΩ 102 Ω GND Figure 8. Single-Ended Input Termination for DIN (AC Coupled) 12 Rev. 1.3 S i5010 4.11. Differential Output Circuitry The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. Si5010 VDD 100 Ξ 50 Ξ VDD DOUT+, CLKOUT+ 0.1ΞF Zo = 50 Ξ DOUT–, CLKOUT– 0.1ΞF Zo = 50 Ξ 100 Ξ VDD 50 Ξ VDD Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled) Rev. 1.3 13 S i5010 5. Pin Descriptions: Si5010 CLKOUT+ CLKOUT– 15 RATESEL 20 19 18 17 16 REXT VDD GND REFCLK+ REFCLK– 1 2 3 4 5 6 LOL 7 VDD 8 GND 9 DIN+ 10 DIN– PWRDN/CAL VDD DOUT+ DOUT– VDD GND NC GND Pad Connection 14 13 12 11 Top View Figure 10. Si5010 Pin Configuration Table 8. Si5010 Pin Descriptions Pin # Pin Name I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. 1 REXT 2, 7, 11, 14 3, 8, 18, and GND Pad VDD GND 2.5 V GND Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground. Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. Loss-of-Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 7. Differential Data Input. Clock and data are recovered from the differential signal present on these pins. 4 5 REFCLK+ REFCLK– I See Table 2 6 LOL O LVTTL 9 10 DIN+ DIN– I See Table 2 14 Rev. 1.3 S i5010 Table 8. Si5010 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. Powerdown. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a high-to-low transition on this pin. (See "4.2. PLL Self-Calibration" on page 10.) Note: This input has a weak internal pulldown. 12 13 DOUT– DOUT+ O CML 15 PWRDN/CAL I LVTTL 16 17 CLKOUT– CLKOUT+ O CML Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK. Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. Note: This input has a weak internal pulldown. 19 RATESEL I LVTTL 20 NC No Connect. This pin should be tied to ground. Rev. 1.3 15 S i5010 6. Ordering Guide Part Number Package Temperature Lead Finish Si5010-BM Si5010-GM 20-pin QFN 20-pin QFN –40 to 85 °C –40 to 85 °C 85/15 Pb/Sn Matte Sn (Pb-free) 7. Top Mark Silicon Labs Part Number Die Revision (R) Part Designator (Z) Si5010-BM Si5010-GM B B B F 16 Rev. 1.3 S i5010 8. Package Outline: Si5010-BM/GM Figure 11 illustrates the package details for the Si5010-BM/GM. Table 9 lists the values for the dimensions shown in the illustration. D D1 PIN1 ID 0.50 DIA. 20 A A1 A2 A3 b b 1 2 3 θ e e D2 L 20 1 2 3 E1 E E2 Top View Side View Bottom View Figure 11. 20-pin Quad Flat No-Lead (QFN) Table 9. Package Dimensions Symbol Min Millimeters Nom Max Symbol Min Millimeters Nom Max A A1 A2 A3 b D, E — 0.00 — 0.18 0.85 0.01 0.65 0.20 REF. 0.23 4.00 BSC 0.90 0.05 0.70 0.30 D1, E1 D2, E2 e θ L — 0.50 1.95 3.75 BSC 2.10 0.50 BSC — 0.60 12° 0.75 2.25 Notes: 1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994 2. Package warpage MAX 0.05 mm. 3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP. 4. The package weight is approximately 42 mg. 5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28 minimum/54 typical. 6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification. Rev. 1.3 17 S i5010 9. 4x4 mm 20L QFN Recommended PCB Layout See Note 8 Gnd Pin See Note 9 Gnd Pin Symbol A D e G R X Y Z Parameter Min Pad Row/Column Width/Length Thermal Pad Width/Height Pad Pitch Pad Row/Column Separation Pad Radius Pad Width Pad Length Pad Row/Column Extents 2.23 2.03 — 2.43 — 0.23 — 4.26 Gnd Pin Dimensions Nom 2.25 2.08 0.50 BSC 2.46 0.12 REF 0.25 0.94 REF 4.28 Max 2.28 2.13 — 2.48 — 0.28 — 4.31 Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad. 3. The center thermal pad is to be Solder Mask Defined (SMD). 4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent solder from flowing into the via hole. 5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a 0.65 mm pitch, should be used for the center thermal pad. 6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate paste release. 7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended. 8. Do not place any signal or power plane vias in these “keep out” regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane. 18 Rev. 1.3 S i5010 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Added "7. Top Mark" on page 16. Updated “8. Package Outline: Si5010-BM” on page 17. Added "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. Revision 1.1 to Revision 1.2 Made minor note corrections to "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. Revision 1.2 to Revision 1.3 Global change: MLP to QFN. Updated "6. Ordering Guide" on page 16. Updated "7. Top Mark" on page 16. Updated "8. Package Outline: Si5010-BM/GM" on page 17. Updated "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. Rev. 1.3 19 S i5010 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 20 Rev. 1.3