SI5017-D-GM

Si5017 OC-48/STM-16 SONET/SDH CDR IC WITH L IMITING A MPLIFIER Features High-speed clock and data recovery device with integrated limiting amplifier: ! ! ! ! ! Supports OC-48/STM-16 and 2.7 Gbps FEC DSPLL™ technology Low power—528 mW (typ) Small footprint: 5 x 5 mm Bit-error-rate alarm ! Jitter generation 3.0 mUIrms (typ) ! Loss-of-signal level alarm ! Data slicing level control ! 10 mVPP differential sensitivity ! 3.3 V supply ! Reference and reference-less Ordering Information: See page 22. operation supported Applications Pin Assignments SONET/SDH test equipment Optical transceiver modules ! SONET/SDH regenerators CLKOUT– CLKOUT+ Description CLKDSBL NC Si5017 VDD ! SONET/SDH/ATM routers Add/drop multiplexers ! Digital cross connects ! Board level serial links BER_LVL ! ! BER_ALM ! 28 27 26 25 24 23 22 1 21 VDD VDD 2 20 REXT LOS_LVL 3 SLICE_LVL 4 REFCLK+ 5 REFCLK– 6 LOL 7 19 RESET/CAL GND Pad 18 VDD 17 DOUT+ 16 DOUT– VDD DIN– DSQLCH DIN+ 10 11 12 13 14 VDD 9 LTR 15 TDI 8 LOS The Si5017 is a fully-integrated, high-performance limiting amplifier (LA) and clock and data recovery (CDR) IC for high-speed serial communication systems. It derives timing information and data from a serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). Use of an external reference clock is optional. Silicon Laboratories® DSPLL™ technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5017 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (–40 to 85 °C). VDD Functional Block Diagram LOS_LVL DSQLCH Signal Detect LOS Retimer DIN+ DIN– 2 Limiting Amp BUF 2 DOUT+ DOUT– DSPLL BUF BER Monitor 2 CLKOUT+ CLKOUT– CLK_DSBL REFCLK+ REFCLK– (Optional) 2 Lock Detection Bias Gen. Reset/ Calibration BER_ALM REXT SLICE_LVL Rev. 1.2 12/03 LTR BER_LVL RESET/CAL LOL Copyright © 2003 by Silicon Laboratories Si5017-DS12 Si5017 2 Rev. 1.2 Si5017 TA B L E O F C O N T E N TS Section Page Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.2 5 11 12 12 12 12 12 13 13 13 14 14 14 15 15 15 15 15 15 15 18 19 22 23 24 26 3 Si5017 Detailed Block Diagram LOS LOS_LVL BER_LVL LTR BER_ALM DSQLCH BER Monitor Signal Detect Retime DOUT+ DOUT– DIN+ Limiting Amp Phase Detector A/D DSP VCO CLK Dividers CLKOUT+ CLKOUT– DIN+ n SLICE_LVL Lock Detection REFCLK± (optional) REXT 4 CLKDSBL Slicing Control LOL Bias Generation Calibration Rev. 1.2 RESET/CAL Si5017 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature Si5017 Supply Voltage2 Test Condition Min1 Typ Max1 Unit TA –40 25 85 °C VDD 3.135 3.3 3.465 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5017 specifications are guaranteed when using the recommended application circuit (including component tolerance) of the "Typical Application Schematic" on page 11. V SIG NAL+ SIG NAL– V IS t A. Operation with Single-Ended Inputs V SIGNAL+ 0.5 V ID SIGNAL– (SIGNAL+) – (SIG NAL–) V ID t B. O peration with Differential Inputs and Outputs Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) Rev. 1.2 5 Si5017 t Cf-D t C r-D DOUT CLK OUT Figure 2. Clock to Data Timing 80% DOUT, CLKOUT 20% tF tR Figure 3. DOUT and CLKOUT Rise/Fall Times taq RESET/Cal LOL DATAIN LOL taq Figure 4. PLL Acquisition Time DATAIN LOS Threshold Level LOS tLOS Figure 5. LOS Response Time 6 Rev. 1.2 Si5017 Table 2. DC Characteristics (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition 1 Supply Current FEC (2.7 Gbps) OC-48 IDD Power Dissipation FEC (2.7 Gbps) OC-48 PD Common Mode Input Voltage (DIN)2 Min Typ Max Unit — — 163 160 174 170 mA — — 538 528 603 554 mW VICM See Figure 11 1.40 1.50 1.60 V VICM See Figure 10 1.90 2.10 2.30 V VIS See Figure 1A 10 — 500 mV VID See Figure 1B 10 — 1000 mV VIS See Figure 1A 200 — 750 mV REFCLK Differential Input Voltage Swing2 VID See Figure 1B 200 — 1500 mV Input Impedance (DIN) RIN Line-to-Line 84 100 116 Ω Differential Output Voltage Swing (DOUT) VOD 100 Ω Load Line-to-Line 700 800 900 mVPP Differential Output Voltage Swing (CLKOUT) VOD 100 Ω Load Line-to-Line 700 800 900 mVPP Output Common Mode Voltage (DOUT) VOCM 100 Ω Load Line-to-Line 1.85 1.95 2.00 V Output Common Mode Voltage (CLKOUT) VOCM 100 Ω Load Line-to-Line 1.75 1.80 1.90 V Output Impedance (DOUT,CLKOUT) ROUT Single-ended 84 100 116 Ω Common Mode Input Voltage (REFCLK)2 DIN Single-ended Input Voltage Swing 2 DIN Differential Input Voltage Swing2 REFCLK Single-ended Input Voltage Swing 2 Input Voltage Low (LVTTL Inputs) VIL — — .8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 10 µA Input High Current (LVTTL Inputs) IIH — — 10 µA Input Impedance (LVTTL Inputs) RIN 10 — — kΩ LOS_LVL, BER_LVL, SLICE_LVL Input Impedance RIN 75 100 125 kΩ Output Voltage Low (LVTTL Outputs) VOL IO = 2 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 2 mA 2.0 — — V Notes: 1. No load on LVTTL outputs. 2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac coupled to ground. Rev. 1.2 7 Si5017 Table 3. AC Characteristics (Clock and Data) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Output Clock Rate Symbol Test Condition fCLK Min Typ Max Unit 2.4 — 2.7 GHz Output Clock Rise Time tR Figure 3 — 70 90 ps Output Clock Fall Time tF Figure 3 — 70 90 ps 48 50 52 % of UI Output Clock Duty Cycle Output Data Rise Time tR Figure 3 — 80 110 ps Output Data Fall Time tF Figure 3 — 80 110 ps Clock to Data Delay FEC (2.7 Gbps) OC-48 tCr-D Figure 2 180 200 215 230 250 260 ps Clock to Data Delay FEC (2.7 Gbps) OC-48 tCf-D –60 –60 –30 –30 0 0 ps 100 kHz–1.5 GHz 1.5 GHz–4.0 GHz –15 –10 — — — — dB dB SLICE_LVL = 750 mV to 2.25 V –15 — 15 mV SLICE_LVL = 750 mV to 2.25 V –500 — 500 µV Input Return Loss Slicing Level Offset1 (relative to the internally set input common mode voltage) VSLICE Slicing Level Accuracy Figure 2 Loss-of-Signal Range2 (peak-to-peak differential) VLOS LOS_LVL = 1.50 to 2.50 V 0 — 40 mV Loss-of-Signal Response Time tLOS Figure 5 8 20 25 µs Notes: 1. Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows: VSLICE = (SLICE_LVL – 1.50)/50. 2. Adjustment voltage is calculated as follows: VLOS = (LOS_LVL – 1.50)/25. 8 Rev. 1.2 Si5017 Table 4. AC Characteristics (PLL Characteristics) (VDD =3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance (OC-48)* JTOL(PP) f = 600 Hz 40 — — UIPP f = 6000 Hz 4 — — UIPP f = 100 kHz 4 — — UIPP f = 1 MHz 0.5 — — UIPP JGEN(rms) with no jitter on serial data — 3.0 5.0 mUI JGEN(PP) with no jitter on serial data — 25 55 mUI JBW OC-48 — — 2.0 MHz — 0.03 0.1 dB After falling edge of RESET/CAL — 1.6 1.9 ms From the return of valid data 20 100 500 µs After falling edge of RESET/CAL — 2.0 4.5 ms From the return of valid data 1.5 2.5 5.5 ms 19.44 — 168.75 MHz –100 — 100 ppm Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) 450 600 750 ppm Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) 150 300 450 ppm RMS Jitter Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth* Jitter Transfer Peaking * Acquisition Time (Reference clock applied) Acquisition Time (Reference-less operation) JP TAQ TAQ Reference Clock Range Input Reference Clock Frequency Tolerance CTOL *Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern. Rev. 1.2 9 Si5017 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.5 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 °C Storage Temperature Range TSTG –55 to 150 °C 1 kV ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 10 Symbol Test Condition Value Unit ϕJA Still Air 38 °C/W Rev. 1.2 Si5017 Typical Application Schematic LOS LOL BER_ALM DSQLCH RESET/CAL DOUT+ DIN– DOUT– Si5017 REFCLK+ CLKOUT+ VDD REXT Recovered Data Recovered Clock GND CLKOUT– SLICE_LVL REFCLK– BER_LVL System Reference Clock (Optional) DIN+ LOS_LVL High-Speed Serial Input CLKDSBL LTR LVTTL BER Alarm Loss-of-Signal Control Inputs Indicator Indicator Loss-of-Lock Indicator 100 pF x 4 10 kΩ (1%) VDD 0.1 µF Loss-of-Signal Data Slice Level Set Level Set Bit Error Rate Level Set Rev. 1.2 11 Si5017 Functional Description The Si5017 integrates a high-speed limiting amplifier with a CDR unit that operates up to 2.7 Gbps. No external reference clock is required for clock and data recovery. The limiting amplifier magnifies very low-level input data signals so accurate clock and data recovery can be performed. The CDR uses Silicon Laboratories® DSPLL technology to recover a clock synchronous to the input data stream. The recovered clock retimes the incoming data, and both are output synchronously via current-mode logic (CML) drivers. Silicon Laboratories’ DSPLL technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (PLL) implementations. The limiting amplifier includes a control input for adjusting the data slicing level and provides a loss-ofsignal level alarm output. The CDR includes a bit-errorrate performance monitor which signals a high bit-errorrate condition (associated with excessive incoming jitter) relative to an externally adjustable bit-error-rate threshold. The optional reference clock minimizes the CDR acquisition time and provides a stable reference for maintaining the output clock when locking to reference is desired. Limiting Amplifier The limiting amplifier accepts the low-level signal output from a transimpedance amplifier (TIA). The low-level signal is amplified to a usable level for the CDR unit. The minimum input swing requirement is specified in Table 2. Larger input amplitudes (up to the maximum input swing specified in Table 2) are accommodated without degradation of performance. The limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage. DSPLL™ The Si5017 PLL structure (shown in the "Detailed Block Diagram" on page 4) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). This technology enables CDR with far less jitter than is generated using 12 traditional methods, and it eliminates performance degradation caused by external component aging. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources and making SONET/SDH jitter compliance easier to attain in the application. Operation Without an External Reference The Si5017 can perform clock and data recovery without an external reference clock. Tying the REFCLK+ input to VDD and the REFCLK– input to GND configures the device to operate without an external reference clock. Clock recovery is achieved by monitoring the timing quality of the incoming data relative to the VCO frequency. Lock is maintained by continuously monitoring the incoming data timing quality and adjusting the VCO accordingly. Details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below. Note: Without an external reference the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a reference is applied. Operation With an External Reference The Si5017 can also perform clock and data recovery with an external reference. The device’s optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5017 uses the reference clock to center the VCO output frequency so that clock and data are recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.5 and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 7. Rev. 1.2 Si5017 19.44 MHz 20.83 MHz 128 of LTR forces the DSPLL to lock CLKOUT to the provided reference. If no external reference clock is used, LTR forces the DSPLL to hold the digital frequency control input to the VCO at the last value. This produces a stable output clock as long as supply and temperature are constant. 77.76 MHz 83.31 MHz 32 Loss-of-Signal 155.52 MHz 166.63 MHz 16 The Si5017 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 and is set by applying a voltage on the LOS_LVL pin. The graph in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold. The LOS output is asserted when the input signal drops below the programmed peak-topeak value. If desired, the LOS function may be disabled by grounding LOS_LVL or by adjusting LOS_LVL to be less than 1 V. Lock Detect The Si5017 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The operation of the lock-detector depends on the reference clock option used. When an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 9, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (CLKOUT) drifts over a ±600 ppm range relative to the applied reference clock and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, there is the possibility that the PLL will not drift enough to render an out-of-lock condition, even if the data is removed from inputs. 40 mV In applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (LTR) input can be used to force the PLL to lock to the externally supplied reference. In the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. During reacquisition, CLKOUT may vary by approximately ±10% from the nominal data rate. 30 mV 15 mV LOS Undefined OC-48 with Ratio of VCO 15/14 FEC to REFCLK LOS Disabled SONET/SDH LOS Threshold (mVPP) Table 7. Typical REFCLK Frequencies 40 mV/V 0 mV 0V 1.00 V 1.50 V 2.5 V LOS_LVL (V) Figure 6. LOS_LVL Mapping R1 3 LOS_LVL Set LOS Level R2 10k Si5017 CDR Lock-to-Reference The LTR input is used to force a stable output clock when an alarm condition, like LOS, exists. In typical applications, the LOS output is tied to the LTR input to force a stable output clock when the input data signal is lost. When LTR is asserted, the DSPLL is prevented from acquiring the data signal present on DIN. The operation of the LTR control input depends on which reference clocking mode is used. 2.25 V 1.875 V LOS 9 LOS Alarm Figure 7. LOS Signal Hysteresis When an external reference clock is present, assertion Rev. 1.2 13 Si5017 In many applications it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator such as LOS, since a marginal data input signal could cause intermittent toggling, leading to false alarm status. When it is anticipated that very low-level DIN signals will be encountered, the introduction of an adequate amount of LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of LOS signal hysteresis for the Si5017 CDR. The value of R1 may be chosen to provide a range of hysteresis from 3 to 8 dB where a nominal value of 800 Ω adjusts the hysteresis level to approximately 6 dB. Use a value of 500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of hysteresis, respectively. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/ LOSA). PLL Performance The PLL implementation used in the Si5017 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. Jitter Tolerance The Si5017’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. Sinusoidal Input Jitter (UIPP) 1.5 Bit-Error-Rate (BER) Detection 0.15 The Si5017 uses a proprietary Silicon Laboratories® algorithm to generate a bit-error-rate (BER) alarm on the BER_ALM pin if the observed BER is greater than a user programmable threshold. Bit error detection relies on the input data edge timing; edges occurring outside of the expected event window are counted as bit errors. The BER threshold is programmed by applying a voltage to the BER_LVL pin between 500 mV and 2.25 V corresponding to a BER of approximately 10–10 and 10–6, respectively. The voltage present on BER_LVL maps to the BER as follows: log10(BER) = (4 x BER_LVL) –13. (BER_LVL is in volts; BER is in bits per second.) Data Slicing Level The Si5017 provides the ability to externally adjust the slicing level for applications that require bit-error-rate (BER) optimization. Adjustments in slicing level of ±15 mV (relative to the internally set input common mode voltage) are supported. The slicing level is set by applying a voltage between 0.75 and 2.25 V to the SLICE_LVL input. The voltage present on SLICE_LVL maps to the slicing level as follows: f0 SONET Data Rate OC-48 F0 (Hz) 10 f1 f2 f3 Frequency F1 (Hz) 600 ft F2 F3 Ft (kHz) (kHz) (kHz) 6 100 1000 Figure 8. Jitter Tolerance Specification Jitter Transfer The Si5017 exceeds all relevant Bellcore/ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency. These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 9. ( V SLICE_LVL – 1.5 V ) V SLICE = ------------------------------------------------------50 where VSLICE is the slicing level, and VSLICE_LVL is the voltage applied to the SLICE_LVL pin. When SLICE_LVL is driven below 500 mV, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal. 14 Slope = 20 dB/Decade 15 Rev. 1.2 Si5017 DOUT+ signal is held low and the DOUT– signal is held high. This pin can be is used to squelch corrupt data during LOS and LOL situations. Care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held through ac coupling capacitors. Jitter Transfer 0.1 dB 20 dB/Decade Slope Device Grounding The Si5017 uses the GND pad on the bottom of the 28pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location. Acceptable Range Fc Frequency SONET Data Rate OC-48 Bias Generation Circuitry The Si5017 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. Fc (kHz) 2000 Figure 9. Jitter Transfer Specification Jitter Generation The Si5017 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5017 typically generates less than 3.0 mUIrms of jitter when presented with jitter-free input data. RESET/DSPLL Calibration The Si5017 achieves optimal jitter performance by automatically calibrating the loop gain parameters within the DSPLL on powerup. Calibration may also be initiated by a high-to-low transition on the RESET/CAL pin. The RESET/CAL pin must be held high for at least 1 µs. When RESET/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and begins to lock to the incoming data stream. For a valid reset to occur when using Reference mode, a proper, external reference clock frequency must be applied as specified in Table 7. Clock Disable The Si5017 provides a clock disable pin (CLK_DSBL) that is used to disable the recovered clock output (CLKOUT). When the CLK_DSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to VDD through 100 Ω on-chip resistors. Voltage Regulator The Si5017 operates from a 3.3 V external supply voltage. Internally the device operates from a 2.5 V supply. The Si5017 regulates 2.5 V internally down from the external 3.3 V supply. In addition to supporting 3.3 V systems, the on-chip linear regulator offers better power supply noise rejection versus a direct 2.5 V supply. Differential Input Circuitry The Si5017 provides differential inputs for both the highspeed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in Table 2 on page 7 to ensure a BER of at least 10–12. The REFCLK input differential peak-to-peak voltage requirement is also specified in Table 2. Data Squelch The Si5017 provides a data squelching pin (DSQLCH) that is used to set the recovered data output (DOUT) to binary zero. When the DSQLCH pin is asserted, the Rev. 1.2 15 Si5017 Si5017 Clock source 2.5 V (±5%) 2.5 kΩ 0.1 µF Zo = 50 Ω RFCLK + 10 kΩ 100 Ω 0.1 µF Zo = 50 Ω 2.5 kΩ RFCLK – 10 kΩ GND Figure 10. Input Termination for REFCLK (ac coupled) Si5017 TIA 2.5 V (±5%) 0.1 µF Zo = 50 Ω DIN+ 50 Ω 0.1 µF 5 kΩ 50 Ω Zo = 50 Ω 7.5 kΩ DIN– GND Figure 11. Input Termination for DIN (ac coupled) 16 Rev. 1.2 Si5017 Si5017 Clock source 2.5 V (±5%) 2.5 kΩ 0.1 µF Zo = 50 Ω RFCLK + 10 kΩ 2.5 kΩ 50 Ω RFCLK – 10 kΩ 0.1 µF GND Figure 12. Single-Ended Input Termination for REFCLK (ac coupled) Si5017 2.5 V (±5%) Signal source 0.1 µF Zo = 50 Ω DIN+ 50 Ω 5 kΩ 100 Ω 50 Ω 7.5 kΩ DIN– 0.1 µF GND Figure 13. Single-Ended Input Termination for DIN (ac coupled) Rev. 1.2 17 Si5017 Differential Output Circuitry The Si5017 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7. Si5017 VDD 50 Ω 2.5 V (±5%) 100 Ω DOUT+, CLKOUT+ 0.1 µF Zo = 50 Ω DOUT–, CLKOUT– 0.1 µF Zo = 50 Ω 100 Ω 50 Ω 2.5 V (±5%) VDD Figure 14. Output Termination for DOUT and CLKOUT (ac coupled) 18 Rev. 1.2 Si5017 CLKOUT– CLKOUT+ CLKDSBL VDD BER_LVL BER_ALM NC Pin Descriptions: Si5017 28 27 26 25 24 23 22 VDD 1 21 VDD VDD 2 20 REXT LOS_LVL 3 SLICE_LVL 4 REFCLK+ 5 REFCLK– 6 LOL 7 19 RESET/CAL GND Pad 18 VDD 17 DOUT+ 16 DOUT– VDD DSQLCH DIN– LTR DIN+ 10 11 12 13 14 VDD 9 LOS 15 TDI 8 Figure 15. Si5017 Pin Configuration Table 8. Si5017 Pin Descriptions Pin # Pin Name I/O Signal Level 1,2,11,14,18, 21,25 VDD 3 LOS_LVL I LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 13 shows the input setting to output threshold mapping. LOS is disabled when the voltage applied is less than 1 V. 4 SLICE_LVL I Slicing Level Control. The slicing threshold level is set by applying a voltage to this pin as described in the Slicing Level section of the data sheet. If this pin is tied to GND, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on DIN. Slicing level becomes active when the voltage applied to the pin is greater than 500 mV. 5 6 REFCLK+ REFCLK– I 3.3 V See Table 2 Rev. 1.2 Description Supply Voltage. Nominally 3.3 V. Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK– to GND to operate without an external reference clock. See Table 7 on page 13 for typical reference clock frequencies. 19 Si5017 Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 7 LOL O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9. If no external reference is supplied, this signal will be active when the internal PLL is no longer locked to the incoming data. 8 LTR I LVTTL Lock-to-Reference. When this pin is low, the DSPLL disregards the data inputs. If an external reference is supplied, the output clock locks to the supplied reference. If no external reference is used, the DSPLL locks the control loop until LTR is released. 9 LOS O LVTTL Loss-of-Signal. This output pin is driven low when the input signal is below the threshold set via LOS_LVL. (LOS operation is guaranteed only when ac coupling is used on the DIN inputs.) 10 DSQLCH LVTTL Data Squelch. When driven high, this pin forces the data present on DOUT+ to zero and DOUT– to one. For normal operation, this pin should be low. DSQLCH may be used during LOS/LOL conditions to prevent random data from being presented to the system. 12 13 DIN+ DIN– 15 GND 16 17 DOUT– DOUT+ 19 RESET/CAL Note: This input has a weak internal pullup. Note: This input has a weak internal pulldown. I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. AC coupling is recommended. GND Production Test Input. This pin is used during production testing and must be tied to GND for normal operation. O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. I LVTTL Reset/Calibrate. Driving this input high for at least 1 µs will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration. For normal operation, drive this pin low. Note: This input has a weak internal pulldown. 20 Rev. 1.2 Si5017 Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 20 REXT 22 23 CLKOUT– CLKOUT+ O CML Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered. 24 CLKDSBL I LVTTL Clock Disable. When this input is high, the CLKOUT output drivers are disabled. For normal operation, this pin should be low. External Bias Resistor. This resistor is used to establish internal bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. Note: This input has a weak internal pulldown. 26 BER_LVL I 27 BER_ALM O 28 NC GND Pad GND Bit Error Rate Level Control. The BER threshold level is set by applying a voltage to this pin. When the BER exceeds the programmed threshold, BER_ALM is driven low. If this pin is tied to GND, BER_ALM is disabled. LVTTL Bit Error Rate Alarm. This pin will be driven low to indicate that the BER threshold set by BER_LVL has been exceeded. The alarm will clear after the BER rate has improved by approximately a factor of 2. No Connect. Leave this pin disconnected. GND Rev. 1.2 Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 28-lead MLP (see Figure 16 on page 23) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance. 21 Si5017 Ordering Guide 22 Part Number Package Voltage Temperature Si5017-BM 28-Lead MLP 3.3 –40 to 85 °C Rev. 1.2 Si5017 Package Outline Figure 16 illustrates the package details for the Si5017. Table 9 lists the values for the dimensions shown in the illustration. 2X 0.10 C A A D D/2 0.05 C b A D1 D1/2 M C A B D2 2X N 0.10 C B 1 2 3 0.10 A1 E1/2 N 1 2 3 E/2 E1 E (Ne–1) Xe REF. E2 L B TOP VIEW θ C SEATING PLANE e (Nd–1) Xe REF. C CL C b A1 BOTTOM VIEW SECTION "C–C" e SCALE: NONE Approximate device weight is 62.2 mg. Figure 16. 28-Lead Micro Leaded Package (MLP) Table 9. Package Diagram Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC E 5.00 BSC E1 4.75 BSC E2 2.95 3.10 N 28 Nd 7 Ne 7 e 0.50 BSC L 0.50 0.60 θ Rev. 1.2 Max 0.90 0.05 0.30 3.25 0.75 12° 23 Si5017 Document Change List ! Revision 0.1 to Revision 1.0 ! Added Figure 4, “PLL Acquisition Time,” on page 6. ! Table 2 on page 7 " " " " " " ! Added FEC (2.7 GHz) Supply Current Updated values: Supply Current Added FEC (2.7 GHz) Power Dissipation Updated values: Power Dissipation Updated values: Common Mode Input Voltage (REFCLK) Updated values: Output Common Mode Voltage Table 3 on page 8 " " " " ! Updated Figure 16, “28-Lead Micro Leaded Package (MLP),” on page 23. ! Updated Table 9, “Package Diagram Dimensions,” on page 23. Added separate Output Clock Rise Time Added separate Output Clock Fall Time Updated values: Output Clock Rise Time Updated values: Output Clock Fall Time Table 4 on page 9 " " " " " Updated values: Jitter Tolerance (OC-48) for f = 1 MHz Updated values: Acquisition Time (reference clock applied) Updated values: Acquisition Time (reference-less operation) Updated values: Freq Difference at which Receive PLL goes out of Lock Updated values: Freq Difference at which Receive PLL goes into Lock ! Removed “Hysteresis Dependency” Figure. Added Figure 7, “LOS Signal Hysteresis,” on page 13. ! Corrected error: Table 8 on page 19—changed description for LOS_LVL from “LOS is disabled when the voltage applied is less than 500 mV” to “LOS is disabled when the voltage applied is less than 1.0 V.” ! Revision 1.0 to Revision 1.1 ! Corrected “Revision 0.1 to Revision 1.0” Change List. Revision 1.1 to Revision 1.2 ! Added Figure 5, “LOS Response Time,” on page 6. ! Updated Table 2 on page 7 Added “Output Common Mode Voltage (DOUT)” with updated values. " Added “Output Common Mode Voltage (CLKOUT)” with updated values. " ! Table 3 on page 8. " " ! Updated Table 8 on page 19 " 24 Added “Output Clock Duty Cycle” Added “Loss-of-Signal Response Time” Changed “clock input” to “DIN inputs” for Loss-of-Signal. Rev. 1.2 " " Changed dimension A. Changed dimension E2. Si5017 Notes: Rev. 1.2 25 Si5017 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. 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