SI5017-EVB

Si 5 0 1 7 - EVB EVALUATION BOARD FOR Si5017 SiPHY™ SONET/SDH C L O C K A N D D A TA R E C O V E R Y IC Description Features The Si5017 evaluation board provides a platform for testing and characterizing Silicon Laboratories’ Si5017 SiPHY™ SONET/SDH clock and data recovery IC. The Si5017 CDR supports OC-48, STM-16, and 2.7 Gbps FEC rates. „ Single 3.3 V power supply Differential I/Os ac coupled „ Simple jumper configuration „ All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment. Functional Block Diagram VDD 210 Ω Pulse Generator Jitter Analyzer ZC = 50 Ω ZC = 50 Ω ZC = 50 Ω ZC = 50 Ω Si5017 348 Ω Pattern Generator + CLKOUT – + REFCLK – ZC = 50 Ω ZC = 50 Ω + DATAIN – Scope + DATAOUT – ZC = 50 Ω ZC = 50 Ω Pattern Analyzer LOS LOL LTR BER_ALM DSQLCH RESET/CAL CLKDSBL Test Points Jumpers LOS_LVL REXT SLICE_LVL 10 kΩ BER_LVL Si5017-EVB Rev. 1.0 12/02 Copyright © 2002 by Silicon Laboratories Si5017-EVB-DS10 Si5017-EVB Functional Description The evaluation board simplifies characterization of the Si5017 Clock and Data Recovery (CDR) device by providing access to all of the Si5017 I/Os. Device performance can be evaluated by following the “Test Configuration” section. Specific performance metrics include input sensitivity, jitter tolerance, jitter generation, and jitter transfer. Power Supply When applied, REFCLK is used to center the frequency of the DSPLL™ so the device can lock to the data. Ideally, the REFCLK frequency should be 1/128th, 1/32nd, or 1/16th the VCO frequency and must have a frequency accuracy of ±100 ppm. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. Typical REFCLK frequencies are given in Table 1. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board. Table 1. Typical REFCLK Frequencies The evaluation board requires one 3.3 V supply. Supply filtering is placed on the board to filter typical system noise components; however, initial performance testing should use a linear supply capable of supplying the nominal voltage ±5% dc. CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 3.3 V relative to chassis GND. Device Powerdown The CDR can be powered down via the RESET/CAL signal. When asserted, the evaluation board draws minimal current. RESET/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. RESET/CAL is wired to the signal post adjacent to the VDD post. For a valid reset to occur when using external reference clock mode, a proper external reference clock frequency must be applied as specified in Table 1. CLKOUT, DATAOUT, DATAIN CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os) are wired to the board perimeter on 30 mil (0.030 inch) 50 Ω microstrip lines to the end-launch SMA jacks as labeled on the PCB. These I/Os are ac coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential, both the positive (+) and negative (–) terminals must be terminated to 50 Ω. Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 Ω resistors. Note: The 50 Ω termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 Ω + 50 Ω = 100 Ω. SONET/SDH with 15/14 FEC Ratio of VCO to REFCLK 19.44 MHz 20.83 MHz 128 77.76 MHz 83.31 MHz 32 155.52 MHz 166.63 MHz 16 Loss-of-Lock (LOL) Loss-of-lock (LOL) is an indicator of the relative frequency between the data and the REFCLK. LOL asserts when the frequency difference is greater than ±600 ppm. To prevent LOL from de-asserting prematurely, there is hysterisis in returning from the outof-lock condition. LOL will be de-asserted when the frequency difference is less than ±300 ppm. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board. Loss-of-Signal Alarm Threshold Control The loss-of-signal alarm (LOS) is used to signal low incoming data amplitude levels. The programmable threshold control is set by applying a dc voltage level from a low noise voltage source to the LOS_LVL pin. The LOS_LVL is controllable through the BNC jack J10. The mapping of the LOS_LVL voltage to input signal alarm threshold level is shown in Figure 1. The LOS Threshold to LOS Level is mapped as follows: V LOS_LVL – 1.5 V LOS = --------------------------------------25 If this function is not used, install jumper to JP1 header. REFCLK REFCLK is optional for clock and data recovery within the Si5017 device. If REFCLK is not used, jumper both JP15 and JP16. These jumpers pull the REFCLK+ input to VDD and REFCLK– input to GND, which configures the device to operate without an external reference. 2 SONET/SDH Rev. 1.0 Si5017-EVB level is set by applying a dc voltage to the BER_LVL pin. BER_LVL is controllable through the BNC jack J12. Jumper JP7 to disable the BER alarm. Refer to the “BER Detection” section of the Si5016/Si5017 data sheet for threshold level programming. 30 mV 15 mV LOS Undefined LOS Disabled LOS Threshold (mVPP) 40 mV Test Configuration The three critical jitter tests typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5017 Evaluation Board as shown in Figure 2, all three measurements can be easily made. 40 mV/V 0 mV 0V 1.00 V 1.50 V 1.875 V 2.25 V 2.5 V LOS_LVL (V) When applied, REFCLK should be within ±100 ppm of the frequency selected from Table 1 and RESET/CAL must be unjumpered. Figure 1. LOS_LVL Mapping Extended LOS Hysteresis Option An optional LOS Hysteresis Extension circuit is included on the Si5017-EVB to provide a convenient means of increasing the amount of LOS Alarm hysteresis when testing and evaluating the Si5017 LOS functionality. This simple network will extend the LOS hysteresis to approximately 6 dB, thereby preventing unnecessary switching on LOS for low level DATAIN signals in the range of 20 mVPPD. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/LOSA). This circuit is constructed with one CMOS inverter (U2) and two resistors (R12, R13) mounted on the underside of the PCB. If desired, this circuit can be enabled by installing a jumper on JP17 (HYST ENABLE) located near the power entry block. Data Slicing Level The slicing level allows optimization of the input crossover point for systems where the slicing level is not at the amplitude average. The data slicing level can be adjusted from the nominal cross-over point of the data by applying a voltage to the SLICE_LVL pin. SLICE_LVL is controllable through the BNC jack J11. The SLICE_LVL to the data slicing level is mapped as follows: V SLICE_LVL – 1.5 V SLICE = -------------------------------------------50 If this function is not used, jumper JP6. Bit-Error-Rate Alarm Threshold The bit-error-rate of the incoming data can be monitored by the BER_ALM pin. When the bit-error-rate exceeds an externally set threshold level, BER_ALM is asserted. BER_ALM is brought to a test point located in the upper right-hand corner of the board. The BER_ALM threshold Jitter Tolerance: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 Ω). During this test, the Jitter Analyzer directs the Modulation Source to apply prescribed amounts of jitter to the synthesizer source. This “jitters” the pattern generator timebase which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. The Si5017 limiting amplifier can also be examined during this test. Simply lower the amplitude of the incoming data to the minimum value typically expected at the limiting amplifier inputs (typically 10 mVPP for the Si5017 device). Jitter Generation: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 Ω). During this test, there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. Jitter Transfer: Referring to Figure 2, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 Ω). During this test, the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes. Rev. 1.0 3 Si5017-EVB Pulse Generator Scope DATAOUT– Pattern Analyzer GPIB 3.3 V + – REFCLK+ Data Clock- REFCLK– DATAIN+ DATAIN– Pattern Generator + REFCLK – (optional) + DATAIN – DATAOUT + – + CLKOUT – Si5017-EVB DATAOUT+ CLKOUT+ CLKOUT– Jitter Analyzer Data Clock+ GPIB GPIB Clock Synthesizer Signal Source FM Modulation Source GPIB Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation 4 Rev. 1.0 3.3V VDD L1 5 J13 LOS_N POS1 1 POS2 2 C12 tantalum 10uF 2 C17 0603 0.1uF JP2 JP3 JP5 CLKDSBL RESET/CAL DSQLCH NC7SZ04 U2 4 3 JP8 JP9 JP10 JP11 ------LOS JP12 ------LTR R13 0603 10K R9 0603 0 NO LOAD JP17 MKDSN 2,5/3-5,08 ------LOL LOS_N HYSTERESIS ENABLE J10 BNC ---------------BER_ALM C13 R12 JP1 LOS_LVL JP13 VDD 0603 806 0603 100pF C18 C14 0603 0.1uF J11 BNC R10 JP6 SLICE_LVL 0603 100pF C15 0603 0 C19 R11 0603 0.1uF 0603 100pF C16 J12 BNC 0603 0 JP7 BER_LVL JP14 0603 100pF Rev. 1.0 J7 C5 AMP 449692 DIN+ 1 2 8 10 RES/VDDF RES/VDDG LTR DSQLCH 19 24 RESET/CAL CLKDSBL 3 4 26 LOS_LVL SLICE_LVL BER_LVL 11 14 18 21 25 U1 0603 0.1uF VDDA VDDB VDDC VDDD VDDE C20 R7 0603 4.99K LOL LOS BER_ALM 7 9 27 BER_MON 28 J8 C6 AMP 449692 0603 0.1uF JP15 12 13 0603 210 J1 16 DOUT+ 17 REFCLK+ CLKOUT- 22 REFCLK- CLKOUT+ 23 DIN- J3 C3 DOUT- DIN+ AMP 449692 0603 0.1uF Si5017 VDD R6 REFCLK+ DOUT- C4 0603 0.1uF DIN- BER_MON AMP 449692 0603 0.1uF J4 C8 AMP 449692 5 DOUT+ 0603 0.1uF 6 J2 C7 AMP 449692 Reference Less Operation (jumper both JP15 and JP16) C2 CLKOUTAMP 449692 JP16 VDD JP4 0603 0.1uF 15 TDI 20 REXT 0603 0.1uF J5 C1 R8 0603 100 REFCLK- R1 0603 10k (1%) Si5017 AMP 449692 0603 0.1uF J6 CLKOUT+ NO LOAD Figure 3. Si5017 Schematic 5 Si5017-EVB R5 0603 348 Si5017-EVB Bill of Materials Si5017EVB Assy Rev B-01 BOM 6 2/8/2002 Reference Description Manufacturer's # Manufacturer C1,C2,C3,C4,C5,C6, C7,C8,C17,C18,C19, C20 C12 C13,C14,C15,C16 JP1,JP6,JP7,JP11, JP12,JP13,JP14, JP15,JP16,JP17 JP2,JP3,JP5,JP8, J1,J2,J3,J4,J5,J6, J7,J8 J10,J11,J12 J13 L1 R1,R13 R5 R6 R7 R8 R10,R11 R12 U1 U2 PCB No Load R9 JP4,JP9,JP10 CAP,SM,0.1UF,16V,20%,X7R,0603 C0603X7R160-104KNE VENKEL CAP,SM,10UF,10V,10%,TANTALUM,3216 CAP,SM,100PF,50V,10%,C0G,0603 CONN,HEADER,2X1 TA010TCM106KAR VENKEL C0603C0G500-101KNE VENKEL 2340-6111TN or 2380-6121TN 3M CONN,HEADER,3X1 CONN,SMA SIDE MOUNT 2340-6111TN or 2380-6121TN 3M 901-10003 AMPHENOL CONN,BNC,VERT CONN,POWER,2 POSITION FERRITE,SM,600,1206 RES,SM,10K,1%,0603 RES,SM,348,1%,0603 RES,SM,210,1%,0603 RES,SM,4.99K,1%,0603 RES,SM,100,1%,0603 RES,SM,0,0603 RES,SM,806,1%,0603 Si5017 Rev B Device IC,SM,7SZ04,SINGLE GATE INVERTER,5 PIN SOT23 Printed Circuit Board 161-9317 1729018 BLM31A601S CR0603-16W-1002FT CR0603-16W-3480FT CR0603-16W-2100FT CR0603-16W-4991FT CR0603-16W-1000FT CR0603-16W-000T CR0603-16W-8060FT Si5017-BM Rev B NC7SZ04M5X Si5017-EVB PCB Rev C RES,SM,0,0603 CONN,HEADER,3X1 CR0603-16W-000T VENKEL 2340-6111TN or 2380-6121TN 3M Rev. 1.0 MOUSER PHOENIX CONTACT MURATA VENKEL VENKEL VENKEL VENKEL VENKEL VENKEL VENKEL SILICON LABORATORIES FAIRCHILD SILICON LABORATORIES Si5017-EVB Figure 4. Si5017 Top View Rev. 1.0 7 Si5017-EVB Figure 5. Si5017 Component Side 8 Rev. 1.0 Si5017-EVB Figure 6. Si5017 Solder Side Rev. 1.0 9 Si5017-EVB Document Change List Revision 0.23 to Revision 1.0 „ “Preliminary” language removed. Evaluation Board Assembly Revision History 10 Assembly Level PCB Rev. Si5017 Rev. B-01 Rev. C Rev. B Assembly Notes Assemble per BOM rev B-01 Rev. 1.0 Si5017-EVB Notes: Rev. 1.0 11 Si5017-EVB Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Rev. 1.0