SI5018-B-GM

Si5018 SiPHY™ OC-48/STM-16 C LOCK AND D ATA R ECOVERY IC W ITH FEC Features Complete high-speed, low-power, CDR solution includes the following: „ Supports OC-48 /STM-16 & FEC „ Low power—270 mW „ (typ OC-48) „ Small footprint: 4x4 mm „ DSPLL™ Eliminates external „ loop filter components „ „ 3.3 V tolerant control inputs „ Exceeds all SONET/SDH jitter specifications Jitter generation 3.0 mUIrms (typ) „ Device powerdown Loss-of-lock indicator Single 2.5 V Supply Ordering Information: See page 17. Applications Pin Assignments „ Optical transceiver modules „ SONET/SDH regenerators „ Board level serial links CLKOUT– CLKOUT+ Description GND Si5018 GND SONET/SDH/ATM routers „ Add/drop multiplexers „ Digital cross connects „ SONET/SDH test equipment GND „ 20 19 18 17 16 REXT 1 15 PWRDN/CAL VDD 2 14 VDD GND 3 13 DOUT+ REFCLK+ 4 12 DOUT– REFCLK– 5 11 VDD 7 8 9 10 VDD DIN+ DIN– 6 GND GND Pad Connection LOL The Si5018 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/STM-16 data rates. In addition, support for 2.7 Gbps data streams is also provided for applications that employ forward error correction (FEC). DSPLL™ technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5018 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (–40 to 85 °C). Functional Block Diagram LOL D IN + D IN – 2 BU F D SPLLTM Phas e-Locked Loop R etim er BU F 2 D OU T + D OU T – PW R D N /C AL Bias R EXT Rev. 1.3 6/08 2 BU F 2 C LKOU T + C LKOU T – R EF C LKIN + R EF C LKIN – Copyright © 2008 by Silicon Laboratories Si5018 Si5018 2 Rev. 1.3 Si5018 TABLE O F C ONTENTS Section Page Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev. 1.3 3 Si5018 1. Detailed Block Diagram DOUT+ Retim e DOUT– c DIN+ DIN– Phase Detector A/D VCO DSP CLK Divider CLKOUT+ c CLKOUT– n REFCLK+ Lock Detector REFCLK– LOL REXT Calibration Bias G eneration 4 PWRDN/CAL Rev. 1.3 Si5018 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature Si5018 Supply Voltage2 Test Condition Min1 Typ Max1 Unit TA –40 25 85 °C VDD 2.375 2.5 2.625 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5018 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "Typical Application Schematic‚" on page 9. V SIGNAL+ VICM,VOCM Differential I/Os SIGNAL– VIS Single-Ended Voltage (SIGNAL+) – (SIGNAL–) VID,VOD (VID = 2VIS) Differential Voltage Swing Differential Peak-to-Peak Voltage t Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) t C-D DOUT CLKOUT Figure 2. Differential Clock to Data Timing 80% DOUT, CLKOUT 20% tF tR Figure 3. Differential DOUT and CLKOUT Rise/Fall Times Rev. 1.3 5 Si5018 Table 2. DC Characteristics (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current IDD — 108 122 mA Power Dissipation PD — 270 320 mW Common Mode Input Voltage (DIN, REFCLK)* VICM varies with VDD — .80 x VDD — V Single Ended Input Voltage (DIN, REFCLK)* VIS See Figure 1 200 — 750 mVPP Differential Input Voltage Swing (DIN, REFCLK)* VID See Figure 1 200 — 1500 mVPP Input Impedance (DIN, REFCLK) RIN Line-to-Line 84 100 116 Ω Differential Output Voltage Swing (DOUT) OC48 VOD 100 Ω Load Line-to-Line 780 990 1260 mVPP Differential Output Voltage Swing (CLKOUT) OC48 VOD 100 Ω Load Line-to-Line 550 900 1260 mVPP Output Common Mode Voltage (DOUT,CLKOUT) VOCM 100 Ω Load Line-to-Line — VDD – 0.23 — V Output Impedance (DOUT,CLKOUT) ROUT Single-ended 84 100 116 Ω Output Short to GND (DOUT,CLKOUT) ISC(–) — 25 31 mA Output Short to VDD (DOUT,CLKOUT) ISC(+) –17.5 –14.5 — mA Input Voltage Low (LVTTL Inputs) VIL — — .8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 10 μA Input High Current (LVTTL Inputs) IIH — — 10 μA Output Voltage Low (LVTTL Outputs) VOL IO = 2 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 2 mA 2.4 — — V Input Impedance (LVTTL Inputs) RIN 10 — — kΩ PWRDN/CAL Leakage Current IPWRDN 15 25 35 μA VPWRDN ≥ 0.8 V *Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min), and the unused input must be ac coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the specified maximum Input Voltage Range (VIS max). 6 Rev. 1.3 Si5018 Table 3. AC Characteristics (Clock and Data) (VA 2.5 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Output Clock Rate fCLK Output Rise/Fall Time tR,tF Figure 3 Clock to Data Delay FEC (2.7 GHz) OC-48 tC-D Figure 2 Input Return Loss 100 kHz–2.5 GHz 2.5 GHz–4.0 GHz Min Typ Max Unit 2.4 — 2.7 GHz — 80 110 ps 225 225 250 250 270 270 ps — — 16 13 — — dB dB Table 4. AC Characteristics (PLL Characteristics) (VA 2.5 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance* JTOL(P–P) f = 600 Hz 40 — — UIPP f = 6000 Hz 4 — — UIPP f = 100 kHz 4 — — UIPP f = 1 MHz .4 — — UIPP RMS Jitter Generation* JGEN(rms) with no jitter on serial data — 2.9 5.0 mUI Peak-to-Peak Jitter Generation* JGEN(PP) with no jitter on serial data — 25 55 mUI JBW — — 2.0 MHz JP — 0.03 0.1 dB After falling edge of PWRDN/CAL 1.45 1.5 1.7 ms From the return of valid data 40 60 150 μs CDUTY 40 50 60 % CTOL –100 — 100 ppm 19.44 — 168.75 MHz Jitter Transfer Bandwidth* Jitter Transfer Peaking* Acquisition Time Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance TAQ Reference Clock Range Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL 450 600 750 ppm Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK 150 300 450 ppm *Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 – 1 data pattern. Rev. 1.3 7 Si5018 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 2.8 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 °C Storage Temperature Range TSTG –55 to 150 °C 1 kV ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 8 Symbol Test Condition Value Unit ϕJA Still Air 38 °C/W Rev. 1.3 Si5018 3. Typical Application Schematic Powerdown PWRDN/CAL DOUT+ DIN– DOUT– Si5018 REFCLK+ CLKOUT+ CLKOUT– Recovered Data Recovered Clock GND REFCLK– VDD System Reference Clock DIN+ REXT High-Speed Serial Input LOL Loss-of-Lock Indicator 0.1 μF 10 kΩ (1%) VDD 2200 pF 20 pF Rev. 1.3 9 Si5018 4. Functional Description The Si5018 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLL™ technology to eliminate the noise entry points caused by external PLL loop filter components. 4.1. DSPLL™ The phase-locked loop structure (shown in "Typical Application Schematic‚" on page 9) utilizes Silicon Laboratories' DSPLL™ technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain. no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5018 uses the reference clock to center the VCO output frequency at the OC-48/STM-16 data rate. The device will selfconfigure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.488 GHz and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies are given in Table 7. Table 7. Typical REFCLK Frequencies OC-48/ STM-16 (2.488 GHz) OC-48/STM-16 w/ 15/14 FEC (2.666 GHz) Ratio of VCO to REFCLK 19.44 MHz 20.83 MHz 128 77.76 MHz 83.31 MHz 32 155.52 MHz 166.63 MHz 16 4.2. PLL Self-Calibration 4.4. Forward Error Correction (FEC) The Si5018 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on powerup. The Si5018 supports FEC in SONET OC-48 (SDH STM-16) applications for data rates up to 2.7 Gbps. In FEC applications, the appropriate reference clock frequency is determined by dividing the input data rate by 16, 32, or 128. For example, if an FEC code is used that produces a 2.7 Gbps data rate, the required reference clock would be 168.75 MHz, 84.375 MHz, or 21.09 MHz. A self-calibration can be initiated by forcing a high-tolow transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 μs before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories’ “AN42: Controlling DSPLL™ Self-Calibration for the Si5020/5018/5010 CDR Devices and Si531x Clock Multiplier/Regenerator Devices.” 4.3. The Si5018 CDR requires an external reference clock applied to the REFCLK input for normal device operation. When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that 10 4.5. Lock Detect The Si5018 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out of lock, and the loss-oflock (LOL) pin is asserted high. In this state, the PLL will Reference Clock Detect periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock may drift over a ±600 ppm range relative to the applied reference clock, and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the Rev. 1.3 Si5018 low noise and stability of the DSPLL, under the condition where data is removed from the inputs, there is the possibility that the PLL will not drift enough to render an out-of-lock condition. Sinusoidal Input Jitter (UIPP) If REFCLK is removed, the LOL output alarm is always asserted when it has been determined that no activity exists on REFCLK, indicating the frequency lock status of the PLL is unknown. 20 dB/Decade Slope 15 1.5 0.15 Note: LOL is not asserted during PWRDN/CAL. 4.6. PLL Performance f0 f1 f2 f3 ft Frequency The PLL implementation used in the Si5018 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. 4.6.1. Jitter Tolerance The Si5018’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 4. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. SONET Data Rate F0 (Hz) F1 (Hz) F2 (Hz) F3 (kHz) Ft (kHz) OC- 48 10 600 6000 100 1000 Figure 4. Jitter Tolerance Specification Jitter Trans f er 4.6.2. Jitter Transfer The Si5018 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 5). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 4. 20 dB / Dec ade Slope 0.1 dB A c c eptable Range 4.6.3. Jitter Generation Fc Frequenc y The Si5018 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5018 generates less than 3.0 mUIrms of jitter when presented with jitter free input data. S ONET Da ta Ra te OC- 48 Fc (kHz) 2000 Figure 5. Jitter Transfer Specification 4.7. Powerdown The Si5018 provides a powerdown pin, PWRDN/CAL, that disables the output drivers (DOUT, CLKOUT). When the PWRDN/CAL pin is driven high, the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels. When PWRDN/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream. 4.8. Device Grounding The Si5018 uses the GND pad on the bottom of the 20- Rev. 1.3 11 Si5018 pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. 4.9. Bias Generation Circuitry The Si5018 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. 4.10. Differential Input Circuitry The Si5018 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is possible, the 0.1 μF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6. Si5018 Dif f erential Driv er V DD 2.5 k Ω 0.1 μ F Z o = 50 Ω D IN +, R F C LK + Z o = 50 Ω D IN –, R F C LK – 10 k Ω 0.1 μ F 2.5 k Ω 102 Ω 10 k Ω GND Figure 6. Input Termination for DIN and REFCLK (AC Coupled) Si5018 Clock source VDD 2.5 kΩ 0.1 μF Zo = 50 Ω REFCLK + 10 kΩ 2.5 kΩ 100 Ω 102 Ω REFCLK – 10 kΩ 0.1 μF GND Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled) 12 Rev. 1.3 Si5018 Si5018 Clock source VDD 2.5 kΩ 0.1 μF Zo = 50 Ω DIN + 10 kΩ 2.5 kΩ 100 Ω 102 Ω DIN – 10 kΩ 0.1 μF GND Figure 8. Single-Ended Input Termination for DIN (AC Coupled) Rev. 1.3 13 Si5018 4.11. Differential Output Circuitry The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 μF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. Si5018 V DD V DD 50 Ω 100 Ω DOUT +, CLKOUT + 0.1 μ F Z o = 50 Ω DOUT –, CLKOUT – 0.1 μ F Z o = 50 Ω 100 Ω V DD 50 Ω V DD Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled) 14 Rev. 1.3 Si5018 CLKOUT– CLKOUT+ GND GND GND 5. Pin Descriptions: Si5018 20 19 18 17 16 REXT 1 15 PWRDN/CAL VDD 2 14 VDD GND 3 13 DOUT+ REFCLK+ 4 12 DOUT– REFCLK– 5 11 VDD 6 7 8 9 10 LOL VDD GND DIN+ DIN– GND Pad Connection Figure 10. Si5018 Pin Configuration Table 8. Si5018 Pin Descriptions Pin # Pin Name I/O Signal Level Description 1 REXT 4 5 REFCLK+ REFCLK– I See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. 6 LOL O LVTTL Loss-of-Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 7. 9 10 DIN+ DIN– I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. 12 13 DOUT– DOUT+ O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. Rev. 1.3 15 Si5018 Table 8. Si5018 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 15 PWRDN/CAL I LVTTL Powerdown. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration‚" on page 10.) Note: This input has a weak internal pulldown. CML Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK. VDD 2.5 V Supply Voltage. Nominally 2.5 V. GND GND Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground. 16 17 CLKOUT– CLKOUT+ 2, 7, 11, 14 3, 8, 18, 19, 20, and GND Pad 16 O Rev. 1.3 Si5018 6. Ordering Guide Part Number Package Voltage Pb-Free Temperature Si5018-X-GM 20-Lead QFN 2.5 Yes –40 to 85 °C 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Silicon Labs Part Number Die Revision (R) Assembly Date (YWW) Si5018-B-GM B Y = Last digit of current year WW = Work week Rev. 1.3 17 Si5018 8. Package Outline Figure 11 illustrates the package details for the Si5018. Table 9 lists the values for the dimensions shown in the illustration. Figure 11. 20-pin Quad Flat No-Lead (QFN) Table 9. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 c — — D D2 Min Nom Max E2 1.95 2.10 2.25 L 0.50 0.60 0.70 0.30 θ 0° — 12° 0.60 aaa 0.10 bbb 0.10 ccc 0.08 4.00 BSC 1.95 2.10 Millimeters 2.25 e 0.50 BSC ddd 0.10 E 4.00 BSC eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-1. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 18 Rev. 1.3 Si5018 9. 4x4 mm 20L QFN Recommended PCB Layout See Note 8 Gnd Pin See Note 9 Gnd Pin Gnd Pin Symbol Parameter Dimensions Min Nom Max A Pad Row/Column Width/Length 2.23 2.25 2.28 D Thermal Pad Width/Height 2.03 2.08 2.13 e Pad Pitch — 0.50 BSC — G Pad Row/Column Separation 2.43 2.46 2.48 R Pad Radius — 0.12 REF — X Pad Width 0.23 0.25 0.28 Y Pad Length — 0.94 REF — Z Pad Row/Column Extents 4.26 4.28 4.31 Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad. 3. The center thermal pad is to be Solder Mask Defined (SMD). 4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent solder from flowing into the via hole. 5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a 0.65 mm pitch, should be used for the center thermal pad. 6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate paste release. 7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended. 8. Do not place any signal or power plane vias in these “keep out” regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane. Rev. 1.3 19 Si5018 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 „ Added "Top Mark‚" on page 17. Updated "Package Outline‚" on page 18. „ Added "4x4 mm 20L QFN Recommended PCB Layout‚" on page 19. „ Revision 1.1 to Revision 1.2 „ Made minor note corrections to "4x4 mm 20L QFN Recommended PCB Layout‚" on page 19. Revision 1.2 to Revision 1.3 „ „ 20 Updated "Ordering Guide‚" on page 17. Updated "Package Outline‚" on page 18. Rev. 1.3 Si5018 NOTES: Rev. 1.3 21 Si5018 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, DSPLL, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev. 1.3