SI52146

Si52146 PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR Features       PCI-Express Gen 1, Gen 2, &  Gen 3 compliant Low power push-pull type  differential output buffers Integrated resistors on differential  clocks Dedicated output enable pin for each clock Hardware selectable spread  control Six PCI-Express clocks  25 MHz crystal input or clock input I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature: –40 to 85 oC 3.3 V Power supply  32-pin QFN package Ordering Information: See page 18 Applications   Pin Assignments CKPWRGD_PDB1 SDATA 26 XOUT OE11 OE01 32 31 30 29 VDD XIN 28 27 25 24 VDD 23 DIFF5 22 DIFF5 21 VDD Description The Si52146 is a spread-controlled PCIe clock generator that can source six PCIe clocks simultaneously. The device has six hardware inputs for enabling the respective outputs on the fly while powered on along with the spread control hardware pin to enable Spread for EMI reduction. VDD OE21 SSON 2 OE31 OE41 OE51 NC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 GND SCLK 20 Network attached storage Multi-function printer   Wireless access point Routers DIFF4 19 DIFF4 18 DIFF3 17 DIFF3 DIFF1 DIFF0 DIFF0 DIFF1 DIFF2 VDD Notes: 1 . Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. DIFF0 XIN/CLKIN XOUT DIFF1 Patents pending PLL1 (SSC) Divider DIFF2 DIFF3 DIFF4 SCLK SDATA CKPWRGD/PDB OE [5:0] SSON DIFF5 Control & Memory Control RAM Preliminary Rev. 0.1 12/11 Copyright © 2011 by Silicon Laboratories DIFF2 VDD Functional Block Diagram Si52146 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i52146 2 Preliminary Rev. 0.1 S i52146 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Preliminary Rev. 0.1 3 S i52146 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter 3.3 V Operating Voltage 3.3 V Input High Voltage 3.3 V Input Low Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current 3.3 V Output High Voltage (SE) 3.3 V Output Low Voltage (SE) High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Power Down Current Dynamic Supply Current Symbol VDD core VIH VIL VIHI2C VILI2C IIH IIL VOH VOL IOZ CIN COUT LIN IDD_PD IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. Test Condition 3.3 ±5% Control input pins Control input pins SDATA, SCLK SDATA, SCLK Except internal pull-down resistors, 0 < VIN < VDD Except internal pull-up resistors, 0 < VIN < VDD IOH = –1 mA IOL = 1 mA Min 3.135 2.0 VSS – 0.3 2.2 — — –5 2.4 — –10 1.5 — — — — Typ 3.3 — — — — — — — — — — — — — — Max 3.465 VDD + 0.3 0.8 — 1.0 5 — — 0.4 10 5 6 7 1 60 Unit V V V V V A A V V A pF pF nH mA mA 4 Preliminary Rev. 0.1 S i52146 Table 2. AC Electrical Specifications Parameter Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle CLKIN Rise and Fall Times CLKIN Cycle to Cycle Jitter CLKIN Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF at 0.7 V DIFF Duty Cycle Symbol LACC TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL TDC Condition Measured at VDD/2 differential Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN