SI53106-A01AGM

Si53106 S IX -O UTPUT PCI E G EN 3 BUFFER /Z ERO D ELAY B UFFER Features      Six 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch value from HW pin SMBus address configurable to allow multiple buffers in a single control network 3.3 V supply voltage operation  Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant  Gen 3 SRNS Compliant  PLL or bypass mode  Spread spectrum tolerable  1.05 to 3.3 V I/O supply voltage  50 ps output-to-output skew  Industrial Temperature: –40 to 85 °C  40-pin QFN  For higher output devices or variations of this device, contact Silicon Labs Ordering Information: See page 29. Patents pending Applications Server  Storage  Datacenter  Enterprise Switches and Routers  Description The Si53106 is a low-power, 6-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Rev. 1.2 12/15 Copyright © 2015 by Silicon Laboratories Si53106 Si53106 Functional Block Diagram OE_[5:0] 6 SSC Compatible PLL CLK_IN CLK_IN 100M_133 HBW_BYPASS_LBW SA_0 SA_1 PWRGD / PWRDN SDA SCL 2 Control Logic Rev. 1.2 DIF_[5:0] Si53106 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2. OE and Output Enables (Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5. PWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Pin Descriptions: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Rev. 1.2 3 Si53106 1. Electrical Specifications Table 1. DC Operating Characteristics VDD_A = 3.3 V±5%, VDD = 3.3 V±5% Parameter Symbol Test Condition Min Max Unit VDD/VDD_A 3.3 V ±5% 3.135 3.465 V VDD_IO 1.05 V to 3.3 V ±5% 0.9975 3.465 V 3.3 V Input High Voltage VIH VDD 2.0 VDD+0.3 V 3.3 V Input Low Voltage VIL VSS-0.3 0.8 V 3.3 V Core Supply Voltage 3.3 V I/O Supply Input Leakage Voltage1 Current2 IIL 0 < VIN < VDD –5 +5 µA 3 3.3 V Input High Voltage VIH_FS VDD 0.7 VDD+0.3 V 3 3.3 V Input Low Voltage VIL_FS VSS–0.3 0.35 V 3.3 V Input Low Voltage VIL_Tri 0 0.8 V 3.3 V Input Med Voltage VIM_Tri 1.2 1.8 V 3.3 V Input High Voltage VIH_Tri 2.4 VDD V Voltage4 VOH IOH = –1 mA 2.4 — V 3.3 V Output Low Voltage4 VOL IOL = 1 mA — 0.4 V CIN 2.5 4.5 pF COUT 2.5 4.5 pF LPIN — 7 nH –40 85 °C 3.3 V Output High Input Capacitance Output 5 Capacitance5 Pin Inductance Ambient Temperature TA No Airflow Notes: 1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs. 2. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Inputs with resistors should state current requirements. 3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS thresholds levels over full operating range. 4. Signal edge is required to be monotonic when transitioning through this region. 5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance. Table 2. Current Consumption TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5% Parameter Operating Current Symbol Min Typ Max Unit IDDVDD 133 MHz, VDD Rail — 19 30 mA IDDVDDA 133 MHz, VDDA + VDDR, PLL Mode — 15 25 mA IDDVDDIO 133 MHz, CL = Full Load, VDD IO Rail — 49 65 mA Power Down, VDD Rail — 0.45 1 mA IDDVDDAPD Power Down, VDDA Rail — 4.5 7 mA IDDVDDIOPD Power Down, VDD_IO Rail — 0.23 0.5 mA Power Down Current IDDVDDPD 4 Test Condition Rev. 1.2 Si53106 Table 3. Output Skew, PLL Bandwidth and Peaking TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5% Parameter Test Condition Min Typ Max Unit –100 –15 100 ps 2.5 3.6 4.5 ns CLK_IN, DIF[x:0] Input-to-Output Delay in PLL Mode Nominal Value1,2,3,4 CLK_IN, DIF[x:0] Input-to-Output Delay in Bypass Mode \Nominal Value2,4,5 CLK_IN, DIF[x:0] Input-to-Output Delay Variation in PLL mode Over voltage and temperature2,4,5 –100 39 100 ps CLK_IN, DIF[x:0] Input-to-Output Delay Variation in Bypass Mode Over voltage and temperature2,4,5 –250 3.7 250 ps Output-to-Output Skew across all 6 Outputs (Common to Bypass and PLL Mode)1,2,3,4,5 0 20 50 ps PLL Jitter Peaking (HBW_BYPASS_LBW = 0)6 — 0.4 2.0 dB PLL Jitter Peaking (HBW_BYPASS_LBW = 1)6 — 0.1 2.5 dB PLL Bandwidth (HBW_BYPASS_LBW = 0)7 — 0.7 1.4 MHz PLL Bandwidth (HBW_BYPASS_LBW = 1)7 — 2 4 MHz DIF[11:0] Notes: 1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point. 3. This parameter is deterministic for a given device. 4. Measured with scope averaging on to find mean value. 5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 7. Measured at 3 db down or half power point. Rev. 1.2 5 Si53106 Table 4. Clock Input Parameters TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5% Parameter Input Frequency Symbol FIN Test Condition Min Typ Max Unit Bypass Mode 33 — 150 MHz PLL Mode, 100 MHz 90 100 110 MHz PLL Mode, 133.33 MHz 120 133.33 147 MHz Input High Voltage- CLK_IN VIHDIF Differential inputs single-ended measurement 600 800 1150 mV Input Low Voltage- CLK_IN VILDIF Differential inputs single-ended measurement VSS –300 0 300 mV Input Common Mode Voltage - CLK_IN VCOM Common Mode Voltage Input 300 — 1000 mV Input Amplitude- CLK_IN VSwing Peak to Peak 300 — 1450 Input Slew Rate- CLK_IN IDDVDDAPD Measured differentially 0.4 — 8 V/ns Input Leakage Current IIN VIN = VDD, VIN = GND -5 — 5 A Input Duty Cycle dtin Measured from differential waveform 45 — 55 % Input Jitter, Cycle-Cycle JDIFIN Differential measurement 0 — 125 ps Input SS Modulation Frequency fMODIN Triangle Wave Modulation 30 — 33 kHz 6 Rev. 1.2 Si53106 Table 5. Phase Jitter Parameter Phase Jitter PLL Mode Test Condition Min Typ Max Unit — 29 86 ps PCIe Gen 2 Low Band, Common Clock F < 1.5 MHz1,3,4,5 — 2.3 3.0 ps (RMS) PCIe Gen 2 High Band, Common Clock 1.5 MHz < F < Nyquist1,3,4,5 — 2.4 3.1 ps (RMS) PCIe Gen 3, Common Clock (PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 — 0.6 1.0 ps (RMS) PCIe Gen 3 Separate Reference No Spread, SRNS (PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,3,4,5 — 0.42 0.71 ps (RMS) PCIe Gen 4, Common Clock (PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8 — 0.6 1.0 ps (RMS) Intel® QPI & Intel SMI (4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 — 0.21 0.5 ps (RMS) Intel QPI & Intel SMI (8 Gb/s, 100 MHz, 12 UI)1,6 — 0.13 0.3 ps (RMS) Intel QPI & Intel SMI (9.6 Gb/s, 100 MHz, 12 UI)1,6 — 0.11 0.2 ps (RMS) PCIe Gen 1, Common Clock 1,2,3 Notes: 1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a smaller sample size have to be extrapolated to this BER target. 2. ζ = 0.54 implies a jitter peaking of 3 dB. 3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest specification. 4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target. 8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Rev. 1.2 7 Si53106 Table 5. Phase Jitter (Continued) Additive Phase Jitter Bypass Mode PCIe Gen 11,2,3 — 10 — ps PCIe Gen 2 Low Band F < 1.5 MHz1,3,4,5 — 1.6 — ps (RMS) PCIe Gen 2 High Band 1.5 MHz < F < Nyquist1,3,4,5 — 1.6 — ps (RMS) PCIe Gen 3 (PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 — 0.4 — ps (RMS) PCIe Gen 4, Common Clock (PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8 — 0.4 — ps (RMS) Intel QPI & Intel® SMI (4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 — 0.12 — ps (RMS) Intel QPI & Intel® SMI (8 Gb/s, 100 MHz, 12 UI)1,6 — 0.1 — ps (RMS) Intel QPI & Intel® SMI (9.6 Gb/s, 100 MHz, 12 UI)1,6 — 0.09 — ps (RMS) Notes: 1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a smaller sample size have to be extrapolated to this BER target. 2. ζ = 0.54 implies a jitter peaking of 3 dB. 3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest specification. 4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3. 7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target. 8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. 8 Rev. 1.2 Si53106 Table 6. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 Parameter Symbol CLK 100 MHz, 133 MHz Min Typ Max Unit Notes 2 Clock Stabilization Time TSTAB — 1.5 1.8 ms Long Term Accuracy LACC — — 100 ppm Absolute Host CLK Period (100MHz) TABS 9.94900 — 10.05100 ns 346 Absolute Host CLK Period (133MHz) TABS 7.44925 — 7.55075 ns 346 Edge_rate 1.0 — 4.0 V/ns 347 Rise Time Variation ∆ TRISE — — 125 ps 389 Fall Time Variation ∆ TFALL — — 125 ps 389 Rise/Fall Matching TRISE_MAT/ TFALL_MAT — — 20 % 3 8 10 11 Voltage High (typ 0.7 V) VHIGH 660 — 850 mV 3,8,12 Voltage Low (typ 0.7 V) VLOW –150 — 150 mV 3,8,13 Maximum Voltage VMAX — — 1150 mV 8 Absolute Crossing Point Voltages VoxABS 250 — 550 mV 3,8,14,15, Total Variation of VCROSS Over All Edges Total ∆ Vox — — 140 mV 3,8,18 Duty Cycle DC 45 — 55 % 3,4 Maximum Voltage (Overshoot) Vovs — — VHigh + 0.3 V 3,8,19 Maximum Voltage (Undershoot) Vuds — — VLow – 0.3 V 3,8,20 Edge Rate Rev. 1.2 34 , ,5 , , , , , , , , , , , , , 16 9 Si53106 Table 6. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued) Parameter Ringback Voltage Symbol Vrb CLK 100 MHz, 133 MHz Min Typ Max 0.2 — N/A Unit Notes V 38 , Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the time that stable clocks are output from the buffer chip (PLL locked). 3. Test configuration is RS = 33.2 , RP = 49.9, 2 pF for 100  transmission line; RS = 27 , RP = 42.2, 2 pF for 85  transmission line. 4. Measurement taken from differential waveform. 5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz. 6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum specified period. 7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV to +150 mV on the differential waveform . Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge Only valid for Rising clock and Falling CLOCK. Signal must be monotonic through the VOL to VOH region for TRISE and TFALL. 8. Measurement taken from single-ended waveform. 9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max. 10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the falling edge rate (average) of CLOCK. 11. Rise/Fall matching is derived using the following, 2*(TRISE - TFALL) / (TRISE + TFALL). 12. VHIGH is defined as the statistical average High value as obtained by using the Oscilloscope VHIGH Math function. 13. VLOW is defined as the statistical average Low value as obtained by using the Oscilloscope VLOW Math function. 14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK. 15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 16. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 17. VCROSS(rel) Min and Max are derived using the following, VCROSS(rel) Min = 0.250 + 0.5 (VHAVG – 0.700), VCROSS(rel) Max = 0.550 – 0.5 (0.700 – VHAVG), (see Figures 3-4 for further clarification). 18. VCROSS is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the maximum allowed variance in VCROSS for any particular system. 19. Overshoot is defined as the absolute value of the maximum voltage. 20. Undershoot is defined as the absolute value of the minimum voltage. 10 Rev. 1.2 Si53106 Table 7. Clock Periods Differential Clock Outputs with SSC Disabled SSC ON Center Freq, MHz Measurement Window 1 Clock 1 µs –C–C Jitter AbsPer Min 0.1 s –SSC –ppm Long Short Term AVG Term AVG Min Min 0.1 s Unit 0.1 s 1 µs 0 ppm Period Nominal +SSC +ppm Short Long Term AVG Term AVG Max Max 1 Clock +C–C Jitter AbsPer Max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns Table 8. Clock Periods Differential Clock Outputs with SSC Enabled SSC ON Center Freq, MHz Measurement Window 1 Clock 1 µs 0.1 s –ppm –SSC Long Short Term AVG Term AVG Min Min –C–C Jitter AbsPer Min 0.1 s 0.1 s Unit 1 µs 0 ppm Period Nominal +SSC +ppm Short Long Term AVG Term AVG Max Max 1 Clock +C–C Jitter AbsPer Max 99.75 9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126 ns 133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845 ns Table 9. Absolute Maximum Ratings Parameter Symbol Min Max Unit VDD/VDD_A — 4.6 V VDD_IO — 4.6 V VIH — 4.6 V VIL −0.5 — V Storage Temperature1 ts –65 150 °C Input ESD protection3 ESD 2000 — V 3.3 V Core Supply Voltage1 3.3 V I/O Supply Voltage1 3.3 V Input High Voltage 1,2 3.3 V Input Low Voltage1 Notes: 1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters. 2. Maximum VIH is not to exceed maximum VDD. 3. Human body model. Rev. 1.2 11 Si53106 2. Functional Description 2.1. CLK_IN, CLK_IN The differential input clock can be sourced from a clock synthesizer, e.g. CK420BQ, CK509B, or CK410B+. 2.2. OE and Output Enables (Control Registers) Each output can be individually enabled or disabled by SMBus control register bits. Additionally, each output of the DIF[11:0] has a dedicated OE pin. The OE pins are asynchronous, asserted-low signals. The Output Enable bits in the SMBus registers are active high and are set to enable by default. The disabled state for the Si53106 NMOS push-pull output is Low/Low. Please note that the logic level for assertion or deassertion is different in software than it is on hardware. This follows hardware default nomenclature for communication channels (e.g., output is enabled if the OE# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if OE register is true). Table 10 is a truth table depicting enabling and disabling of outputs via hardware and software. Note that, for the output to be active, the control register bit must be a 1 and the OE pin must be a 0. Note: The assertion and deassertion of this signal is absolutely asynchronous. Table 10. Si53106 Output Management Inputs OE Hardware Pins and Control Register Bits Outputs PLL State PWRGD/ PWRDN CLK_IN/ CLK_IN SMBUS Enable Bit OE Pin DIF/DIF[11:0] FB_OUT/ FB_OUT 0 x x x Low/Low Low/Low OFF 0 x Low/Low Running ON 1 0 Running Running ON 1 1 Low/Low Running ON 1 Running 2.2.1. OE Assertion (Transition from 1 to 0) All differential outputs that were disabled are to resume normal operation in a glitch-free manner. The latency from the assertion to active outputs is 4 to 12 DIF clock periods. 2.2.2. OE De-Assertion (Transition from 0 to 1) The impact of deasserting OE is that each corresponding output will transition from normal operation to disabled in a glitch-free manner. A minimum of four valid clocks will be provided after the deassertion of OE. The maximum latency from the deassertion to disabled outputs is 12 DIF clock periods. 2.3. 100M_133M—Frequency Selection The Si53106 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz. 100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs. Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53106 is operated in 1:1 mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 11. Table 11. Frequency Program Table 100M_133M Optimized Frequency (CLK_IN = CLK_OUT) 0 133.33 MHz 1 100.00 MHz Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner. 12 Rev. 1.2 Si53106 2.4. SA_0, SA_1—Address Selection SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53106. The two trilevel input pins that can configure the device to nine different addresses. Table 12. SMBUS Address Table SA_1 SA_0 SMBUS Address L L D8 L M DA L H DE M L C2 M M C4 M H C6 H L CA H M CC H H CE 2.5. PWRGD/PWRDN PWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to indicating a power-down condition. PWRGD (assertion) is used by the Si53106 to sample initial configurations, such as frequency select condition and SA selections. After PWRGD has been asserted high for the first time, the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering power-saving mode, PWRDN should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO. When PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all ac and dc parameters. Note: The assertion and deassertion of PWRDN is absolutely asynchronous. Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended. Operation in this mode may result in glitches, excessive frequency shifting, etc. Table 13. PWRGD/PWRDN Functionality PWRGD/ PWRDN DIF DIF 0 Low Low 1 Normal Normal Rev. 1.2 13 Si53106 2.5.1. PWRDN Assertion When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/ LOW on the next DIF high-to-low transition. PWRDWN DIF DIF Figure 1. PWRDN Assertion 2.5.2. PWRGD Assertion The power-up latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the assertion of the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN deassertion to a voltage greater than 200 mV. Tstable 0 and