SI5320-F-BC

Si5320 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features „ Ultra-low-jitter clock output with jitter generation as low as 0.3 psRMS „ „ No external components (other than a resistor and standard bypassing) „ Input clock ranges at 19, 39, 78, 155, 311, and 622 MHz „ „ „ „ „ „ Output clock ranges at 19, 155, or 622 MHz Digital hold for loss of input clock Support for forward and reverse FEC clock scaling Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9x9 mm) Ordering Information: Applications „ „ Si5320 Si5320 See page 29. SONET/SDH line/port cards Optical modules Core switches Digital cross connects „ Terabit routers „ „ Description The Si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-192/OC-48 and 10 GbE. This device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’ DSPLL™ technology delivers all PLL functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. FEC rates are supported with selectable 255/ 238 or 238/255 scaling of the clock multiplication ratios. The Si5320 establishes a new standard in performance and integration for ultra-low-jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 V DD GND Biasing & Supply Regulation FXDDELAY CLKIN+ CLKIN– VALTIME LOS CAL_ACTV 2 ÷ ÷ Signal Detect 3 INFRQSEL[2:0] Rev. 2.3 4/05 DH_ACTV DSPLLTM 2 2 FEC[1:0] DBLBW Calibration 2 CLKOUT+ CLKOUT– FRQSEL[1:0] RSTN/CAL BWSEL[1:0] Copyright © 2005 by Silicon Laboratories Si5320 Si5320 NOTES: 2 Rev. 2.3 Si5320 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Pin Descriptions: Si5320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 2.3 3 Si5320 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5320 Supply Voltage3 When Using 3.3 V Supply Symbol Test Condition Min1 Typ Max1 Unit TA –202 25 85 °C VDD33 3.135 3.3 3.465 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5320 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. 3. The Si5320 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 15. 3.3 V operation uses an on-chip voltage regulator and is recommended. 4 Rev. 2.3 Si5320 C LKIN + C LKIN – V IS A. O peration with Single-Ended C lock Input N ote: W hen using single-ended clock sources, the unused clock input on the Si5320 m ust be ac-coupled to ground. C LKIN + 0.5 V ID C LKIN – (C LKIN+) – (C LKIN –) V ID B. O peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided externally. Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) – (C L K IN – ) 0 V tLOS Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 2.3 5 Si5320 Table 2. DC Characteristics, VDD = 3.3 V (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Supply Current 1 Supply Current 2 Power Dissipation Using 3.3 V Supply Clock Output Common Mode Input Voltage (CLKIN) 1,2,3 Symbol Test Condition Min Typ Max Unit IDD Clock in = 622.08 MHz Clock out = 19.44 MHz — 141 155 mA IDD Clock in = 19.44 MHz Clock out = 622.08 MHz — 135 145 mA PD Clock in = 19.44 MHz Clock out = 622.08 MHz — 445 479 mW 1.0 1.5 2.0 V VICM Single-Ended Input Voltage2,3,4 (CLKIN) VIS See Figure 1A 200 — 5004 mVPP Differential Input Voltage Swing2,3,4 (CLKIN) VID See Figure 1B 200 — 5004 mVPP Input Impedance (CLKIN+, CLKIN–) RIN — 80 — kΩ Differential Output Voltage Swing (CLKOUT) VOD 100 Ω Load Line-to-Line 816 906 1100 mVPP Output Common Mode Voltage (CLKOUT) VOCM 100 Ω Load Line-to-Line 1.4 1.8 2.2 V Output Short to GND (CLKOUT) ISC(–) –60 — — mA Output Short to VDD25 (CLKOUT) ISC(+) — 15 — mA Input Voltage Low (LVTTL Inputs) VIL — — 0.8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 50 µA Input High Current (LVTTL Inputs) IIH — — 50 µA Internal Pulldowns (All LVTTL Inputs) Ipd — — 50 µA Input Impedance (LVTTL Inputs) RIN 50 — — kΩ Output Voltage Low (LVTTL Outputs) VOL IO = .5 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = .5 mA 2.0 — — V Notes: 1. The Si5320 device provides weak 1.5 V internal biasing that enables ac-coupled operation. 2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5320 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends maintaining the input clock amplitude below 500 mVPP for optimal performance. 6 Rev. 2.3 Si5320 Table 3. AC Characteristics (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Input Clock Frequency (CLKIN) FEC[1:0] = 00 (non FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN No FEC Scaling Input Clock Frequency (CLKIN) FEC[1:0] = 01 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Frequency (CLKIN) FEC[1:0] = 10 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Rise Time (CLKIN) tR Input Clock Fall Time (CLKIN) tF Input Clock Duty Cycle Min Typ Max Unit 19.436 38.872 77.744 155.48 310.97 621.95 — — — — — — 21.685 43.369 86.738 173.48 346.95 693.90 MHz 18.142 36.284 72.568 145.13 290.27 580.54 — — — — — — 20.239 40.478 80.955 161.91 323.82 647.64 MHz 20.826 41.652 83.305 166.61 333.22 666.44 — — — — — — 23.234 46.465 92.934 185.87 371.74 743.47 MHz Figure 2 — — 11 ns Figure 2 — — 11 ns CDUTY_IN 40 50 60 % fO_19 fO_155 fO_622 — 19.436 155.48 621.95 — — — — — 21.685 173.48 693.90 255/238 FEC Scaling 238/255 FEC Scaling Range* CLKOUT Frequency FRQSEL[1:0] = 00 (no output) FRQSEL[1:0] = 01 FRQSEL[1:0] = 10 FRQSEL[1:0] = 11 MHz CLKOUT Rise Time tR Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline — 213 260 ps CLKOUT Fall Time tF Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline — 191 260 ps Output Clock Duty Cycle CDUTY_OUT Differential: (CLKOUT+) – (CLKOUT–) 48 — 52 % RSTN/CAL Pulse Width tRSTN 20 — — ns *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. Rev. 2.3 7 Si5320 Table 3. AC Characteristics (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Transitionless Period Required on CLKIN for Detecting a LOS Condition. INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 tLOS Figure 3 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 tVAL Min 24/ /fo_622 12 /fo_622 10/ fo_622 9 /fo_622 9 /fo_622 — — — — — — 0.09 12.0 — — 16 Measured from when a valid reference clock is applied until the LOS flag clears Typ fo_622 Max Unit 32/ fo_622 s 0.22 14.1 s 32 /fo_622 32 /fo_622 32/ fo_622 32 /fo_622 32 /fo_622 *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. 8 Rev. 2.3 Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit JTOL(PP) f = 8 Hz 1000 — — ns f = 80 Hz 100 — — ns f = 800 Hz 10 — — ns 12 kHz to 20 MHz — 0.87 1.2 ps 50 kHz to 80 MHz — 0.26 0.35 ps 12 kHz to 20 MHz — 0.85 1.2 ps 50 kHz to 80 MHz — 0.26 0.35 ps 12 kHz to 20 MHz — 7.3 10.0 ps 50 kHz to 80 MHz — 3.7 5.0 ps 12 kHz to 20 MHz — 7.2 10.0 ps 50 kHz to 80 MHz — 3.8 5.0 ps FBW BW = 800 Hz — 800 — Hz JP < 800 Hz — 0.0 0.05 dB f = 16 Hz 500 — — ns f = 160 Hz 50 — — ns f = 1600 Hz 5 — — ns 12 kHz to 20 MHz — 0.78 1.2 ps 50 kHz to 80 MHz — 0.25 0.35 ps 12 kHz to 20 MHz — 7.0 9.0 ps 50 kHz to 80 MHz — 3.8 5.0 ps FBW BW = 1600 Hz — 1600 — Hz JP < 1600 Hz — 0.00 0.05 dB Wander/Jitter at 800 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 0) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[1:0 = 01, 10 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[1:0 = 00 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[1:0 = 01, 10 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 9 Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit JTOL(PP) f = 16 Hz 1000 — — ns f = 160 Hz 100 — — ns f = 1600 Hz 10 — — ns 12 kHz to 20 MHz — 0.82 1.0 ps 50 kHz to 80 MHz — 0.26 0.35 ps 12 kHz to 20 MHz — 0.79 1.0 ps 50 kHz to 80 MHz — 0.26 0.35 ps 12 kHz to 20 MHz — 7.3 10.0 ps 50 kHz to 80 MHz — 3.8 5.0 ps 12 kHz to 20 MHz — 7.1 10.0 ps 50 kHz to 80 MHz — 4.3 5.0 ps FBW BW = 1600 Hz — 1600 — Hz JP < 1600 Hz — 0.0 0.1 dB f = 32 Hz 500 — — ns f = 320 Hz 50 — — ns f = 3200 Hz 5 — — ns 12 kHz to 20 MHz — 0.72 0.9 ps 50 kHz to 80 MHz — 0.24 0.3 ps Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 0) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 JGEN(PP) Jitter Transfer Bandwidth (see Figure 10) Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 10 Rev. 2.3 Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Symbol Test Condition Min Typ Max Unit JGEN(PP) 12 kHz to 20 MHz — 6.8 10.0 ps 50 kHz to 80 MHz — 3.7 5.0 ps FBW BW = 3200 Hz — 3200 — Hz JP < 3200 Hz — 0.05 0.1 dB JTOL(PP) f = 32 Hz 1000 — — ns f = 320 Hz 100 — — ns f = 3200 Hz 10 — — ns 12 kHz to 20 MHz — 0.86 1.2 ps 50 kHz to 80 MHz — 0.29 0.4 ps 12 kHz to 20 MHz — 0.79 1.2 ps 50 kHz to 80 MHz — 0.28 0.4 ps 12 kHz to 20 MHz — 7.7 10.0 ps 50 kHz to 80 MHz — 3.9 5.0 ps 12 kHz to 20 MHz — 7.2 10.0 ps 50 kHz to 80 MHz — 4.0 5.0 ps FBW BW = 3200 Hz — 3200 — Hz JP < 3200 Hz — 0.05 0.1 dB f = 64 Hz 500 — — ns f = 640 Hz 50 — — ns f = 6400 Hz 5 — — ns 12 kHz to 20 MHz — 0.7 1.0 ps 50 kHz to 80 MHz — 0.25 0.3 ps 12 kHz to 20 MHz — 6.6 9.0 ps 50 kHz to 80 MHz — 3.8 5.0 ps Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 0) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 11 Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Symbol Test Condition Min Typ Max Unit FBW BW = 6400 Hz — 6400 — Hz JP < 6400 Hz — 0.05 0.1 dB JTOL(PP) f = 64 Hz 1000 — — ns f = 640 Hz 100 — — ns f = 6400 Hz 10 — — ns 12 kHz to 20 MHz — 1.0 1.4 ps 50 kHz to 80 MHz — 0.38 0.5 ps 12 kHz to 20 MHz — 0.94 1.4 ps 50 kHz to 80 MHz — 0.41 0.6 ps 12 kHz to 20 MHz — 9.4 12.0 ps 50 kHz to 80 MHz — 4.7 5.5 ps 12 kHz to 20 MHz — 8.3 12.0 ps 50 kHz to 80 MHz — 4.6 5.5 ps FBW BW = 6400 Hz — 6400 — Hz JP < 6400 Hz — 0.05 0.1 dB f = 128 Hz 500 — — ns f = 1280 Hz 50 — — ns f = 12800 Hz 5 — — ns 12 kHz to 20 MHz — 0.74 1.0 ps 50 kHz to 80 MHz — 0.30 0.4 ps 12 kHz to 20 MHz — 6.9 9.0 ps 50 kHz to 80 MHz — 4.0 5.0 ps FBW BW = 12,800 Hz — 12800 — Hz JP < 12,800 Hz — 0.05 0.1 dB Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 0) Jitter Tolerance (see Figure 7) (1/1 Scaling) CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(RMS) CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 scaling) JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 scaling) JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 12800 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 12 Rev. 2.3 Si5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit TAQ RSTN/CAL high to CAL_ACTV low, with valid clock input and VALTIME = 0 — 300 350 ms Clock Output Wander with Temperature Gradient 1,2 CCO_TG Stable Input Clock; Temperature Gradient