SI5321-F-BC

Si5321 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features „ Ultra-low jitter clock output with jitter generation as low as 0.3 psRMS „ „ No external components (other than a resistor and bypassing) „ Input clock ranges at 19, 39, 78, 155, „ „ 311, or 622 MHz „ Output clock ranges at 19, 39, 78, 155, „ 311, 622, 1244, or 2488 MHz „ „ Maximum range includes 693 MHz for „ 10 GbE FEC support „ Digital hold for loss-of-input clock Support for 255/238 (15/14), 255/237 (85/79), and 66/64 FEC scaling (ITU-T G.709 and IEEE 802.3ae) Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9x9 mm) Backwards compatible with Si5320 Si5321 Si5321 Ordering Information: Applications See page 30. SONET/SDH line/port cards „ Terabit routers Core switches „ Digital cross connects „ „ Description The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories DSPLL™ technology provides PLL functionality with unparalleled performance. It eliminates external loop filter components, provides programmable loop parameters, and simplifies design. FEC rates are supported by selectable forward and reverse 255/ 238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. The ITU-T G.709 255/237 rate and the IEEE 802.3ae 66/64 rate are supported when using a 155 MHz or higher rate input clock. The performance and integration of Silicon Laboratories’ Si5321 clock IC provides high-level support of the latest specifications and systems. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 V DD GND Biasing & Supply Regulation FXDDELAY CLKIN+ CLKIN– VALTIME LOS CAL_ACTV ÷ 2 DH_ACTV DSPLL™ ÷ CLKOUT+ CLKOUT– 2 Signal Detect 3 2 2 Calibration FRQSEL[2:0] RSTN/CAL BWBOOST BWSEL[1:0] INFRQSEL[2:0] FEC[2:0] Rev. 2.3 4/05 Copyright © 2005 by Silicon Laboratories Si5321 Si5321 2 Rev. 2.3 Si5321 TA B L E O F C O N T E N TS SECTION PAGE 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.5. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 2.3 3 Si5321 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5321 Supply Voltage3, 3.3 V Supply Symbol Test Condition Min1 Typ Max1 Unit TA –202 25 85 °C VDD33 3.135 3.3 3.465 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5321 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. 3. The Si5321 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 16. 4 Rev. 2.3 Si5321 C LKIN + C LKIN – V IS A. O peration with Single-Ended C lock Input* N ote: W hen using single-ended clock sources, the unused clock input on the Si5321 m ust be ac-coupled to ground. C LKIN + 0.5 V ID C LKIN – (C LKIN+) – (C LKIN –) V ID B. O peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided externally. Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) - (C L K IN - ) 0 V tL O S Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 2.3 5 Si5321 Table 2. DC Characteristics, VDD = 3.3 V (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current 1 IDD 622.08 MHz In, 19.44 MHz Out — 141 155 mA Supply Current 2 IDD 19.44 MHz In, 622.08 MHz Out — 135 145 mA Power Dissipation Using 3.3 V Supply Clock Output PD 19.44 MHz In, 622.08 MHz Out — 445 479 mW 1.0 1.5 2.0 V Common Mode Input (CLKIN) Voltage1,2,3 VICM Single-Ended Input Voltage2,3,4 (CLKIN) VIS See Figure 1A 200 — 5004 mVPP Differential Input Voltage Swing2,3,4 (CLKIN) VID See Figure 1B 200 — 5004 mVPP Input Impedance (CLKIN+, CLKIN–) RIN — 80 — kΩ Differential Output Voltage Swing (CLKOUT) VOD 100 Ω Load Line-to-Line 750 825 1100 mVPP Output Common Mode Voltage (CLKOUT) VOCM 100 Ω Load Line-to-Line 1.4 1.8 2.2 V Output Short to GND (CLKOUT) ISC(–) –60 — — mA Output Short to VDD25 (CLKOUT) ISC(+) — 15 — mA Input Voltage Low (LVTTL Inputs) VIL — — 0.8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 50 µA Input High Current (LVTTL Inputs) IIH — — 50 µA Internal Pulldowns (LVTTL Inputs) Ipd — — 50 µA Input Impedance (LVTTL Inputs) RIN 50 — — kΩ Output Voltage Low (LVTTL Outputs) VOL IO = 0.5 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 0.5 mA 2.0 — — V Notes: 1. The Si5321 device provides weak 1.5 V internal biasing that enables ac-coupled operation. 2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be accoupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5321 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends maintaining the input clock amplitude below 500 mVPP for optimal performance. 6 Rev. 2.3 Si5321 Table 3. AC Characteristics (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Input Clock Frequency (CLKIN) FEC[2:0] = 000 (non FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN No FEC Scaling Input Clock Frequency (CLKIN) FEC[2:0] = 001 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Frequency (CLKIN) FEC[2:0] = 010 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Frequency (CLKIN) FEC[2:0] = 100 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Frequency (CLKIN) FEC[2:0] = 101 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Min Typ Max 19.436 38.872 77.744 155.48 310.97 621.95 — — — — — — 21.685 43.369 86.738 173.48 346.95 693.90 18.142 36.284 72.568 145.13 290.27 580.54 — — — — — — 20.239 40.478 80.955 161.91 323.82 647.64 20.826 41.652 83.305 166.61 333.22 666.44 — — — — — — 23.234 46.465 92.934 185.87 371.74 743.47 N/A N/A N/A 144.52 289.05 578.11 N/A N/A N/A — — — N/A N/A N/A 161.23 322.46 644.92 N/A N/A N/A 167.31 334.62 669.25 N/A N/A N/A — — — N/A N/A N/A 186.66 373.31 746.61 Unit MHz 255/238 FEC Scaling MHz 238/255 FEC Scaling 255/237 FEC Scaling Minimum input frequency is in the 155 MHz range 237/255 FEC Scaling Minimum input frequency is in the 155 MHz range MHz MHz MHz Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. Rev. 2.3 7 Si5321 Table 3. AC Characteristics (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Input Clock Frequency (CLKIN) FEC[2:0] = 110 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN 66/64 FEC Scaling Minimum input frequency is in the 155 MHz range Input Clock Frequency (CLKIN) FEC[2:0] = 111 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 fCLKIN Input Clock Rise Time (CLKIN) tR Input Clock Fall Time (CLKIN) tF Input Clock Duty Cycle CLKOUT Frequency Range FRQSEL[2:0] = 001 FRQSEL[2:0] = 000 FRQSEL[2:0] = 100 FRQSEL[2:0] = 010 FRQSEL[2:0] = 101 FRQSEL[2:0] = 011 FRQSEL[2:0] = 110 FRQSEL[2:0] = 111 Min Typ Max N/A N/A N/A 150.79 301.58 603.16 N/A N/A N/A — — — N/A N/A N/A 168.22 336.44 672.88 N/A N/A N/A 160.36 320.72 641.46 N/A N/A N/A — — — N/A N/A N/A 178.90 357.80 715.59 Figure 2 — — 11 ns Figure 2 — — 11 ns CDUTY_IN 40 50 60 % fO_19 fO_39 fO_78 fO_155 fO_311 fO_622 fO_1250 fO_2500 19.436 38.872 77.744 155.48 310.97 621.95 1243.9 2487.8 — — — — — — — — 21.685 43.369 86.738 173.48 346.95 693.90 1387.8 2775.6 64/66 FEC Scaling Minimum input frequency is in the 155 MHz range Unit MHz MHz MHz CLKOUT Rise Time tR Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline — 190 220 ps CLKOUT Fall Time tF Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline — 185 205 ps Output Clock Duty Cycle CDUTY_OUT Differential: (CLKOUT+) – (CLKOUT–) 48 — 52 % RSTN/CAL Pulse Width tRSTN 20 — — ns Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. 8 Rev. 2.3 Si5321 Table 3. AC Characteristics (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Transitionless Period Required on CLKIN for Detecting a LOS Condition. INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 tLOS Figure 3 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 tVAL Min Typ /fo_622 /fo_622 12/ fo_622 10 /fo_622 9 /fo_622 8/ fo_622 — — — — — — 1.6 90 — — 24 16 Measured from when a valid reference clock is applied until the LOS flag clears Max Unit 32 /fo_622 /fo_622 32/ fo_622 32 /fo_622 32 /fo_622 32/ fo_622 32 3.2 220 s ms Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. Rev. 2.3 9 Si5321 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit f = 8 Hz 1000 — — ns f = 80 Hz 100 — — ns f = 800 Hz 10 — — ns 12 kHz to 20 MHz — 0.9 1.2 ps 50 kHz to 80 MHz — 0.27 0.35 ps 12 kHz to 20 MHz — 0.9 1.2 ps 50 kHz to 80 MHz — 0.27 0.35 ps 12 kHz to 20 MHz — 7.6 11 ps 50 kHz to 80 MHz — 3.6 10.0 ps 12 kHz to 20 MHz — 6.7 9.2 ps 50 kHz to 80 MHz — 3.0 10.0 ps Wander/Jitter at 800 Hz Bandwidth (BWSEL[1:0] = 10 and BWBOOST = 0) Jitter Tolerance (see Figure 7) JTOL(PP) CLKOUT RMS Jitter Generation FEC[2:0] = 000 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[2:0] = 001, 010, 100, 101, 110, 111 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 001, 010, 100, 101, 110, 111 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) FBW BW = 800 Hz — 800 — Hz JP < 800 Hz — 0.0 0.05 dB f = 16 Hz 500 — — ns f = 160 Hz 50 — — ns f = 1600 Hz 5 — — ns 12 kHz to 20 MHz — .80 1.0 ps 50 kHz to 80 MHz — .25 .30 ps 12 kHz to 20 MHz — 6.4 10.0 ps 50 kHz to 80 MHz — 3.0 5.0 ps FBW BW = 1600 Hz — 1600 — Hz JP < 1600 Hz — 0.0 0.05 dB Wander/Jitter Transfer Peaking Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 10 and BWBOOST = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. 10 Rev. 2.3 Si5321 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit JTOL(PP) f = 16 Hz 1000 — — ns f = 160 Hz 100 — — ns f = 1600 Hz 10 — — ns 12 kHz to 20 MHz — 0.8 1.2 ps 50 kHz to 80 MHz — 0.27 0.35 ps 12 kHz to 20 MHz, — 0.9 1.2 ps 50 kHz to 80 MHz, — 0.27 0.35 ps 12 kHz to 20 MHz, — 6.7 10.0 ps 50 kHz to 80 MHz, — 3.0 5.0 ps 12 kHz to 20 MHz, — 6.5 10.0 ps 50 kHz to 80 MHz, — 3.0 5.0 ps Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 01 and BWBOOST = 0) Jitter Tolerance (see Figure 9) CLKOUT RMS Jitter Generation FEC[2:0] = 000 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[2:0] = 001, 010, 100, 101, 110, 111 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 001, 010, 100, 101, 110, 111 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) FBW BW = 1600 Hz — 1600 — Hz JP < 1600 Hz — 0.0 0.1 dB f = 32 Hz 500 — — ns f = 320 Hz 50 — — ns f = 3200 Hz 5 — — ns 12 kHz to 20 MHz, — 0.8 1.0 ps 50 kHz to 80 MHz, — 0.25 0.3 ps 12 kHz to 20 MHz, — 6.1 10.0 ps 50 kHz to 80 MHz, — 3.0 5.0 ps BW = 3200 Hz — 3200 — Hz Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 01 and BWBOOST = 1) Jitter Tolerance (see figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 Jitter Transfer Bandwidth (see Figure 6) JGEN(RMS) JGEN(PP) FBW Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 11 Si5321 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter Transfer Peaking Symbol Test Condition Min Typ Max Unit JP < 3200 Hz — 0.05 0.1 dB JTOL(PP) f = 32 Hz 1000 — — ns f = 320 Hz 100 — — ns f = 3200 Hz 10 — — ns 12 kHz to 20 MHz — 0.9 1.1 ps 50 kHz to 80 MHz — 0.3 0.4 ps 12 kHz to 20 MHz — 0.85 1.1 ps 50 kHz to 80 MHz — 0.3 0.45 ps 12 kHz to 20 MHz — 7.1 10.0 ps 50 kHz to 80 MHz — 3.2 5.0 ps 12 kHz to 20 MHz — 6.6 11.0 ps 50 kHz to 80 MHz — 3.2 5.5 ps Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00 and BWBOOST= 0) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[2:0] = 001, 010, 100,101, 110, 111 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 001, 010, 100,101, 110, 111 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) FBW BW = 3200 Hz — 3200 — Hz JP < 3200 Hz — 0.05 0.1 dB f = 64 Hz 500 — — ns f = 640 Hz 50 — — ns f = 6400 Hz 5 — — ns 12 kHz to 20 MHz — 0.75 0.95 ps 50 kHz to 80 MHz — 0.27 0.35 ps 12 kHz to 20 MHz — 6.1 10.0 ps 50 kHz to 80 MHz — 3.1 5.0 ps FBW BW = 6400 Hz — 6400 — Hz JP < 6400 Hz — 0.05 0.1 dB Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 00 and BWBOOST = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. 12 Rev. 2.3 Si5321 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit JTOL(PP) f = 64 Hz 1000 — — ns f = 640 Hz 100 — — ns f = 6400 Hz 10 — — ns 12 kHz to 20 MHz — 1.0 1.3 ps 50 kHz to 80 MHz — 0.4 .55 ps 12 kHz to 20 MHz — 1.0 1.5 ps 50 kHz to 80 MHz — .45 0.7 ps 12 kHz to 20 MHz — 9.3 13.0 ps 50 kHz to 80 MHz — 4.1 6.0 ps 12 kHz to 20 MHz — 8.0 20.0 ps 50 kHz to 80 MHz — 4.0 7.5 ps Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 11 and BWBOOST = 0) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 JGEN(RMS) CLKOUT RMS Jitter Generation FEC[2:0] = 001, 010, 100,101, 110, 111 JGEN(RMS) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 JGEN(PP) CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 001, 010, 100,101, 110, 111 JGEN(PP) Jitter Transfer Bandwidth (see Figure 6) FBW BW = 6400 Hz — 6400 — Hz JP < 6400 Hz — 0.05 0.1 dB f = 128 Hz 500 — — ns f = 1280 Hz 50 — — ns f = 12800 Hz 5 — — ns 12 kHz to 20 MHz — .85 1.2 ps 50 kHz to 80 MHz — .35 .55 ps 12 kHz to 20 MHz — 6.8 11.0 ps 50 kHz to 80 MHz — 3.4 5.5 ps FBW BW = 12,800 Hz — 12800 — Hz JP < 12,800 Hz — 0.05 .1 dB TAQ RSTN/CAL high to CAL_ACTV low, with valid clock input and VALTIME = 0 — 300 350 ms Wander/Jitter Transfer Peaking Wander/Jitter at 12800 Hz Bandwidth (BWSEL[1:0] = 11 and BWBOOST = 1) Jitter Tolerance (see Figure 7) CLKOUT RMS Jitter Generation FEC[2:0] = 000 CLKOUT Peak-Peak Jitter Generation FEC[2:0] = 000 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Acquisition Time JGEN(RMS) JGEN(PP) Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 13 Si5321 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Clock Output Wander with Temperature Gradient 1,2 CCO_TG Stable Input Clock; Temperature Gradient