SI5323-B-GM

Si5323 P R E L I M I N A R Y D A TA S H E E T P I N -P R O G R A M M A B L E P R E C I S I O N C L O C K M U L T I P L I E R /J I T T E R A T T E N U A T O R Description The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Features Selectable output frequencies ranging from 8 kHz to 1050 MHz Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Dual clock inputs w/manual or automatically controlled hitless switching Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOL, LOS alarm outputs Pin-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Optical modules Test and measurement Xtal or Refclock CKIN1 CKOUT1 DSPLL CKIN2 ® Signal Format CKOUT2 Disable/BYPASS Loss of Signal Loss of Lock Signal Detect Control VDD (1.8, 2.5, or 3.3 V) GND Frequency Select Bandwidth Select Rate Select Manual/Auto Switch / Clock Select Latency Control Preliminary Rev. 0.2 3/07 Copyright © 2007 by Silicon Laboratories Si5323 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5323 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD Test Condition Min –40 2.97 2.25 1.62 Typ 25 3.3 2.5 1.8 251 Max 85 3.63 2.75 1.98 279 Unit ºC V V V mA Supply Current IDD fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output CKOUT2 disabled fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output CKOUT2 disabled Tristate/Sleep Mode — — 217 204 243 234 mA mA — 0.008 0.008 194 TBD — — 220 TBD 707.35 1049.76 mA mA MHz MHz Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2) CKF CKOF Input frequency and clock multiplication ratio pin-selectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing for table selections. Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8V ±10% 2.5V ±10% 3.3V ±10% Rise/Fall Time Duty Cycle CKNTRF CKNDC 20–80% Whichever is less 0.25 0.9 1.0 1.1 — 40 50 Output Clocks (CKOUT1, CKOUT2) Common Mode Differential Output Swing Single Ended Output Swing VOCM VOD VSE LVPECL 100 Ω load line-to-line VDD – 1.42 1.1 0.5 — — — VDD – 1.25 1.9 0.93 V V V — — — — — — — 1.9 1.4 1.7 1.95 11 60 — VPP V V V ns % ns Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.2 S i5323 Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Rise/Fall Time Duty Cycle PLL Performance Jitter Generation Symbol CKOTRF CKODC JGEN Test Condition 20–80% Min — 45 Typ 230 — 0.3 Max 350 55 TBD Unit ps % ps rms fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz — — — — 0.3 0.05 TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD TBD ps rms dB dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Jitter Transfer External Reference Jitter Transfer Phase Noise JPK JPKEXTN CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset — — — — — — — Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air θJA — 38 — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 3.6 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V C C kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.2 3 S i5323 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Preliminary Rev. 0.2 S i5323 Figure 2. Si5323 Typical Application Circuit Preliminary Rev. 0.2 5 S i5323 1. Functional Description The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequencymultiplied clock outputs ranging from 8 kHz to 1050 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5323 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to look up valid Si5323 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5323 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5323 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5323 supports hitless switching between the two input clocks in compliance with GR-253-CORE and GR1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (