SI5326A-B-GM

P R E L I M I N A R Y D A TA S H E E T Si5326 ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Description The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Dual clock inputs w/manual or automatically controlled hitless switching Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable On-chip voltage regulator for 1.8, 2.5, or 3.3 V ±10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Optical modules Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement Xtal or Refclock CKIN1 ÷ N31 ÷ NC1 CKOUT1 ® CKIN2 ÷ N32 DSPLL ÷ NC2 ÷ N2 Loss of Signal/ Frequency Offset Loss of Lock CKOUT2 Signal Detect Control VDD (1.8, 2.5, or 3.3 V) GND I2C/SPI Port Device Interrupt Rate Select Clock Select Latency Control Confidential Rev. 0.2 2/07 Copyright © 2007 by Silicon Laboratories Si5326 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5326 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD Test Condition Min –40 2.97 2.25 1.62 Typ 25 3.3 2.5 1.8 251 Max 85 3.63 2.75 1.98 279 Unit ºC V V V mA Supply Current IDD fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output CKOUT2 disabled fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output CKOUT2 disabled Tristate/Sleep Mode — — — 217 204 243 234 mA mA — — 0.002 0.002 970 1213 194 TBD — — 220 TBD 710 945 1134 1417 mA mA MHz MHz Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2) CKF CKOF Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8 V ±10% 2.5 V ±10% 3.3 V ±10% Rise/Fall Time Duty Cycle CKNTRF CKNDC 20–80% Whichever is less 0.25 0.9 1.0 1.1 — 40 50 Output Clocks (CKOUT1, CKOUT2) Common Mode Differential Output Swing Single Ended Output Swing Rise/Fall Time VOCM VOD VSE CKOTRF LVPECL 100 Ω load line-to-line VDD – 1.42 1.1 0.5 — — — — 230 VDD – 1.25 1.9 0.93 350 V ps V — — — — — — — 1.9 1.4 1.7 1.95 11 60 — VPP V V V ns % ns 20–80% Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Confidential Rev. 0.2 S i5326 Table 1. Performance Specifications (Continued) (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Duty Cycle PLL Performance Jitter Generation Symbol CKODC JGEN Test Condition Min 45 Typ — 0.3 Max 55 TBD Unit % ps rms fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz 800 Hz–80 MHz — — — — — 0.3 TBD 0.05 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD TBD ps rms ps rms dB dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Jitter Transfer External Reference Jitter Transfer Phase Noise JPK JPKEXTN CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset — — — — — — — Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air Theta JA — TBD — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 3.6 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V ºC ºC kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Confidential Rev. 0.2 3 S i5326 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Confidential Rev. 0.2 S i5326 Figure 2. Si5326 Typical Application Circuit (I2C Control Mode) Figure 3. Si5326 Typical Application Circuit (SPI Control Mode) Confidential Rev. 0.2 5 S i5326 1. Functional Description The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5326 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5326 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from www.silabs.com/timing. The Si5326 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5326 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5326 supports hitless switching between the two input clocks in compliance with GR-253-CORE and GR1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (