SI53303-B-GM

Si5330x Data Sheet Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz The Si5330x family of Universal/Any-format fanout buffers is ideal for clock distribution (1 MHz minimum) and redundant clocking applications. These devices feature typical ultra-low jitter characteristics of 50 fs and operate over a wide frequency range. Built-in LDOs deliver high PSRR performance and reduce the need for external components, simplifying low-jitter clock distribution in noisy environments. The Si5330x family is available in multiple configurations, with some versions offering a selectable input clock using a 2:1 input mux. Other features include independent (synchronous) output enable, glitchless switching, LOS monitor of input clocks, output clock division, and built-in format translation. These buffers can be paired with the Si534x clocks and jitter attenuators, the Si5332 clocks, and the Si5xx oscillators to deliver endto-end clock tree performance. KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 Input Mux operation • Synchronous output enable • Loss of signal (LOS) monitors for loss of input clock • Output clock division: /1, /2, /4 • RoHS compliant, Pb-free • Temperature range: –40 to +85 °C silabs.com | Building a more connected world. Rev. 1.0 Si5330x Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Product Family Overview Part Number Description Input MUX Input Output Glitchless Switch1 LOS Output OE Option Synchronous OE1 Clk Divider Option Si53301-B-GM 6 output universal buffer with 2:1 input mux Yes 2 6 Diff / 12 SE Yes Yes Per Bank Yes Per Bank Si53302-B-GM 10 output universal buffer with 2:1 input mux Yes 2 10 Diff / 20 SE Yes Yes Per Bank Yes Per Bank Si53303-B-GM Dual 1:5 universal buffer No 2 5 Diff / 10 SE No No Per Bank Yes Per Bank Si53304-B-GM 6 output universal buffer with 2:1 input mux Yes 2 6 Diff / 12 SE Yes No Individual Yes No Si53305-B-GM 10 output universal buffer with 2:1 input mux Yes 2 10 Diff / 20 SE Yes No Individual Yes No Si53306-B-GM 4 output universal buffer, single input No 1 4 Diff / 8 SE No No Single Yes No Si53307-B-GM 2 output universal buffer with 2:1 input mux Yes 2 2 Diff / 4 SE Yes No Single Yes No Si53308-B-GM Dual 1:3 universal buffer No 2 3 Diff / 6 SE No Yes Per Bank Yes Per Bank Note: 1. The synchronous features (Glitch-less switching and Synchronous OE) of the Si533xx family require a minimum input clock frequency of 1 MHz. If the selected input clock stops, pauses, or is gapped such that the 1 MHz minimum is not met for any time interval, then the output clock(s) will be disabled (turned off). Once the paused input clock restarts, the output clock may NOT start up immediately. Output start-up (turning back on) may be delayed for several input clock cycles until the internal synchronizer determines the input clock is once again valid. 2. Click on the part number above to see a block diagram for each corresponding part number. Table 1.2. Si5330x Ordering Guide Part Number Package Pb-Free, ROHS-6 Temperature Si53301-B-GM1 32-QFN Yes –40 to 85 °C Si53302-B-GM1 44-QFN Yes –40 to 85 °C Si53303-B-GM1 44-QFN Yes –40 to 85 °C Si53304-B-GM1 32-QFN Yes –40 to 85 °C Si53305-B-GM1 44-QFN Yes –40 to 85 °C Si53306-B-GM1 16-QFN Yes –40 to 85 °C Si53307-B-GM1 16-QFN Yes –40 to 85 °C Si53308-B-GM1 32-QFN Yes –40 to 85 °C Si53301/4-EVB Evaluation Board — — Note: 1. Add an "R" at the end of the OPN to denote tape and reel ordering options. silabs.com | Building a more connected world. Rev. 1.0 | 2 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Universal, Any-Format Input Termination . . . . . . . . . . . . . . . . . . . . . 5 2.2 Internal Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Input Mux (Si53301/02/04/05/07 Only) . . . . . . . . . . . . . . . . . . . . . .10 2.6 Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . .10 2.7 Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . .10 2.8 Loss of Signal (LOS) Indicator . . . . . . . . . . . . . . . . . . . . . . . . .11 2.9 Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . .11 2.10 Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . .11 2.11 Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . .12 2.12 LVCMOS Output Termination to Support 1.5 V and 1.2 V . . . . . . . . . . . . . . .14 2.13 AC Timing Waveforms . . . . . . . . . . . . . . . .14 2.14 Typical Phase Noise Performance (Differential Input Clock) . . . . . . . . . . . . . .15 2.15 Typical Phase Noise Performance (Single-Ended Input Clock) . . . . . . . . . . . . .17 2.16 Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.17 Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . .18 3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 Si53301 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .35 5.2 Si53302 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.3 Si53303 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.4 Si53304 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5 Si53305 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.6 Si53306 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .51 5.7 Si53307 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.8 Si53308 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .55 6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1 16-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.2 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.3 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .60 7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 silabs.com | Building a more connected world. Rev. 1.0 | 3 7.1 16-QFN Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.2 32-QFN Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . .62 7.3 44-QFN Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.1 Si53301/04/08 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . .64 8.2 Si53302/03/05 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . .65 8.3 Si53306/07 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . .66 9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 silabs.com | Building a more connected world. Rev. 1.0 | 4 Si5330x Data Sheet Functional Description 2. Functional Description The Si5330x family of low-jitter, low-skew, universal/any-format buffers accepts most common differential or LVCMOS input signals. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations). 2.1 Universal, Any-Format Input Termination The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. The simplified tables below summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for singleended formats. See AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance for more information. Table 2.1. AC-Coupled Clock Input Options Clock Format 1.8 V 2.5/3.3 V LVPECL/Low-power LVPECL N/A Yes LVCMOS No Yes LVDS Yes Yes HCSL No Yes CML Yes Yes Table 2.2. DC-Coupled Clock Input Options Clock Format 1.8 V 2.5/3.3 V LVPECL/Low-power LVPECL N/A Yes LVCMOS No Yes LVDS No Yes HCSL No Yes CML No No silabs.com | Building a more connected world. Rev. 1.0 | 5 Si5330x Data Sheet Functional Description VDD 0.1 µF Si5330x CLKx 100 CLKxb 0.1 µF Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination VDD VDD = 3.3 V or 2.5 V CMOS Driver VDD 1k Si5330x CLKx 50 CLKxb Rs VTERM = VDD/2 1k Note: Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace. Figure 2.2. DC-Coupled, Single-Ended (LVCMOS) Input Termination VDD VDD 1k VBIAS = VDD/2 VDD = 3.3 V or 2.5 V CMOS Driver VDD 1k Si5330x CLKx 50 CLKxb Rs 1k Notes: 1. Assumes all VDDs are at the same level. 2. Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace. 1k VTERM = VDD/2 Figure 2.3. AC-Coupled, Single-Ended (LVCMOS) Input Termination silabs.com | Building a more connected world. Rev. 1.0 | 6 Si5330x Data Sheet Functional Description VDD DC Coupled LVPECL Input Termination Scheme 1 R1 VDD R1 VDD = 3.3 V or 2.5 V Si5330x CLKx 50 “Standard” LVPECL Driver CLKxb 50 R2 VTERM = VDD – 2V R1 // R2 = 50 Ohm R2 3.3 V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5 V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Input Termination Scheme 2 VTERM = VDD – 2 V VDD 50 VDD = 3.3 V or 2.5 V 50 Si5330x 50 “Standard” LVPECL Driver CLKx CLKxb 50 DC Coupled LVDS Input Termination VDD VDD = 3.3 V or 2.5 V Si5330x CLKx 50 Standard LVDS Driver 100 CLKxb 50 DC Coupled HCSL Input Termination VDD = 3.3 V or 2.5 V VDD 33 Si5330x 50 Standard HCSL Driver CLKx CLKxb 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 2.4. Differential DC-Coupled Input Terminations silabs.com | Building a more connected world. Rev. 1.0 | 7 Si5330x Data Sheet Functional Description Table 2.3. AC/DC-Coupled Clock Input Requirements for Glitchless, Non-Continuous Clocks1, 2, 3 Input Clock Driver Stop State Clock Input Type Low High High-Z DC-Coupled Yes Yes No AC-Coupled Yes No No Note: 1. "Non-continuous clocks” means any clock that can be stopped, disabled, or gapped. 2. “Yes” means this configuration is supported. 3. “No” indicates that the configuration is not supported. Operating under a "No" condition can result in erroneous clock outputs and/or erroneous LOS indications. Operating the device in unsupported configurations is not recommended. 2.2 Internal Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The clock input should not be actively driven when power is not applied to the device. The non-inverting input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to VDD. The inverting input is biased with a 75 kΩ pull-up to VDD. VDD Si5330x RPU CLK0 or CLK1 RPD RPU + – RPU = 75 k RPD = 18.75 k Figure 2.5. Internal Input Bias Resistors silabs.com | Building a more connected world. Rev. 1.0 | 8 Si5330x Data Sheet Functional Description 2.3 Voltage Reference (VREF) The VREF pin can be used to bias the input receiver, as shown in the figure below, when a single-ended input clock (such as LVCMOS) is used. Note that VREF = VDD/2 and should be compatible with the Vcm rating of the single-ended input clock driving the CLK0 or CLK1 inputs. To optimize jitter and duty cycle performance, use the circuit in Figure 2.3 AC-Coupled, Single-Ended (LVCMOS) Input Termination on page 6. VREF pin should be left floating when differential clocks are used. VDDO = 3.3V , 2.5V Si5330x Rs CMOS Driver CLKx 50 CLKxb VREF 100 nF Figure 2.6. Using Voltage Reference with Single-Ended Input Clock 2.4 Universal, Any-Format Output Buffer The highly flexible output drivers support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUTx[1] and SFOUTx[0] are 3-level inputs that can be pinstrapped to select the Bank A and Bank B clock signal formats independently. This feature enables the device to be used for format/level translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 2.4. Output Signal Format Selection SFOUTx[1] SFOUTx[0] VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open1 Open1 LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open1 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open1 1 LVPECL Low power LVPECL Low power N/A 0 Open1 CML CML CML 1 Open1 HCSL HCSL N/A Note: 1. SFOUTx[1:0] are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is internally biased to VDD/2. silabs.com | Building a more connected world. Rev. 1.0 | 9 Si5330x Data Sheet Functional Description 2.5 Input Mux (Si53301/02/04/05/07 Only) The Si53301/02/04/05/07 provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input and has an internal pulldown resistor. The following table summarizes the input and output clock based on the input mux pin settings. Table 2.5. Input Mux Logic CLK_SEL CLK0 CLK1 Q1 Qb L L X L H L H X H L H X L L H H X H H L Note: 1. On the next negative transition of CLK0 or CLK1. 2.6 Glitchless Clock Input Switching The Si53301/2/4/5/7 feature glitchless switching between two valid input clocks. The following figure illustrates that switching between input clocks does not generate runt pulses or glitches at the output. CLK1 CLK0 CLK_SEL Note 1 Note 2 Note 3 Qn Notes: 1. Qn continues with CLK0 for 2-3 falling edges of CLK0. 2. Qn is disabled low for 2-3 falling edges of CLK1 . 3. Qn starts on the first rising edge after 1 + 2. Figure 2.7. Glitchless Input Clock Switch The Si53301/2/4/5/7 support glitchless switching between clock inputs with a frequency variance up to 10x. When a switchover to a new clock is made, the output will disable low after two or three clock cycles of the previously selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. If a switchover to an absent clock is made, the output will glitchlessly stop low and wait for edges of the newly-selected clock. A switchover from an absent clock to a live clock will also be glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input clock. 2.7 Synchronous Output Enable The Si5330x features a synchronous output enable (disable) feature. The output enable pin is sampled and synchronized to the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are enabled or disabled. When OE is low, Q is held low and Qb is held high for differential output formats. For LVCMOS output format options, both Q and Qb are held low when OE is set low. The output enable pin has an internal pull-up that enables the outputs when left unconnected. See Table 3.10 AC Characteristics on page 23 for output enable and output disable times. silabs.com | Building a more connected world. Rev. 1.0 | 10 Si5330x Data Sheet Functional Description 2.8 Loss of Signal (LOS) Indicator Si53301/2/8 feature a Loss of Signal (LOS) indicator. The LOS0 and LOS1 indicators are used to check for the presence of input clocks CLK0 and CLK1. The LOS0 and LOS1 pins must be checked prior to selecting the clock input or should be polled to check for the presence of the currently selected input clock. In the event that an input clock is not present, the associated LOSx pin will assume a logic high (LOSx = 1) state. When a clock is present at the associated input clock pin, the LOSx pin will assume a logic low (LOSx = 0) state. 2.9 Flexible Output Divider The Si53301/02/03/08 provide optional clock division in addition to clock distribution. The divider setting for each bank of output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVx pins open will force a divider value of 1, which is the default mode of operation. Table 2.6. Divider Selection DIVx1 Divider Value Open ÷1 (default) 0 ÷2 1 ÷4 Notes: 1. DIVx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is internally biased to VDD/2. 2.10 Power Supply (VDD and VDDOX) The device includes separate core (VDD) and output driver supplies (VDDOX). This feature allows the core to operate at a lower voltage than V DDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3, 2.5, or 1.8 V. Control signals, such as CLK_SEL, DIV, and OE, are in the VDD domain. Each output bank has its own VDDOX supply, supporting 3.3, 2.5, or 1.8 V. silabs.com | Building a more connected world. Rev. 1.0 | 11 Si5330x Data Sheet Functional Description 2.11 Output Clock Termination Options The recommended output clock termination options for ac and dc are shown below. Unused outputs should be left unconnected. AC-Coupled LVPECL Output Termination Scheme 1 VDD R1 VDDOX Si5330x R1 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qb 50 0.1 uF Rb R2 Rb 3.3 V LVPECL: R1 = 82.5 ; R2 = 127 ; Rb = 120 2.5 V LVPECL: R1 = 62.5 ; R2 = 250 ; Rb = 90 VBIAS = VDD – 1.3 V R1 // R2 = 50 R2 AC-Coupled LVPECL Output Termination Scheme 2 VDDOX Si5330x 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qb 50 Rb 0.1 uF 50 Rb 50 VBIAS = VDD – 1.3 V 3.3 V LVPECL: Rb = 120 2.5 V LVPECL: Rb = 90 DC-Coupled LVPECL Output Termination Scheme 1 Note: VDDOX = VDDOA or VDDOB = 3.3 V, 2.5 V VDDO R1 R1 VDDOX Si5330x VDD = VDDOX Q 50 LVPECL Receiver Qb 50 R2 3.3 V LVPECL: R1 = 127 2.5 V LVPECL: R1 = 250 VTERM = VDDO – 2 V R1 // R2 = 50 R2 ; R2 = 82.5 ; R2 = 62.5 DC-Coupled LVPECL Output Termination Scheme 2 Note: VDDOX = VDDOA or VDDOB = 3.3 V, 2.5 V VDDOX Si5330x VDD = VDDOX Q 50 LVPECL Receiver Qb 50 50 50 VTERM = VDDO – 2 V Figure 2.8. LVPECL AC and DC Output Terminations silabs.com | Building a more connected world. Rev. 1.0 | 12 Si5330x Data Sheet Functional Description DC Coupled LVDS and Low-Power LVPECL Termination VDDOX = 3.3 V or 2.5 V, or 1.8 V (LVDS only) Si5330x VDD 50 Q Standard LVDS Receiver 100 Qn 50 AC Coupled LVDS and Low-Power LVPECL Termination VDDOX = 3.3 V or 2.5 V or 1.8 V (LVDS only) Si5330x 0.1 uF VDD 50 Q Standard LVDS Receiver 100 Qn 50 0.1 uF AC Coupled CML Termination VDDOX = 3.3V or 2.5V or 1.8V Si5330x 0.1 uF VDD 50 Q Standard CML Receiver 100 Qn 50 0.1 uF DC Coupled HCSL Receiver Termination VDDOX = 3.3 V or 2.5 V Si5330x VDD (3.3 V or 2.5 V only) 50 Q Standard HCSL Receiver Qn 50 50 50 DC Coupled HCSL Source Termination VDDO = 3.3V Si5330x VDD 42.2 50 Q Qn Standard HCSL Receiver 42.2 50 86.6 86.6 Figure 2.9. LVDS, CML, HCSL, and Low-Power LVPECL Output Terminations CMOS Receivers Si5330x CMOS Driver Zo Rs Zout 50 Figure 2.10. LVCMOS Output Termination Table 2.7. Recommended LVCMOS RS Series Termination SFOUTX[1] 0 SFOUTX[0] 1 silabs.com | Building a more connected world. RS (Ω) 3.3 V 2.5 V 1.8 V 33 33 33 Rev. 1.0 | 13 Si5330x Data Sheet Functional Description SFOUTX[1] SFOUTX[0] RS (Ω) 1 0 33 33 33 1 1 33 33 0 Open 0 0 0 0 2.12 LVCMOS Output Termination to Support 1.5 V and 1.2 V LVCMOS clock outputs are natively supported at 1.8, 2.5, and 3.3 V. However, 1.2 V and 1.5 V LVCMOS clock outputs can be supported via a simple resistor divider network that will translate the buffer’s 1.8 V output to a lower voltage as shown in the following figure. R1 VDDO = 1.8 V 50 R2 1.5V LVCMOS: R1 = 43 1.2V LVCMOS: R1 = 58 , R2 = 300 , R2 = 150 , IOUT = 12 mA , IOUT = 12 mA R1 LVCMOS 50 R2 Figure 2.11. 1.5 V and 1.2 V LVCMOS Low-Voltage Output Termination 2.13 AC Timing Waveforms TPHL CLK TSK QN VPP/2 Q VPP/2 VPP/2 QM VPP/2 TPLH TSK Propagation Delay Q Output-Output Skew 80% VPP 20% VPP Q TF 80% VPP 20% VPP TR Rise/Fall Time Figure 2.12. AC-Coupled Timing Waveforms silabs.com | Building a more connected world. Rev. 1.0 | 14 Si5330x Data Sheet Functional Description 2.14 Typical Phase Noise Performance (Differential Input Clock) Each of the phase noise plots superimposes Source Jitter, Total SE Jitter, and Total Diff Jitter on the same diagram. • Source Jitter—Reference clock phase noise (measured Single-ended to PNA). • Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. • Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more information, see 3. Electrical Specifications. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). PSPL 5310A CLK SYNTH SMA103A PSPL 5310A CLKx 50 Si5330x Balun AG E5052 Phase Noise Analyzer 50ohm CLKxb 50 Balun Figure 2.13. Differential Measurement Method Using a Balun Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 156.25 1.0 38.2 147.8 142.8 118.3 112.0 Figure 2.14. Total Jitter Differential Input (156.25 MHz) silabs.com | Building a more connected world. Rev. 1.0 | 15 Si5330x Data Sheet Functional Description Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 312.5 1.0 33.10 94.39 88.39 83.80 76.99 Figure 2.15. Total Jitter Differential Input (312.5 MHz) Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 625 1.0 23 57 52 59 54 Figure 2.16. Total Jitter Differential Input (625 MHz) silabs.com | Building a more connected world. Rev. 1.0 | 16 Si5330x Data Sheet Functional Description 2.15 Typical Phase Noise Performance (Single-Ended Input Clock) For single-ended phase noise measurements, the phase noise analyzer was connected directly without the use of a balun. The following figure shows three phase noise plots superimposed on the same diagram. Frequency (MHz) Single-Ended Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 156.25 1.0 40.74 182.12 177.51 125.22 118.41 Figure 2.17. Total Jitter Single-Ended Input (156.25 MHz) silabs.com | Building a more connected world. Rev. 1.0 | 17 Si5330x Data Sheet Functional Description 2.16 Input Mux Noise Isolation The input clock mux is designed to minimize crosstalk between CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation. Figure 2.18. Input Mux Noise Isolation (Differential Input Clock, 44-QFN Package) Figure 2.19. Input Mux Noise Isolation (Single-Ended Input Clock, 44-QFN Package) 2.17 Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. See AN491: Power Supply Rejection for Low-Jitter Clocks for more information. silabs.com | Building a more connected world. Rev. 1.0 | 18 Si5330x Data Sheet Electrical Specifications 3. Electrical Specifications Table 3.1. Recommended Operating Conditions Parameter Symbol Ambient Operating Temperature TA Test Condition Min Typ Max Unit –40 — 85 °C 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V LVDS, CML Supply Voltage Range1 VDD LVDS, CML, LVCMOS Output Buffer Supply Voltage1 VDDOX Note: 1. Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD = 1.8 V but is supported for LVCMOS clock output for VDDOX = 1.8 V. LVCMOS outputs at 1.5 V and 1.2 V can be supported via a simple resistor divider network. 2. See 2.12 LVCMOS Output Termination to Support 1.5 V and 1.2 V. Table 3.2. Input Clock Specifications (VDD=1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, TA= –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V ± 5%, 3.3 V ± 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V ± 5%, 3.3 V ± 10% VDD × 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V ± 5%, 3.3 V ± 10% — — VDD × 0.3 V Input Capacitance CIN CLK0 and CLK1 pins with respect to GND — 5 — pF silabs.com | Building a more connected world. Rev. 1.0 | 19 Si5330x Data Sheet Electrical Specifications Table 3.3. DC Common Characteristics (VDD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Supply Current Symbol IDDOX @ 200MHz (CMOS) Voltage Reference Input High Voltage Input Mid Voltage Input Low Voltage Min Typ Max Unit — 65 100 mA LVPECL (3.3 V) Si53301/2/3/4/5/6/8 — 35 — mA LVPECL (3.3 V) Si53307 — 40 — mA Low Power LVPECL (3.3 V) Si53301/2/4/5/6/7/8 — 35 — mA Low Power LVPECL (3.3 V) Si53303 — 30 — mA LVDS (3.3 V) — 20 — mA CML (3.3V), Si53301/4/8 — 35 — mA CML (3.3V), Si53302/3/5 — 30 — mA CML (3.3V), Si53306 — 40 — mA CML (3.3V), Si53307 — 60 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 5 — mA CMOS (2.5 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 8 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz Si53306/7 — 20 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz Si53301/2/3/4/5/8 — 15 — mA VREF pin, IREF = ±500 µA — VDD/2 — V SFOUTx, DIVx, CLK_SEL, OEx Si53303 0.85 × VDD — — V SFOUTx, DIVx, CLK_SEL, OEx Si53301/2/4/5/6/7/8 0.8 × VDD — — V SFOUTx, DIVx 3-level input pins 0.45 × VDD 0.5 × VDD 0.55 × VDD V SFOUTx, DIVx, CLK_SEL, OEx Si53301/2/4/5/6/7/8 — — 0.2 × VDD V SFOUTx, DIVx, CLK_SEL, OEx Si53303 — — 0.15 × VDD V IDD Output Buffer Supply Current (Per Clock Output) @ 100 MHz (differential) Test Condition VREF VIH VIM VIL Output Voltage High (LOSx) VOH IDD = –1 mA 0.8 x VDD — — V Output Voltage Low (LOSx) VOL IDD = 1 mA — — 0.2 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL, DIVx, SFOUTx, — 25 — kΩ silabs.com | Building a more connected world. Rev. 1.0 | 20 Si5330x Data Sheet Electrical Specifications Parameter Internal Pull-up Resistor Symbol Test Condition Min Typ Max Unit RUP OEx, DIVx, SFOUTx — 25 — kΩ Table 3.4. Output Characteristics (LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output DC Common Mode Voltage VCOM VDDOX – 1.595 — VDDOX – 1.245 V Single-Ended Output Swing VSE 0.55 0.80 1.050 V Typ Max Unit VDDOX – 1.275 V 0.85 V Note: 1. Unused outputs can be left floating. Do not short unused outputs to ground. Table 3.5. Output Characteristics (Low Power LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Output DC Common Mode Voltage VCOM RL = 100 Ω across Qn and Qn VDDOX – 1.895 Single-Ended Output Swing VSE RL = 100 Ω across Qn and Qn 0.25 0.60 Table 3.6. Output Characteristics (CML) (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Single-Ended Output Swing Symbol Test Condition Min Typ Max Unit VSE Terminated as shown in Figure 2.9 LVDS, CML, HCSL, and LowPower LVPECL Output Terminations on page 13 (CML termination). 300 400 550 mV silabs.com | Building a more connected world. Rev. 1.0 | 21 Si5330x Data Sheet Electrical Specifications Table 3.7. Output Characteristics (LVDS) (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, TA = –40 to 85 °C) Parameter Symbol Output Common Mode Voltage (VDDO = 1.8 V) Min Typ Max Unit RL = 100 Ω across QN and QN Si53301/2/4/5/6/7/8 247 — 490 mV RL = 100 Ω across QN and QN Si53303 247 — 454 mV VDDOX = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 Ω across QN and QN 1.10 1.25 1.35 V VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QN and QN Si53301/2/4/5/6/7/8 0.85 0.97 1.25 V VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QNand QN Si53303 0.85 0.97 1.1 V VSE Single-Ended Output Swing Output Common Mode Voltage (VDDO = 2.5 V or 3.3V) Test Condition VCOM1 VCOM2 Table 3.8. Output Characteristics (LVCMOS) (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output Voltage High VOH Output Voltage Low VOL Test Condition Min Typ Max Unit Si53301/2/4/5/6/7/8 0.75 × VDDOX — — V Si53303 0.8 × VDDOX — — V Si53301/2/4/5/6/7/8 — — 0.25 × VDDOX V Si53303 — — 0.2 × VDDOX V Note: 1. IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTx settings. Table 3.9. Output Characteristics (HCSL) (VDDOX = 2.5 V ± 5% or 3.3 V ± 10%, TA = –40 to 85 °C)) Parameter Output Voltage High Symbol VOH Test Condition Min Typ Max Unit RL = 50 Ω to GND Si53301/2/3/4/5/6/8 550 700 900 mV RL = 50 Ω to GND Si53307 550 700 850 mV Output Voltage Low VOL RL = 50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 Ω to GND 550 700 850 mV Crossing Voltage VC RL = 50 Ω to GND 250 350 550 mV silabs.com | Building a more connected world. Rev. 1.0 | 22 Si5330x Data Sheet Electrical Specifications Table 3.10. AC Characteristics (VDD = VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol LOSx Clear Time TLOSCLR LOSx Activation Time TLOSACT Frequency Duty Cycle6 Minimum Input Clock Slew Rate5 Output Rise/Fall Time Minimum Input Pulse Width Propagation Delay F DC SR TR/TF Test Condition Min Typ Max Unit F < 100 MHz — TPER + 15 — ns F > 100 MHz — 25 — ns — 15 — µs LVPECL, low power LVPECL, LVDS, CML, HCSL1 1 — 725 MHz LVCMOS 1 — 200 MHz 200 MHz, 20/80% TR/TF