Si5332-AM Automotive Grade Clock
Generator with SmartClock™ Technology
AEC-Q100 Qualified, Any-Frequency Clock Generator
KEY FEATURES
Based on Skyworks' proprietary MultiSynth™ flexible frequency synthesis technology,
the automotive grade Si5332-AM generates any combination of output frequencies
with excellent jitter performance (190 fs rms). The device's highly flexible architecture
enables a single device to generate a wide range of integer and non-integer related frequencies on up to 12 differential clock outputs with 0 ppm frequency synthesis error. The
device offers multiple banks of outputs that can each be tied to independent voltages,
enabling usage in mixed-supply applications. Further, the signal format of each clock
output is user-configurable. Given its frequency, format, and supply voltage flexibility, the
Si5332-AM is ideally suited to replace multiple clock ICs and oscillators with a single
device.
The Si5332-AM comes equipped with SmartClock™ technology, providing the capability
of monitoring the health of reference inputs, detecting faults, communicating faults to a
system safety manager, and, with external control, switching over to a redundant backup
source in the event of a fault. In the event of primary and redundant input reference
failure, AlwaysOn mode allows the output clocks to continue operating within ±5% of the
desired output frequency.
The Si5332-AM is quickly and easily configured using ClockBuilder Pro™ software.
ClockBuilder Pro assigns a custom part number for each unique configuration. Devices
ordered with custom part numbers are factory-programmed free of charge, making it
easy to get a custom clock uniquely tailored for each application. Using the Si5332-AM's
I2C interface, the device may be user-configured at power-up or NVM programmed
using the ClockBuilder Pro Field Programmer.
• Any-Frequency 6/8/12-output
programmable clock generators
• AEC-Q100 qualified
• AEC-Q006 qualified
• Automotive Grade 2: –40 to +105 °C
• SmartClock health monitoring and fault
detection features
• Offered in three different package sizes,
supporting different combinations of output
clocks and user configurable hardware
input pins
• 32-pin QFN, up to 6 outputs
• 40-pin QFN, up to 8 outputs
• 48-pin QFN, up to 12 outputs
• MultiSynth technology enables anyfrequency synthesis on any output up to
250 MHz
• Integer dividers up to 333.33 MHz
• Highly configurable output path featuring a
cross point mux
• Up to three independent fractional
synthesis output paths
• Up to five independent integer dividers
• Input frequency range:
• External crystal: 16 to 50 MHz
Applications:
• Differential clock: 10 to 250 MHz
• ADAS ECUs
• Automotive Networking/Gateways
• Digital Cockpit/IVI
• Lidar/Radar Sensors
• Automated Driving ECUs
• Camera/Vision Systems
• LVCMOS clock: 10 to 170 MHz
• Output frequency range:
• Differential: 5 to 333.33 MHz
• LVCMOS: 5 to 170 MHz
• PCIe Gen 1/2/3/4/5 compliant
• User-configurable clock output signal
format per output: LVDS, LVPECL, HCSL,
LVCMOS
• Down and center spread spectrum
• RoHS-6 compliant
• Si5332-AM1/2/3 Family Reference Manual
1
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1
Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Features List
1. Features List
• Any-Frequency 6/8/12-output programmable clock generators
• Offered in three different package sizes, supporting different
combinations of output clocks and user configurable hardware
input pins
• 32-pin QFN, up to 6 outputs
• 40-pin QFN, up to 8 outputs
• 48-pin QFN, up to 12 outputs
• MultiSynth technology enables any-frequency synthesis on any
output up to 250 MHz
• Integer output frequencies up to 333.33 MHz
• Highly configurable output path featuring a cross point mux
• Two independent fractional synthesis output paths
• Up to five independent integer dividers
• Input frequency range:
• External crystal: 16 to 50 MHz
• Differential clock: 10 to 250 MHz
• LVCMOS clock: 10 to 170 MHz
• Output frequency range:
• Differential: 5 to 333.33 MHz
• LVCMOS: 5 to 170 MHz
• SmarClock health monitoring and fault detection capability of
input sources
• Primary and redundant input reference sources
• AlwaysOn sources clock outputs within +/-5% if primary/secondary sources fault
2
• User-configurable clock output signal format per output: LVDS,
LVPECL, HCSL, LVCMOS
• 190 fs RMS phase jitter
• PCIe Gen1/2/3/4/5, common clocks, and SRIS compliant
• 1.8 V, 2.5 V, 3.3 V core VDD
• Adjustable output-output delay
• Independent glitchless on-the-fly output frequency changes
• Very low power consumption
• Independent output supply pins for each bank of outputs:
• 1.8 V, 2.5 V, or 3.3 V differential
• 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS
• Programmable spread spectrum
• Down and center spread from 0.1% to 2.5% in 0.01% steps
from 30 kHz to 33 kHz
• Integrated power supply filtering
• Serial interface: I2C
• ClockBuilder Pro software utility simplifies device configuration
and assigns custom part numbers
• AEC-Q100 qualified
• AEC-Q006 qualified
• Automotive grade 2 temperature range: –40 to +105 °C
• RoHS-6 compliant
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 16, 2021
2
Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Ordering Guide
2. Ordering Guide
In-System Programmable Devices
Si5332X - D - AMpR
Operating Temp Range: -40 to +105 ﾰC
AM = Automotive grade, QFN, ROHS6, Pb-free
p = 1 for 6-output, 32-pin QFN
2 for 8-output, 40-pin QFN
3 for 12-output, 48-pin QFN
R = Tape & Reel (ordering option)
D = Product Revision
Ordering Part
Number
Si5332A
Si5332B
Si5332C
Si5332D
Frequency Synthesis Mode
Integer and Fractional mode
Integer and Fractional mode
Integer mode only
Integer mode only
Input Type
Output Clock
Frequency Range
External crystal 5MHz - 333.33MHz
or Clock
5MHz - 200MHz
5MHz - 333.33MHz
5MHz - 200MHz
Operating
Temperature Range
-40 to +105C
Preprogrammed Devices Using a ClockBuilder Pro Configuration File
Si5332X DXXXXX - AMpR
Operating Temp Range: -40 to +105 ﾰC
AM = Automotive grade, QFN, ROHS6, Pb-free
p = 1 for 6-output, 32-pin QFN
2 for 8-output, 40-pin QFN
3 for 12-output, 48-pin QFN
R = Tape & Reel (ordering option)
D = Product Revision
XXXXX = NVM code. A unique 5-digit ordering sequence
will be assigned by ClockBuilder Pro.
Ordering Part
Number
Si5332A
Si5332B
Si5332C
Si5332D
Frequency Synthesis Mode
Integer and Fractional mode
Integer and Fractional mode
Integer mode only
Integer mode only
Input Type
Output Clock
Frequency Range
External crystal 5MHz - 333.33MHz
or Clock
5MHz - 200MHz
5MHz - 333.33MHz
5MHz - 200MHz
Operating
Temperature Range
-40 to +105C
Figure 2.1. Orderable Part Number Guide
3
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Table of Contents
1. Features List
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2. Ordering Guide
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3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Functional Block Diagrams .
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. 7
3.2 Modes of Operation .
3.2.1 Initialization . .
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. 9
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3.3 Frequency Configuration
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.10
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3.5 Outputs . . . . . . . . . . . . . . .
3.5.1 Output Signal Format . . . . . . . . .
3.5.2 Differential Output Terminations . . . . . .
3.5.3 LVCMOS Output Terminations . . . . . .
3.5.4 LVCMOS Output Signal Swing . . . . . .
3.5.5 LVCMOS Output Polarity . . . . . . . .
3.5.6 Output Enable/Disable . . . . . . . . .
3.5.7 Differential Output Configurable Skew Settings.
3.5.8 Synchronous Output Disable Feature . . . .
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.11
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.12
.16
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.17
3.6 Spread Spectrum .
3.4 Inputs . . . . . . . . . . .
3.4.1 External Reference Input (XA/XB)
3.4.2 Input Clocks . . . . . . .
3.4.3 Input Selection . . . . . .
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.17
3.7 Universal Hardware Pins
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.17
3.8 Custom Factory Preprogrammed Parts .
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.19
3.9 I2C Serial Interface
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.19
3.10 In-Circuit Programming .
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.19
3.11 Minimizing Power Consumption .
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.20
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
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6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
6.1 Pin Descriptions (48-QFN) .
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.35
6.2 Pin Descriptions (40-QFN) .
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.40
6.3 Pin Descriptions (32-QFN) .
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.45
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
7.1 Si5332-AM3 7x7 mm 48-QFN Package Diagram
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.49
7.2 Si5332-AM2 6x6 mm 40-QFN Package Diagram
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.51
7.3 Si5332-AM1 5x5 mm 32-QFN Package Diagram
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.52
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54
8. PCB Land Pattern
4
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4
8.1 7x7 mm 48-QFN Land Pattern .
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.54
8.2 6x6 mm 40-QFN Land Pattern .
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.56
8.3 5x5 mm 32-QFN Land Pattern .
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.58
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
5
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3. Functional Description
The Si5332-AM is an automotive Grade 2 high-performance, low-jitter clock generator capable of synthesizing up to 12 user-programmable clock frequencies up to 333.33 MHz. The device supports free-run operation using an external crystal or it can lock to an
external clock signal. The output drivers support up to 12 differential clocks or 24 LVCMOS clocks, or a combination of both. The output
drivers are configurable to support common signal formats, such as LVPECL, LVDS, HCSL, and LVCMOS. VDDO pins are provided
for versatility, which can be set to 3.3 V, 2.5 V, 1.8 V or 1.5 V (CMOS only) to power the multi-format output drivers. The core voltage
supply (VDD) accepts 3.3 V, 2.5 V, or 1.8 V and is independent from the output supplies (VDDOxs). Using its two-stage synthesis
architecture and patented high-resolution low-jitter MultiSynth technology, the Si5332 can generate an entire clock tree from a single
device.
The Si5332-AM combines a wideband PLL with next generation MultiSynth technology to offer the industry’s highest output count high
performance programmable clock generator with attainable jitter performance below 200 fs RMS. The PLL locks to either an external
16-50 MHz crystal or to an external clock (CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#) for generating synchronous clocks. In clock
generator mode, the oscillator frequency is multiplied by the PLL and then divided down either by an integer divider or MultiSynth for
fractional synthesis.
The Si5332-AM features user-defined universal hardware pins which can be configured in the ClockBuilder Pro software utility.
Universal hardware pins can be used for input functions, such as OE, spread spectrum enable, input clock selection, output frequency
selection, I2C address select, or RESET. Users can also assign a universal hardware pin as an LOS output or as a FOOF output.
The device provides the option of storing a user-defined clock configuration in its non-volatile memory (NVM), which becomes the
default clock configuration at power-up. To enable in-system programming, a power up mode is available through OTP, which powers
up the chip in an OTP defined default mode but with no outputs enabled. This allows a host processor to first write a user defined
subset of the registers and then restart the power-up sequence to activate the newly programmed configuration without re-downloading
the OTP.
SmartClock health monitoring and fault detection features are available through the LOS, FOOF, and CLK_SEL features using the
Universal HW pins defined during ClockBuilder Pro project file development. When using these features, both primary and backup input
reference sources are used. The Si5332-AM monitors the health of the input source to the PLL, and will provide a signal output to a
system safety manager or ASIL rated MCU if a loss of signal or out-of-frequency fault occurs. With an external MCU or equivalent,
the device can then migrate input reference from the primary source to the secondary source, ensuring clock outputs continue to be
supplied to endpoint devices. In the event of primary and redundant input reference failure, AlwaysOn mode allows the output clocks
to continue operating within ±5% of the desired output frequency. Further details on these features, as well as system implementations,
are available in the application note, "AN1292: Si5332-AM Fault Detection and Monitoring".
6
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.1 Functional Block Diagrams
Si5332-AM3: 12-Output, 48-QFN
÷INT
Bank A
CLKIN_2
CLKIN_2b
CLKIN_3
CLKIN_3b
XTAL
÷INT
÷INT
PLL
÷INT
OSC
Bank B
÷INT
NVM
SCLK
SDATA
Universal1
Universal2
Universal3
Universal4
Universal5
Universal6
Universal7
HW Input
Control
INT0
INT1
INT2
INT3
OUT2
OUT2b
VDDO2
OUT3
OUT3b
OUT4
OUT4b
÷INT
OUT5
OUT5b
Bank C
Multi
Synth1
VDDO1
OUT1
OUT1b
÷INT
I2C
Multi
Synth0
VDDO0
OUT0
OUT0b
÷INT
VDDO3
OUT6
OUT6b
÷INT
OUT7
OUT7b
÷INT
OUT8
OUT8b
÷INT
Bank D
÷INT
INT4
÷INT
VDDO4
OUT9
OUT9b
VDDO5
OUT10
OUT10b
OUT11
OUT11b
Figure 3.1. Block Diagram for 12-Output Si5332 in 48-QFN
The Si5332-AM2 48-QFN features:
• Up to 12 differential clock outputs with six VDDO pins.
• Seven user-configurable Universal HW pins, defined using ClockBuilder Pro.
7
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
Si5332-AM2: 8-Output, 40-QFN
VDDO0
÷INT
OUT1
OUT1b
VDDO1
CLKIN_2
CLKIN_2b
Multi
Synth
CLKIN_3
CLKIN_3b
XTAL
÷INT
OUT0
OUT0b
÷INT
PLL
Multi
Synth
OSC
Bank A
÷INT
÷INT
OUT3
OUT3b
INT
NVM
INT
SCLK
SDATA
I2C
INT
INT
Universal1
Universal2
Universal3
Universal4
INT
VDDO2
OUT2
OUT2b
Bank B
VDDO3
÷INT
OUT4
OUT4b
÷INT
OUT5
OUT5b
HW Input
Control
Universal5
VDDO4
Universal6
÷INT
Universal7
OUT6
OUT6b
VDDO5
÷INT
OUT7
OUT7b
Figure 3.2. Block Diagram for 8-Output Si5332 in 40-QFN
The Si5332-AM2 40-QFN features:
• Up to eight differential clock outputs with six VDDO pins.
• Seven user-configurable Universal HW pins, defined using ClockBuilder Pro.
8
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8
Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
Si5332-AM1: 6-Output, 32-QFN
VDDO0
÷INT
VDDO1
CLKIN_2
CLKIN_2b
Multi
Synth
÷INT
XTAL
OUT0
OUT0b
OUT1
OUT1b
÷INT
OUT2
OUT2b
PLL
Multi
Synth
OSC
÷INT
VDDO2
INT
NVM
SCLK
SDATA
I2C
VDDO3
INT
÷INT
OUT3
OUT3b
INT
VDDO4
Universal1
Universal2
Universal3
Universal4
INT
HW Input
Control
÷INT
OUT4
OUT4b
INT
VDDO5
Universal5
÷INT
OUT5
OUT5b
Figure 3.3. Block Diagram for 6-Output Si5332 in 32-QFN
The Si5332-AM1 32-QFN features:
• Up to six differential clock outputs with individual VDDO.
• Five user-configurable Universal HW pins, defined using ClockBuilder Pro.
3.2 Modes of Operation
The Si5332-AM supports both free-run and synchronous modes of operation. The default mode selection is set in ClockBuilder Pro.
Alternatively, two universal hardware pins can be defined as CLKIN_SEL[1:0] to select between a crystal or clock input. There is also
the option to select the input source via the serial interface by writing to the input select register.
3.2.1 Initialization
When power is applied, the device begins an initialization period where it downloads default register values and configuration data
from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this
initialization period is complete. The clock outputs will be squelched until the device initialization is done.
3.3 Frequency Configuration
The phase-locked loop is fully integrated and does not require external loop filter components. Its function is to phase lock to the
selected input and provide a common synchronous reference to the high-performance MultiSynth fractional or integer dividers.
A cross point mux connects any of the MultiSynth divided frequencies or INT divided frequencies to individual output drivers or banks
of output drivers. Additional output integer dividers provide further frequency division by an integer from 1 to 63. The frequency
configuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth
fractional dividers (Nn/Nd), and the output integer dividers (R). Skyworks’ Clockbuilder Pro configuration utility determines the optimum
divider values for any desired input and output frequency plan
9
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9
Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.4 Inputs
The Si5332 requires an external 16–50 MHz crystal at its XA/XB pins to operate in free-run mode, or an external input clock (CLKIN_2/
CLKIN_2# or CLKIN_3/CLKIN_3#) for synchronous operation. An external crystal is not required in synchronous mode.
3.4.1 External Reference Input (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) on Si5332-AM to produce a low jitter reference for
the PLL when operating in the free-run mode. The Si5332-AM1/2/3 Automotive Grade Device Reference Manual provides additional
information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table 5.4 External Crystal
Input Specification on page 25 for crystal specifications.
For free-running operation, the internal oscillator can operate from a low-frequency fundamental mode crystal (XTAL) with a resonant
frequency of 16 to 50 MHz. A crystal can easily be connected to pins XA and XB without external components, as shown in the figure
below. Internal loading capacitance (CL) values from 2.5 pf to 21.5 pf can be selected via register settings. Alternatively, an external CL
can be used along with the internal CL. See the Si5332-AM1/2/3 Automotive Grade Device Reference Manual for more information on
calculating crystal capacitive loading values.
XA
Osc
XTAL
To synthesis stage
or output selectors
XB
Figure 3.4. External Reference Input (XA/XB)
3.4.2 Input Clocks
An input clock is available to synchronize the PLL when operating in synchronous mode. This input can be configured as LVPECL,
LVDS or HCSL differential, or LVCMOS. The recommended input termination schemes are shown in the Si5332-AM1/2/3 Family
Reference Manual. Input clocks defined as "Unused" in CBPro can be left unconnected.
3.4.3 Input Selection
The active clock input is selected by register control, or by defining two universal input pins as CLKIN_SEL[1:0] in ClockBuilder Pro.
A register bit determines input selection as pin or register selectable. If there is no clock signal on the selected input at power-up, the
device will not generate output clocks.
In a typical application, the Si5332-AM reference input is configured immediately after power-up and initialization. If the device is
switched to another input more than ±1000 ppm offset from the initial input, the device must be recalibrated manually to the new
frequency, temporarily turning off the clock outputs. After the VCO is recalibrated, the device will resume producing clock outputs. If the
selected inputs are within ±1000 ppm, any phase error difference will propagate through the device at a rate determined by the PLL
bandwidth. Hitless switching and phase build-out are not supported by the Si5332-AM.
SmartClock health monitoring and fault detection features utilize the CLK_SEL pins. ClockBuilder Pro helps guide users through the
steps needed to assign these pins.
10
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.5 Outputs
The Si5332-AM supports up to 12 differential output drivers. Each output can be independently configured as a differential pair or as
dual LVCMOS outputs. The 8-output and 12-output devices feature banks of outputs, with each bank sharing a common VDDO.
Table 3.1. Clock Outputs
Device/Package
Maximum Outputs
Si5332-AM1 (32-QFN)
6 Differential, 12 LVCMOS
Si5332-AM2 (40-QFN)
8 Differential, 16 LVCMOS
Si5332-AM3 (48-QFN)
12 Differential, 24 LVCMOS
The output stage is different for each of the three versions of Si5332.
• The 6-output device features individual VDDO pins for each clock output. Each clock output can be sourced from MultiSynth0,
MultiSynth1, the input reference clock, or one of the five INT dividers through the cross point mux.
• The 8-output device includes four clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0,
MultiSynth1, the input reference clock, or one of the five INT dividers through the cross point mux. The remaining four clock outputs
are divided into Bank A and Bank B. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the input reference clock,
or one of the five INT dividers through the cross point mux. The outputs within each of the two Banks share a common VDDO pin.
• The 12-output device includes two clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0,
MultiSynth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The remaining ten clock outputs
are divided into Bank A, Bank B, Bank C, and Bank D. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the
input reference clock, or one of the five INT dividers through the cross point MUX. The outputs within each of the four Banks share a
common VDDO pin.
Individual output banks can be configured to supply buffered copies of the input reference clock for all outputs within the bank.
Individual integer output dividers (R) allow the generation of additional synchronous frequencies. These integer dividers are configurable as divide by 1 (default) through 63.
3.5.1 Output Signal Format
The differential output swing and common mode voltage are compatible with a wide variety of signal formats including HCSL, LVDS and
LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS drivers, enabling the device to
support both differential and single-ended clock outputs. Output formats can be defined in ClockBuilder Pro or via the serial interface.
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.5.2 Differential Output Terminations
LVDS Driver Termination
For a general LVDS interface, the recommended value for the differential termination impedance (ZT) is between 90 Ω and 132 Ω. The
actual value should be selected to match the differential impedance (Z0) of the transmission line. A typical point-to-point LVDS design
uses a 100 Ω parallel resistor at the receiver and a 100 Ω differential transmission-line environment. To avoid any transmission-line
reflection issues, surface mount the components and place them as close to the receiver as possible. The standard LVDS termination
schematic as shown in Figure 3.5 Standard LVDS Termination on page 12 can be used with either type of output structure. Figure
3.6 Optional LVDS Termination on page 12, which can also be used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value should be approximately 0.01 to 0.1 μF. If using a non-standard
termination, please contact Skyworks to confirm if the output structure is current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the
output.
Zo = ZT/2
Si5332-AM
LVDS Output
Driver
+
LVDS
Receiver
ZT
Zo = ZT/2
_
Figure 3.5. Standard LVDS Termination
Zo = ZT/2
Si5332-AM
LVDS Output
Driver
Zo = ZT/2
+
C
ZT/2 LVDS
Receiver
ZT/2 _
Figure 3.6. Optional LVDS Termination
Termination for 3.3 V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current
path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines. Use
matched impedance techniques to maximize operating frequency and minimize signal distortion. Figure 3.7 3.3 V LVPECL Output
Termination, Option 1 on page 13 and Figure 3.8 3.3 V LVPECL Output Termination, Option 2 on page 13 show two different layouts.
Other suitable clock layouts may exist, but it is recommended that the board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.3V
3.3V
Zo=50Ω
Si5332-AM
LVPECL Output
Driver
+
Zo=50Ω
_
Input
LVPECL
R1
50Ω
RTT = 54Ω
R2
50Ω
RTT
Vcc-2V
Figure 3.7. 3.3 V LVPECL Output Termination, Option 1
3.3V
R3
125Ω
3.3V
R4
125Ω
Zo=50Ω
Si5332-AM
LVPECL Output
Driver
3.3V
+
Zo=50Ω
_
LVPECL
R1
84Ω
Input
R2
84Ω
Figure 3.8. 3.3 V LVPECL Output Termination, Option 2
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
Termination for 2.5 V LVPECL Outputs
Figure 3.9 2.5 V LVPECL Termination Example, Option 1 on page 14 and Figure 3.10 2.5 V LVPECL Termination Example, Option 2
on page 14 show examples of termination for the 2.5 V LVPECL driver option. These terminations are equivalent to terminating 50 Ω
to VDDO – 2 V. For VDDO = 2.5 V, the VDDO – 2 V is very close to ground level. The R3 in Figure 3.10 2.5 V LVPECL Termination
Example, Option 2 on page 14 can be optionally eliminated using the termination shown in Figure 3.9 2.5 V LVPECL Termination
Example, Option 1 on page 14.
2.5V
R3
250 Ω
2.5V
R4
250 Ω
Zo=50 Ω
Si5332-AM
LVPECL Output
Driver
2.5V
+
Zo=50 Ω
_
Input
2.5V LVPECL
Driver
R1
62.5 Ω
R2
62.5 Ω
Figure 3.9. 2.5 V LVPECL Termination Example, Option 1
2.5V
2.5V
Zo=50 Ω
Si5332-AM
LVPECL Output
Driver
+
Zo=50 Ω
2.5V LVPECL
Driver
_
R1
50Ω
Input
R2
50Ω
R3
18Ω
Figure 3.10. 2.5 V LVPECL Termination Example, Option 2
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
Termination for HCSL Outputs
The Si5332-AM HCSL driver option integrates termination resistors to simplify interfacing to an HCSL receiver. The HCSL driver
supports both 100 Ω and 85 Ω transmission line options. This configuration option may be specified using ClockBuilder Pro or via the
device I2C interface.
1.71 V to 3.465 V
Si5332-AM
HCSL Output
Driver
Zo = 42.5 Ω
or 50 Ω
OUTx
Zo = 42.5 Ω
or 50 Ω
OUTxb
HCSL
Receiver
Figure 3.11. HCSL Internal Termination Mode
1.71 V to 3.465 V
Si5332-AM
HCSL Output
Driver
OUTx
Zo = 42.5 Ω
or 50 Ω
RT = Zo
Zo = 42.5 Ω
or 50 Ω
OUTxb
HCSL
Receiver
RT = Zo
Figure 3.12. HCSL External Termination Mode
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.5.3 LVCMOS Output Terminations
LVCMOS outputs can be dc-coupled, as shown in the figure below.
1.71 to 3.465 V
Zo = 50 Ω
Set output
driver to 50 Ω
mode.
OUTx
Zo = 50 Ω
OUTxb
Figure 3.13. LVCMOS Output Termination Example, Option 1
1.425 to 3.465 V
OUTx
Set output driver
to 25 Ω mode.
Rs
OUTxb
Rs
Rs = Zo – Rdrv
(see Table 5.8)
Figure 3.14. LVCMOS Output Termination Example, Option 2
The Si5332-AM features complementary LVCMOS driver options on all outputs. Skyworks recommends the use of complementary
LVCMOS output drivers for all single-ended clock outputs in order to minimize unwanted emissions. Further details about using
complementary LVCMOS output drivers, and the positive effects in CISPR25 Class4 and Class5 testing results, can be found in
"AN1237: Si5332 Design Guidelines for Minimizing EMI".
3.5.4 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pin for the respective bank.
3.5.5 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). The LVCMOS outputs,
OUTx and OUTxb, can be configured in CBPro to be either in-phase or complementary (180 degrees out of phase).
3.5.6 Output Enable/Disable
The universal hardware input pins can be programmed to operate as output enable (OEb), controlling one or more outputs. Pin
assignment is done using ClockBuilder Pro. An output enable pin provides a convenient method of disabling or enabling the output
drivers. When the output enable pin is held high all designated outputs will be disabled. When held low, the designated outputs will be
enabled. Outputs in the enabled state can be individually disabled through register control.
3.5.7 Differential Output Configurable Skew Settings
Skew on the differential outputs can be independently configured. The skew is adjustable in 35 ps steps across a range of 245 ps.
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
3.5.8 Synchronous Output Disable Feature
Output clocks are always enabled and disabled synchronously. The output will wait until a clock period has completed before the
driver is disabled. Similarly, outputs are synchronously enabled. This prevents unwanted runt pulses from occurring when disabling or
enabling an output.
3.6 Spread Spectrum
To help reduce electromagnetic interference (EMI), the Si5332-AM supports spread spectrum modulation. The output clock frequencies
can be modulated to spread energy across a broader range of frequencies, lowering system EMI. The Si5332-AM implements spread
spectrum using its patented MultiSynth technology to achieve previously unattainable precision in both modulation rate and spreading
magnitude. Spread spectrum can be configured in ClockBuilder Pro to be enabled.
The Si5332-AM features both center and down spread spectrum modulation capability, from 0.1% to 2.5%. Each MultiSynth is capable
of generating an independent spread spectrum clock. The feature is enabled using a user-defined universal hardware input pin or
via the device I2C interface. Spread spectrum can only be applied to an output clock derived from a MultiSynth fractional divider (up
to 250 MHz) since spread spectrum clock generation is performed in the MultiSynth fractional dividers. The Si5332-AM features two
independent MultiSynth dividers enabling the device to provide two independent spread profiles simultaneously to the clock output
banks.
Spread spectrum is commonly used for 100 MHz PCI Express clock outputs. To comply with the spread spectrum specifications for
PCI Express, set the spreading frequency to a maximum of 33 kHz and –0.5% down spread. A universal hardware input pin can be
configured to toggle spread spectrum on/off.
3.7 Universal Hardware Pins
Universal hardware pins are user-configurable control pins that can have one or more of the functions listed below assigned to them
using ClockBuilder Pro.
Universal hardware pins can be utilized for the following functions:
Table 3.2. Universal Hardware Pins
Description
Function
SSEN_EN0
Spread spectrum enable on MultiSynth0 (N0).
SSEN_EN1
Spread spectrum enable on MultiSynth0 (N1).
FS_INTx
Used to switch an integer output divider frequency from frequency A to frequency B.
FS_MSx
Used to switch a MultiSynth output divider output from frequency and/or change spread
spectrum profile.
OE
I2C address select
CLKIN_SEL[1:0]
17
Output enable for one or more outputs.
Sets the LSB of the I2C address to either 0 or 1.
Selects between crystal or clock inputs.
LOS
Loss Of Signal (LOS) Output: Asserts if reference input frequency signal drops below
configured input frequency or is no longer detected.
FOOF
Fast Out Of Frequency (FOOF) Output: Asserts if PLL can no longer track input reference clock.
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Si5332-AM Automotive Grade Clock Generator with SmartClock™ Technology • Functional Description
Spread Spectrum Enable Pins (SSEN[1:0])
SSEN_EN[1:0] pins are input pins that enable/disable spread spectrum on all outputs that correspond to MutliSynth0 or MultiSynth1,
respectively. The change in frequency or spread spectrum will be instantaneous and may not be glitch-free.
Table 3.3. SSEN_EN Pin Selection Table
SSEN_ENx
0
Spread Spectrum disabled on MultiSynthx
1
Spread Spectrum enabled on MultiSynthx
Output Frequency Select Pins
There are five integer dividers, one corresponding to each of the five output banks. Using ClockBuilder Pro, a universal hardware input
pin can be assigned for each integer divider, providing capability to select between two different pre-programmed divide values. Divider
values of every integer from 8 to 255 are available in ClockBuilder Pro for each integer divider.
Table 3.4. FS_INT Pin Selection Table
FS_INTX
Output Frequency from INTx
0
Frequency A, as defined in ClockBuilder Pro
1
Frequency B, as defined in ClockBuilder Pro
Output Enable
A universal hardware input pin can be defined to control output enable of a differential output, a bank of differential outputs, or as a
global output enable pin controlling all outputs. Upon de-assertion of an OE pin, the corresponding output will be disabled within 2-6
clock cycles. Asserting an OE pin from disable to enable will take
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