Si8935/36/37 Data Sheet
Delta-Sigma Modulator for Voltage Measurement
KEY FEATURES
The Si8935/36/37 is a galvanically isolated delta-sigma modulator optimized for voltage sensing. Its 2.5 V input range is ideal for isolated voltage sensing applications. The Si8935/36/37
provides excellent linearity with low offset and gain drift to ensure that accuracy is maintained
over the entire operating temperature range. Exceptionally high common-mode transient immunity means that the Si8935/36/37 delivers accurate measurements even in the presence of
high-power switching as is found in motor drive systems and inverters.
The output of the Si8935/36/37 comes from a second-order, delta-sigma modulator. The modulator can be clocked either from an onboard oscillator (Si8936/37) or from an external clock
(Si8935). The output is typically digitally filtered by a MCU or FPGA in the system.
The Si8935/36/37 isolated delta-sigma modulator utilizes Silicon Labs’ proprietary isolation
technology. It supports up to 5.0 kVrms withstand voltage per UL1577. This technology enables
higher performance, reduced variation with temperature and age, tighter part-to-part matching,
and longer lifetimes compared to other isolation technologies.
• 0 to 2.5 V nominal input voltage
• Modulator clock options
• External clock up to 25 MHz
(Si8935)
• 10 MHz internal clock (Si8936)
• 20 MHz internal clock (Si8937)
• Typical input offset: ±0.4 mV
• Typical gain error: ±0.05%
• Excellent drift specifications
• ±0.5 µV/°C typical offset drift
• 9 ppm/°C typical gain drift
• Typical nonlinearity: 0.003%
• Typical SNR: 86 dB
Applications:
• Industrial, HEV and renewable energy inverters
• AC, Brushless, and DC motor controls and drives
• Variable speed motor control in consumer white goods
• Isolated switch mode and UPS power supplies
• General industrial data acquisition and sensor interface
• Automotive onboard chargers, battery management systems, and charging stations
• High common-mode transient
immunity: 75 kV/µs
• Auomotive-grade OPNs
• AIAG-compliant PPAP
documentation support
• IMDS and CAMDS listing
support
• Compact packages
• 8-pin wide body stretched SOIC
Safety Approvals (Pending):
• UL 1577 recognized
• Up to 5000 Vrms for 1 minute
• CSA approval
• IEC 60950-1, 62368-1 (reinforced insulation)
• VDE certification conformity
• VDE0884 Part 11 (basic/reinforced insulation)
• CQC certification approval
• GB4943.1-2011
• 8-pin narrow body SOIC
• –40 to 125 °C
VDDA
VIN
DSM
NC
GNDA
1
Transmitter
CMOS Isolation
Si8935, Si8936, Si8937
VDDB
CLK
ACLK
ADAT
Receiver
GNDB
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Si8935/36/37 Data Sheet • Ordering Guide
1. Ordering Guide
Table 1.1. Si8935-36-37 Ordering Guide1, 2, 3
Ordering
Part Number (OPN)
Automotive OPN4
Si8935D-IS4
Ordering Options
Isolation Rating
Clock
Package Type
Si8935D-AS4
5.0 kVrms
Input
WB Stretched
SOIC-8
Si8935B-IS
Si8935B-AS
2.5 kVrms
Input
NB SOIC-8
Si8936D-IS4
Si8936D-AS4
5.0 kVrms
10 MHz Output
WB Stretched
SOIC-8
Si8936B-IS
Si8936B-AS
2.5 kVrms
10 MHz Output
NB SOIC-8
Si8937D-IS4
Si8937D-AS4
5.0 kVrms
20 MHz Output
WB Stretched
SOIC-8
Si8937B-IS
Si8937B-AS
2.5 kVrms
20 MHz Output
NB SOIC-8
Note:
1. All packages are RoHS-compliant.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 pending qualification.
4. Automotive-Grade devices ("–A" suffix) are identical in construction materials, topside marking, and electrical parameters to their
Industrial-Grade ("–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive process flows
and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on
shipping labels.
2
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Table of Contents
1. Ordering Guide
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2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Fail-Safe and Low-Power Modes .
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2.2 Modulator.
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3. Voltage Sense Application . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Regulatory Information .
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4.2 Typical Operating Characteristics .
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5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6. Packaging
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6.1 Package Outline: 8-Pin Wide Body Stretched SOIC
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6.2 Package Outline: 8-Pin Narrow Body SOIC .
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6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC .
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6.4 Land Pattern: 8-Pin Narrow Body SOIC
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6.5 Top Marking: 8-Pin Wide Body Stretched SOIC .
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6.6 Top Marking: 8-Pin Narrow Body SOIC .
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7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Si8935/36/37 Data Sheet • System Overview
2. System Overview
The input to the Si8935/36/37 is designed for 0 to 2.5 V nominal input.
The analog input stage of the Si8935/36/37 is a single-ended amplifier feeding the input of a second-order, delta-sigma (ΔΣ) modulator
that digitizes the input signal into a 1-bit output stream. The isolated data output ADAT pin of the converter provides a stream of digital
ones and zeros that is synchronous to the ACLK pin. The Si8936/37 clock is generated internally while the Si8935 clock is provided
externally. The time average of this serial bit-stream output is proportional to the analog input voltage.
VDDA
VIN
DSM
NC
GNDA
Transmitter
CMOS Isolation
Si8935, Si8936, Si8937
VDDB
CLK
ACLK
ADAT
Receiver
GNDB
Figure 2.1. Si8935/36/37 Functional Block Diagram
2.1 Fail-Safe and Low-Power Modes
The Si8935/36/37 implements a fail-safe output when the high-side supply voltage VDDA goes away. The fail-safe output is steady
state logic 0 on ADAT for the externally clocked Si8935. The fail-safe output is a steady state logic 1 on ADAT for the internally clocked
Si8936/37. The clock output ACLK of the Si8946/47 will stop after 256 cycles with a steady state logic 1. When the supply comes back,
the clock will be turned back on and normal DSM data stream will be output in approximately 200 μs. To differentiate from the fail-safe
output, a maximum nominal input signal will generate a single one every 128 bits at ADAT.
In addition to the fail-safe output, when a loss of VDDA supply occurs the part will automatically move into a lower power mode that
reduces IDDB current to approximately 1 mA. Similarly, a loss of VDDB supply will reduce IDDA current to approximately 1 mA. When
the supply voltage is returned, normal operation begins in approximately 250 μs.
4
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Si8935/36/37 Data Sheet • System Overview
2.2 Modulator
The output of the Si8935/36/37 comes from a second-order, delta-sigma modulator like that shown in the figure below. The modulator
provides 1-bit datastream whose average represents the input analog voltage. 0 V across the inputs is represented at the output by a
pulse train that has 50% ones density. Specified linear full-scale at the input (e.g., +2.25 V) produces an output datastream that has
92.87% ones density.
Ʃ
Ʃ
ʃ
ʃ
REF
ʃ
1-Bit DAC
Figure 2.2. Typical 2nd Order Delta-Sigma Modulator Block Diagram
Table 2.1. Modulator Output
5
Single-Ended Input
Bitstream % Ones
2.25 V
92.87%
1.125 V
71.44%
0V
50%
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Si8935/36/37 Data Sheet • Voltage Sense Application
3. Voltage Sense Application
A typical isolated voltage sensing application circuit is shown below. In this example, a high voltage is divided down to produce a
voltage (VIN) within the optimum input signal range of the Si8935/36/37. Numerous alternative inputs configurations are possible with
the flexibility of a high impedance input isolator. The Si8935/36/37 senses the single-ended input voltage where it is oversampled and
converted into a 1-bit bitstream, then transmitted across the isolation barrier to be processed by the system controller/FPGA. If the
voltage sensed is > 2.5 V, a simple voltage divider consisting of R1 and R2 can be used to scale down any voltage to fit the input range
of the Si8935/36/37. R2 < 10 kΩ is recommended for best performance.
3 to 5.5 V
Supply
3 to 5.5 V
Supply
C2
R1
C4
0.1µF
1
2
R2 ≤ 10 kΩ
C1
3
4
VDDA
VDDB
VIN
ACLK
NC
ADAT
GNDA
GNDB
8
0.1µF
FPGA
7
SINC3
6
5
Si8935/36/37
Clock
Figure 3.1. Voltage Sense Application
The Si8935/36/37 has intrinsic low-pass filtering at approximately 800 kHz. For applications where input filtering is required, a passive
RC low-pass filter can be placed at the input pin. Consider the source resistance of the signal measured (or the parallel combination
of R1 and R2 if using a voltage divider) as it should be included in the filter calculation. Capacitor C1 should be sized to make a band
limiting filter at the desired frequency.
C4, the local bypass capacitor for the B-side of Si8935/36/37, should be placed closed to VDDB supply pin with its return close to
GNDB. The output signal typically goes directly to a digital filter for additional processing. The digital filter may be implemented by a
dedicated FPGA in the system or may be a peripheral in the main system controller. The Si8935 expects an external clock to provide
the clock signal for the modulator. That external clock can be provided by the same device that implements the digital filtering or
another device that syncs both the modulator and the digital filter. The Si8936/37 generates an internal clock to the digital filter.
6
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Si8935/36/37 Data Sheet • Electrical Specifications
4. Electrical Specifications
Table 4.1. Electrical Specifications
TA = –40 to +125 °C, SINC3 filter with 256 oversampling ratio and 20 MHz clock; typical specs at 25 °C and VDDA = VDDB = 5V unless
specified otherwise
Parameter
Symbol
Input Side Supply
Voltage
VDDA
Input Supply Current
IDDA
Output Side Supply
Voltage
VDDB
Output Supply
Current (Si8935)
IDDB
VDDB = 3.3 V
1
Output Supply
Current (Si8936)
IDDB
VDDB = 3.3 V
IDDB
VDDB = 3.3 V
Output Supply
Current (Si8937)
Test Condition
Min
Typ
Max
Units
5.5
V
8.7
mA
5.5
V
1.8
2.7
mA
2.8
4.4
7.2
mA
4.1
6.1
11
mA
2.25
V
3.0
VDDA = 3.3 V
5.6
7
3.0
Amplifier Input
Specified Linear Input Range
VIN
Maximum Input
Voltage Before
Clipping
VIN
Input Referred
Offset
VOS
Input Offset Drift
VOST
Input Impedance
RIN
0.25
2.5
TA = 25 °C, VIN = 0.25 V
V
–3
±0.4
3
mV
–40
±0.5
25
µV/°C
500
MΩ
Dynamic Characteristics
Gain
1
TA = 25 °C
Gain Error
Gain Error Drift
TA = 25 °C
Nonlinearity
Nonlinearity Drift
–0.15
±0.05
0.15
%
–7
9
20
ppm/°C
–0.016
0.003
0.016
%
1
ppm/°C
–1
FIN = 5 kHz
Signal-to-Noise
Ratio
SNR
BW = 40 kHz (Si8935/37)
73
86
dB
BW = 20 kHz (Si8936)
FIN = 5 kHz
Total Harmonic
Distortion
THD
–83
BW = 40 kHz (Si8935/37)
–60
dB
BW = 20 kHz (Si8936)
Common-Mode
Transient
Immunity
7
CMTI
VIN = GNDA,
VCM = 1500 V
50
75
kV/µs
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Si8935/36/37 Data Sheet • Electrical Specifications
Parameter
Power-Supply Rejection Ratio
Symbol
PSRR
Test Condition
Min
Typ
Max
Units
VDDA at DC
–100
dB
VDDA at 100 mV and 10 kHz
ripple
–100
dB
VDDB at DC
–100
dB
VDDB at 100 mV and 10 kHz
ripple
–100
dB
Digital
Logic high input
threshold (Si8935)
VIH
85% of
VDDB
Logic low input
threshold (Si8935)
VIL
Input hysteresis
VIHYST
120
mV
Output load
capacitance
CLOAD
15
pF
V
15% of
VDDB
V
External Clock (Si8935)
Clock Frequency
FCLKIN
5
Duty Cycle
FDUTY
45
Delay to Data Valid
TDELAY
Data Hold Time
THOLD
50
25
MHz
55
%
23
ns
6
ns
Internal Clock (Si8936)
Clock Frequency
FCLKOUT
Duty Cycle
FDUTY
Delay to Data Valid
TDELAY
Data Hold Time
THOLD
TA = 25 °C
9.9
10
10.1
MHz
TA = –40 °C to 125 °C
9.8
10
10.2
MHz
45
50
55
%
60
ns
40
ns
Internal Clock (Si8937)
8
Clock Frequency
FCLKOUT
Duty Cycle
FDUTY
Delay to Data Valid
TDELAY
Data Hold Time
THOLD
TA = 25 °C
19.8
20
20.2
MHz
TA = –40 °C to 125 °C
19.6
20
20.4
MHz
45
50
55
%
30
ns
20
ns
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Si8935/36/37 Data Sheet • Electrical Specifications
TDELAY
THOLD
FCLKIN
ACLK
ADAT
Figure 4.1. Si8935 Clock Input
THOLD
TDELAY
FCLKOUT
ACLK
ADAT
Figure 4.2. Si8936/37 Clock Output
VDDB
Si8935/36/37
1
Isolated
Supply
+
-
2
3
4
VDDA
VDDB
VIN
ACLK
NC
ADAT
GNDA
GNDB
8
7
6
5
RC Low-Pass
at 1 Mhz
Oscilloscope
High Voltage
Differential
Probe
High Voltage Transient Generator
Figure 4.3. Common-Mode Transient Immunity Characterization Circuit
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Si8935/36/37 Data Sheet • Electrical Specifications
Table 4.2. IEC Safety Limiting Values1
Parameter
Safety Temperature
Symbol
Test Condition
TS
Characteristic
Unit
150
°C
253
mA
386
mA
203
mA
310
mA
1389
mW
1116
mW
θJA = 90 °C/W
VDD = 5.5 V
TJ = 150 °C
Safety Input Current (WB Stretched SOIC-8)
IS
TA = 25 °C
θJA = 90 °C/W
VDD = 3.6 V
TJ = 150 °C
TA = 25 °C
θJA = 112 °C/W
VDD = 5.5 V
TJ = 150 °C
Safety Input Current (NB SOIC-8)
IS
TA = 25 °C
θJA = 112 °C/W
VDD = 3.6 V
TJ = 150 °C
TA = 25 °C
θJA = 90 °C/W
Safety Input Power (WB Stretched SOIC-8)
PS
TJ = 150 °C
TA = 25 °C
θJA = 112 °C/W
Safety Input Power (NB SOIC-8)
PS
TJ = 150 °C
TA = 25 °C
Device Power Dissipation (WB Stretched SOIC-8)
PD
1.39
W
Device Power Dissipation (NB SOIC-8)
PD
1.12
W
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curves below.
10
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Si8935/36/37 Data Sheet • Electrical Specifications
Table 4.3. Thermal Characteristics
Parameter
IC Junction-to-Air Thermal Resistance
Symbol
WB Stretched
SOIC-8
NB SOIC-8
Unit
θJA
90
112
°C/W
Safety Limiting Current (mA)
Figure 4.4. WB Stretched SOIC-8 Thermal Derating Curve for Safety Limiting Current
350
3.6 V
300
5.5 V
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (o C)
Figure 4.5. NB SOIC-8 Thermal Derating Curve for Safety Limiting Current
11
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Si8935/36/37 Data Sheet • Electrical Specifications
Table 4.4. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
TSTG
–65
150
°C
Ambient Temperature Under Bias
TA
–40
125
°C
Junction Temperature
TJ
—
150
°C
VDDA, VDDB
–0.5
6.0
V
Input Voltage respect to GNDA
VIN
–0.5
VDDA + 0.5
V
Output Sink or Source Current
|IO|
—
5
mA
Total Power Dissipation
PT
—
212
mW
Lead Solder Termperature (10 s)
—
260
°C
Human Body Model ESD Rating
6000
—
V
Capacitive Discharge Model ESD Rating
2000
—
V
Maximum Isolation (WB Stretched SOIC-8 Input to Output) (1 s)
—
6500
VRMS
Maximum Isolation (NB SOIC-8 package Input to Output) (1 s)
—
4500
VRMS
Storage Temperature
Supply Voltage
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of the data sheet.
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Si8935/36/37 Data Sheet • Electrical Specifications
4.1 Regulatory Information
Table 4.5. Regulatory Information (Pending)1, 2
CSA
The Si8935/36/37 is certified under CSA. For more details, see Master Contract File 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
The Si8935/36/37 is certified according to VDE 0884-11. For more details, see File 5006301-4880-0001.
VDE 0884-11: Up to 1414 Vpeak for reinforced insulation working voltage.
UL
The Si8935/36/37 is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si8935/36/37 is certified under GB4943.1-2011.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 5 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
2. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Table 4.6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Nominal External Air Gap (Clearance)
Test Condition
WB Stretched
SOIC-8
NB
SOIC-8
Unit
CLR
9.01
4.9
mm
Nominal External Tracking
(Creepage)
CPG
9.01
4.01
mm
Minimum Internal Gap
(Internal Clearance)
DTI
36
36
µm
Tracking Resistance
PTI or CTI
600
600
V
Erosion Depth
ED
0.04
0.04
mm
Resistance (Input-Output)2
RIO
1012
1012
Ω
Capacitance (Input-Output)2
CIO
1
1
pF
IEC60112
f = 1 MHz
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as x.x mm minimum for the WB Stretched SOIC-8 package. UL does not impose a clearance and creepage minimum for
component-level certifications. CSA certifies the clearance and creepage limits as 8 mm minimum for the WB Stretched SOIC-8
package.
2. To determine resistance and capacitance, the Si8935/36/37 is converted into a two-terminal device. Pins 1–4 are shorted together
to form the first terminal, and pins 5–8 are shorted together to form the second terminal. The parameters are then measured
between these two terminals.
13
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Si8935/36/37 Data Sheet • Electrical Specifications
Table 4.7. IEC 60664-1 Ratings
Specification
Parameter
Test Conditions
WB Stretched
SOIC-8
NB SOIC-8
Material Group
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-IV
I-IV
Rated Mains Voltages < 600 VRMS
I-IV
I-III
Basic Isolation Group
Installation
Classification
Table 4.8. VDE 0884-11 Insulation Characteristics1
Characteristic
Parameter
Symbol
Maximum Working Insulation Voltage
VIORM
Test Condition
Unit
WB Stretched
SOIC-8
NB SOIC-8
1414
560
V peak
2650
1050
V peak
8000
4000
V peak
Method b1
Input to Output Test Voltage
VPR
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 sec
Surge Voltage
VIOSM
Tested per IEC 60065 with surge
voltage using rise/decay time of
1.2 μs/50 μs
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at
TS, VIO = 500 V
RS
6250
6250
(Tested with 10 kV) (Tested with 10 kV)
2
2
>109
>109
V peak
Ω
Note:
1. This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The Si8935/36/37 provides a climate classification of 40/125/21.
14
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Si8935/36/37 Data Sheet • Electrical Specifications
0.1
0.1
0.05
0.05
INL (%)
INL (%)
4.2 Typical Operating Characteristics
0
-0.05
0
-0.05
-0.1
-0.1
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
0.3
0.2
0.2
0.1
0.1
INL (%)
0.3
0
4.5
5.0
5.5
0
-0.1
-0.1
-0.2
-0.2
-0.3
0.0
0.5
1.0
1.5
Signal Amplitude (V)
2.0
2.5
Figure 4.8. Si8935 Nonlinearity (%) vs. Input Signal Amplitude (mV)
0.0
0.3
100
0.2
90
0.1
80
0
0.5
1.0
1.5
Signal Amplitude (V)
2.0
2.5
Figure 4.9. Si8936 Nonlinearity (%) vs. Input Signal Amplitude (mV)
SNR (dB)
INL (%)
4.0
Figure 4.7. Si8935 Nonlinearity (%) vs. VDDA Supply (V)
-0.3
70
-0.1
60
-0.2
50
40
-0.3
0.0
0.5
1.0
1.5
Signal Amplitude (V)
2.0
2.5
Figure 4.10. Si8937 Nonlinearity (%) vs. Input Signal Amplitude (mV)
15
3.5
VDDA (V)
Figure 4.6. Si8935 Nonlinearity (%) vs. Temperature (°C)
INL (%)
3.0
5
10
15
MCLK (MHz)
20
25
Figure 4.11. Si8935 Signal-to-Noise Ratio (dB) vs. MCLK
(MHz)
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100
100
90
90
80
80
SNR (dB)
SNR (dB)
Si8935/36/37 Data Sheet • Electrical Specifications
70
60
60
50
50
40
40
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
Figure 4.12. Si8935 Signal-to-Noise Ratio (dB) vs. Temperature (°C)
3.0
100
-50
90
-60
80
-70
70
3.5
4.0
4.5
VDDA Supply (V)
5.0
5.5
Figure 4.13. Si8935 Signal-to-Noise Ratio (dB) vs. VDDA
Supply (V)
THD (dB)
SNR (dB)
70
-80
60
-90
50
-100
-110
40
0.0
0.5
1.0
1.5
Input Signal Amplitude (Vpp)
2.0
-40
2.5
Figure 4.14. Si8935 Signal-to-Noise Ratio (dB) vs. Input
Signal Amplitude (mV)
-20
0
20
40
60
Temperature (˚C)
80
100
120
Figure 4.15. Si8935 Total Harmonic Distortion (dB) vs.
Temperature (°C)
-50
-60
-60
-70
THD (dB)
THD (dB)
-70
-80
-80
-90
-90
-100
-100
-110
3.0
3.5
4.0
4.5
VDDA Supply (V)
5.0
5.5
Figure 4.16. Si8935 Total Harmonic Distortion (dB) vs.
VDDA Supply (V)
16
0.0
0.5
1.0
1.5
Input Signal Amplitude (Vpp)
2.0
2.5
Figure 4.17. Si8935 Total Harmonic Distortion vs. Input
Signal Amplitude (mV)
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-50
-50
-60
-60
-70
-70
THD (dB)
THD (dB)
Si8935/36/37 Data Sheet • Electrical Specifications
-80
-80
-90
-90
-100
-100
-110
-110
Input Signal Frequency (kHz)
15
MCLK (MHz)
Figure 4.18. Si8935 Total Harmonic Distortion vs. Input
Signal Frequency (kHz)
Figure 4.19. Si8935 Total Harmonic Distortion vs. MCLK
(MHz)
5
5.0
3
3
2
2
1
1
Input Offset (mV)
Input Offset (mV)
1.0
0
-1
-2
25
0
-1
-3
5
10
15
MCLK (MHz)
20
25
-40
Figure 4.20. Si8935 Input Offset (mV) vs. MCLK (MHz)
3
12
2
10
1
8
0
4
-2
2
3.0
3.5
4.0
Si8935
4.5
VDDA (V)
Si8936
5.0
5.5
0
20
40
60
80
Temperature (˚C)
Si8935
Si8936
Si8937
100
120
6
-1
-3
-20
Figure 4.21. Input Offset (mV) vs. Temperature (°C)
IDDA (mA)
Input Offset (mV)
20
-2
-3
0
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
Si8937
Figure 4.22. Input Offset (mV) vs. VDDA Supply (V)
17
10
Figure 4.23. Si8935/36/37 IDDA (mA) vs. Temperature (C)
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12
12
10
10
8
8
IDDB (mA)
IDDB (mA)
Si8935/36/37 Data Sheet • Electrical Specifications
6
6
4
4
2
2
0
-40
-20
0
20
40
60
Temperature (˚C)
80
100
0
120
5
0.3
0.3
0.2
0.2
0.1
0.1
0
-0.1
-0.2
-0.2
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
20
25
0
-0.1
-0.3
15
MCLK (MHz)
Figure 4.25. Si8935 IDDB (mA) vs. MCLK (MHz)
Gain Error (%)
Gain Error (%)
Figure 4.24. Si8935 IDDB (mA) vs. Temperature (C)
10
-0.3
5.0
Figure 4.26. Si8935 Gain Error (%) vs. Temperature (C)
10.0
15.0
MCLK (MHz)
20.0
25.0
Figure 4.27. Si8935 Gain Error (%) vs. MCLK (MHz)
30
11
25
Internal Clock (MHz)
Internal Clock (MHz)
10.5
10
20
15
10
9.5
5
9
0
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
Figure 4.28. Si8936 Internal Clock Frequency (MHz) vs.
Temperature (C)
18
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
Figure 4.29. Si8937 Internal Clock Frequency (MHz) vs.
Temperature (C)
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Si8935/36/37 Data Sheet • Electrical Specifications
30
Internal Clock (MHz)
25
20
15
10
5
0
-40
-20
0
20
40
60
Temperature (˚C)
80
100
120
Figure 4.30. Si8935 Power Supply Rejection Ratio (dB) vs.
Input Signal Frequency (kHz)
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Si8935/36/37 Data Sheet • Pin Descriptions
5. Pin Descriptions
VDDA
1
VIN
2
NC
3
GNDA
4
Si8935
Si8936
Si8937
8
VDDB
7
ACLK
6
ADAT
5
GNDB
Table 5.1. Si8935/36/37 Pin Descriptions
Name
Pin #
Description
VDDA
1
Input side power supply
VIN
2
Voltage input
NC1
3
No Connect
GNDA
4
Input side ground
GNDB
5
Output side ground
ADAT
6
Delta-sigma modulator data output
ACLK
7
Delta-sigma modulator clock (input on Si8935, output on Si8936/37)
VDDB
8
Output side power supply
Note:
1. No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be connected to the
ground plane.
20
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Si8935/36/37 Data Sheet • Packaging
6. Packaging
6.1 Package Outline: 8-Pin Wide Body Stretched SOIC
The figure below illustrates the package details for the Si8935/36/37 in a 8-Pin Wide Body Stretched SOIC package. The table lists the
values for the dimensions shown in the illustration.
Figure 6.1. 8-Pin Wide Body Stretched SOIC Package
Table 6.1. 8-Pin Wide Body Stretched SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
2.49
2.79
A1
0.36
0.46
b
0.30
0.51
c
0.20
0.33
D
5.74
5.94
E
11.25
11.76
E1
7.39
7.59
e
21
1.27 BSC
L
0.51
1.02
h
0.25
0.76
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Si8935/36/37 Data Sheet • Packaging
Symbol
Millimeters
Min
Max
θ
0°
8°
aaa
—
0.25
bbb
—
0.25
ccc
—
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Si8935/36/37 Data Sheet • Packaging
6.2 Package Outline: 8-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si8935/36/37 in an 8-Pin Narrow Body SOIC package. The table lists the values
for the dimensions shown in the illustration.
Figure 6.2. 8-Pin Narrow Body SOIC Package
Table 6.2. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
23
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
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Si8935/36/37 Data Sheet • Packaging
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. This drawing conforms to JEDEC Outline MS-012.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body Components.
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Si8935/36/37 Data Sheet • Packaging
6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC
The figure below illustrates the recommended land pattern details for the Si8935/36/37 in a 8-Pin Wide Body Stretched SOIC package.
The table lists the values for the dimensions shown in the illustration.
Figure 6.3. 8-Pin Wide Body Stretched SOIC Land Pattern
Table 6.3. 8-Pin Wide Body Stretched SOIC Land Pattern Dimensions1
Dimension
(mm)
C1
10.60
E
1.27
X1
0.60
Y1
1.85
Note:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
25
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Si8935/36/37 Data Sheet • Packaging
6.4 Land Pattern: 8-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si8935/36/37 in an 8-Pin Narrow Body SOIC package. The
table lists the values for the dimensions shown in the illustration.
Figure 6.4. 8-Pin Narrow Body SOIC Land Pattern
Table 6.4. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Symbol
mm
C1
5.40
E
1.27
X1
0.60
Y1
1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
26
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Si8935/36/37 Data Sheet • Packaging
6.5 Top Marking: 8-Pin Wide Body Stretched SOIC
The figure below illustrates the top markings for the Si8935/36/37 in an 8-Pin Wide Body Stretched SOIC package. The table explains
the top marks shown in the illustration.
S i 8 9 3 X V
TTTT TT
Y Y WW
Figure 6.5. Si893x Wide Body Stretched 8-Pin SOIC Top Marking
Table 6.5. Si893x Wide Body Stretched 8-Pin SOIC Top Mark Explanation
Si893X
Line 1 Marking:
Customer Part Number
X = Base part number
• 5 = External clock
• 6 = Internal 10 MHz clock
• 7 = Internal 20 MHz clock
V = Insulation rating:
• D = 5.0 kVrms
Line 2 Marking:
TTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase Order form.
YY = Year
Line 3 Marking:
WW = Work Week
Circle = 43 mils Diameter
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
Left-Justified
27
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Si8935/36/37 Data Sheet • Packaging
6.6 Top Marking: 8-Pin Narrow Body SOIC
The figure below illustrates the top markings for the Si8935/36/37 in an 8-Pin Narrow Body SOIC package. The table explains the top
marks shown in the illustration.
S i 8 9 3XV
CC
Y Y WW
TTTT TT
Figure 6.6. 8-Pin Narrow Body SOIC Top Marking
Table 6.6. 8-Pin Narrow Body SOIC Top Marking Explanation
Si893X
Line 1 Marking:
Customer Part Number
X = Base part number
• 5 = External clock
• 6 = Internal 10 MHz clock
• 7 = Internal 20 MHz clock
V = Insulation rating:
• B = 2.5 kVrms
CC = Country of Origin ISO Code Abbreviation
Line 2 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
TTTTTT = Mfg Code
Line 3 Marking:
Circle = 19.7 mils Diameter
Manufacturing Code from the Assembly Purchase Order form.
Left-Justified
28
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Si8935/36/37 Data Sheet • Revision History
7. Revision History
Revision 0.7
April, 2021
• Updated Applications and Key Features on front page.
• Added Automotive OPNs to 1. Ordering Guide.
• Updated Table 4.6 Insulation and Safety-Related Specifications on page 13.
• Updated 4. Electrical Specifications after full characterization.
• Updated narrow body top marking.
• Numerous clarifications throughout.
Revision 0.1
March, 2019
• Initial release.
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