Si53340-45 Data Sheet
Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Outputs from Any-Format Input and Wide Frequency Range from dc
up to 1250 MHz
KEY FEATURES
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and redundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and
operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high
PSRR performance and reduces the need for external components simplifying low jitter
clock distribution in noisy environments.
They are available in multiple configurations and offer a selectable input clock using a
2:1 input mux. Other features include independent output enable and built-in format
translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to
deliver end-to-end clock tree performance.
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVDS Outputs
• Any-format Inputs (LVPECL, Low-Power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• 2:1 Input Mux
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
4
Power Supply
Filtering
4 Outputs
Si53340/41
VDDOA
OEAb
CLK0*
3
0
3 Outputs
Si53342/43
CLK1*
3
1
3 Outputs
OEBb
VDDOB
CLK_SEL
10
10 Outputs
Si53344/45
*Si53341/43/45 require Single-ended Inputs
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Si53340-45 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si5334x Ordering Guide
Part Number
Input
LVDS Output
Output Enable (OE)
Frequency Range
Package
SI53340-B-GM
2:1 selectable MUX
Any-format
1 bank / 4 Outputs
—
dc to 1250 MHz
16-QFN
3 x 3 mm
SI53341-B-GM
2:1 selectable MUX
LVCMOS
1 bank / 4 Outputs
—
dc to 200 MHz
16-QFN
3 x 3 mm
SI53342-B-GM
2:1 selectable MUX
Any-format
2 banks / 3 Outputs
1 per bank
dc to 1250 MHz
24-QFN
4 x 4 mm
SI53343-B-GM
2:1 selectable MUX
LVCMOS
2 banks / 3 Outputs
1 per bank
dc to 200 MHz
24-QFN
4 x 4 mm
SI53344-B-GM
2:1 selectable MUX
Any-format
1 bank / 10 Outputs
—
dc to 1250 MHz
32-QFN
5 x 5 mm
SI53345-B-GM
2:1 selectable MUX
LVCMOS
1 bank / 10 Outputs
—
dc to 200 MHz
32-QFN
5 x 5 mm
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Si53340-45 Data Sheet
Functional Description
2. Functional Description
The Si53340-45 are a family of low-jitter, low skew, fixed format (LVDS) buffers. The Si53340/42/44 have a universal input that accepts
most common differential or LVCMOS input signals, while the Si53341/43/45 accept only LVCMOS inputs. These devices are available
in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53340/42/44)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, Low-power LVPECL, LVDS,
CML, HCSL, and LVCMOS. The tables below summarize the various ac- and dc-coupling options supported by the device. For the best
high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest
possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 2.1. Clock Input Options
Clock Format
1.8 V
2.5/3.3 V
LVPECL/Low-power LVPECL
N/A
Yes
LVCMOS
No
Yes
LVDS
Yes
Yes
HCSL
No
Yes (3.3 V)
CML
Yes
Yes
LVPECL/Low-power LVPECL
N/A
Yes
LVCMOS
No
Yes
LVDS
No
Yes
HCSL
No
Yes (3.3 V)
CML
No
No
AC-Coupled
DC-Coupled
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Si53340-45 Data Sheet
Functional Description
VDD
0.1 µF
Si53340/42/44
CLKx
100
CLKxb
0.1 µF
Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination
VDD
DC-Coupled
VDD = 3.3 V or 2.5 V
CMOS
Driver
VDD
1k
Si53340/42/44
CLKx
50
CLKxb
Rs
VTERM = VDD/2
1k
VDD
VDD
AC-Coupled
1k
VBIAS = VDD/2
VDD = 3.3 V or 2.5 V
CMOS
Driver
VDD
1k
Si53340/42/44
CLKx
50
CLKxb
Rs
1k
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
1k
VTERM = VDD/2
Figure 2.2. Single-Ended (LVCMOS) Input Termination
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Si53340-45 Data Sheet
Functional Description
VDD
DC Coupled LVPECL Input Termination Scheme 1
R1
VDD
R1
VDD = 3.3 V or 2.5 V
Si53340/42/44
CLKx
50
“Standard”
LVPECL
Driver
CLKxb
50
R2
VTERM = VDD – 2V
R1 // R2 = 50 Ohm
R2
3.3 V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5 V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
DC Coupled LVPECL Input Termination Scheme 2
VDD
VDD = 3.3 V or 2.5 V
Si53340/42/44
50
“Standard”
LVPECL
Driver
CLKx
CLKxb
50
50
50
VTERM = VDD – 2 V
DC Coupled LVDS Input Termination
VDD
VDD = 3.3 V or 2.5 V
Si53340/42/44
CLKx
50
Standard
LVDS
Driver
100
CLKxb
50
DC Coupled HCSL Input Termination Scheme
VDD = 3.3 V
VDD
Si53340/42/44
33
50
Standard
HCSL Driver
CLKx
CLKxb
33
50
50
50
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 2.3. Differential DC-Coupled Input Terminations
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Si53340-45 Data Sheet
Functional Description
2.2 LVCMOS Input Termination (Si53341/43/45)
The table below summarizes the various ac- and dc-coupling options supported by the LVCMOS device, and the figure shows the recommended input clock termination.
Note: 1.8V LVCMOS inputs are not supported for Si53341/43/45.
Table 2.2. LVCMOS Input Clock Options
LVCMOS
AC-Coupled
DC-Coupled
1.8 V
No
No
2.5/3.3 V
Yes
Yes
VDD = 3.3 V or 2.5 V
CMOS
Driver
VDD
DC-Coupled
Si53341/43/45
CLKx
50
Rs
NC
VDD
1k
VDD = 3.3 V or 2.5 V
CMOS
Driver
VDD
AC-Coupled
Si53341/43/45
CLKx
50
Rs
NC
1k
VBIAS = VDD/2
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
Figure 2.4. Recommended Input Clock Termination (Si53341/43/45)
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Si53340-45 Data Sheet
Functional Description
2.3 Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting
input is biased with a 18.75 kΩ pull-down to GND and a 75 kΩ pull-up to VDD. The inverting input is biased with a 75 kΩ pull-up to VDD.
VDD
RPU
CLK0 or
CLK1
RPU
+
RPD
–
RPU = 75 k
RPD = 18.75 k
Figure 2.5. Input Bias Resistors
Note: To minimize the possibility of system noise coupling into the Si5334x differential inputs and adversely affecting the buffered output, Silicon Labs recommends 1 PPS clocks and disabled/gapped clocks be DC-coupled and driven “stop-low” .
2.4 Input Mux
The Si5334x provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects
the active clock input. The following table summarizes the input and output clock based on the input mux and output enable pin settings.
Table 2.3. Input Mux Logic
CLK_SEL
CLK0
CLK1
Q1
Qb
L
L
X
L
H
L
H
X
H
L
H
X
L
L
H
H
X
H
H
L
Note:
1. On the next negative transition of CLK0 or CLK1.
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Si53340-45 Data Sheet
Functional Description
2.5 Output Clock Termination Options
The recommended output clock termination options are shown below. Unused outputs should be left unconnected.
DC Coupled LVDS Termination
VDDXX
Si5334x
VDD
50
Q
LVDS
Receiver
100
Qb
50
AC Coupled LVDS Termination
VDDXX
Si5334x
0.1 µF
Q
VDD
50
100
Qb
50
LVDS
Receiver
0.1 µF
Note:
For Si53340/41/44/45, VDDXX = VDD = 3.3 V, 2.5 V, 1.8 V
For Si53342/43, VDDXX = VDDOA or VDDOB = 3.3 V, 2.5 V, 1.8 V
Figure 2.6. LVDS Output Terminations
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Si53340-45 Data Sheet
Functional Description
2.6 AC Timing Waveforms
TPHL
CLK
TSK
QN
VPP/2
Q
VPP/2
QM
VPP/2
VPP/2
TPLH
TSK
Propagation Delay
Output-Output Skew
TF
Q
80% VPP
20% VPP
80% VPP
Q
20% VPP
TR
Rise/Fall Time
Figure 2.7. AC Timing Waveforms
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Si53340-45 Data Sheet
Functional Description
2.7 Typical Phase Noise Performance: Differential Input Clock
Each of the three phase noise plots superimposes Source Jitter, Total SE Jitter and Total Diff Jitter on the same diagram.
• Source Jitter—Reference clock phase noise (measured Single-ended to PNA).
• Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz.
• Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer
and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more information, see 3. Electrical Specifications.
Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).
Total jitter
measured here
CLKx
CLK SYNTH
SMA103A
Si5334x
DUT
AG E5052 Phase Noise
Analyzer
50
50 Ohm
Source jitter
measured here
Figure 2.8. Differential Measurement Method Using a Balun
The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition).
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter
(fs)
Total Jitter
(SE) (fs)
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
156.25
1.0
38.2
147.8
142.8
118.3
112.0
Figure 2.9. Total Jitter Differential Input (156.25 MHz)
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Si53340-45 Data Sheet
Functional Description
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter
(fs)
Total Jitter
(SE) (fs)
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
312.5
1.0
33.10
94.39
88.39
83.80
76.99
Figure 2.10. Total Jitter Differential Input (312.5 MHz)
Frequency
(MHz)
Differential
Input Slew Rate (V/ns)
Source Jitter
(fs)
Total Jitter
(SE) (fs)
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
625
1.0
23
57
52
59
54
Figure 2.11. Total Jitter Differential Input (625 MHz)
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Si53340-45 Data Sheet
Functional Description
2.8 Typical Phase Noise Performance: Single-Ended Input Clock
For single-ended input phase noise measurements, the input was connected directly without the use of a balun.
The following figure shows three phase noise plots superimposed on the same diagram.
Frequency
(MHz)
Single-Ended
Input Slew Rate (V/ns)
Source Jitter
(fs)
Total Jitter
(SE) (fs)
Additive Jitter
(SE) (fs)
Total Jitter
(Differential) (fs)
Additive Jitter
(Differential) (fs)
156.25
1.0
40.74
182.12
177.51
125.22
118.41
Figure 2.12. Total Jitter Single-Ended Input (156.25 MHz)
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Si53340-45 Data Sheet
Functional Description
2.9 Input Mux Noise Isolation
The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when
clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation.
Figure 2.13. Input Mux Noise Isolation (Differential Input Clock, 44-QFN Package)
Figure 2.14. Input Mux Noise Isolation (Single-Ended Input Clock, 24-QFN Package)
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Si53340-45 Data Sheet
Functional Description
2.10 Power Supply Noise Rejection
The device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements.
See “AN491: Power Supply Rejection for Low-Jitter Clocks” for more information.
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Si53340-45 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. Recommended Operating Conditions
Parameter
Symbol
Ambient Operating Temperature
TA
Supply Voltage Range
Test Condition
VDD
LVDS
Min
Typ
Max
Unit
–40
—
85
°C
1.71
1.8
1.89
V
2.38
2.5
2.63
V
2.97
3.3
3.63
V
Min
Typ
Max
Unit
Table 3.2. Input Clock Specifications
VDD = 1.8 V, 2.5 V, or 3.3 V; TA = –40 to 85 °C
Parameter
Symbol
Test Condition
Differential Input Common
Mode Voltage
VCM
0.05
—
—
V
Differential Input Swing (peakto-peak)
VIN
0.2
—
2.2
V
Input High Voltage
VIH
VDD x 0.7
—
—
V
Input Low Voltage
VIL
—
—
VDD x 0.3
V
Input Capacitance
CIN
—
5
—
pF
Test Condition
Min
Typ
Max
Unit
Si53340/41
—
140
—
mA
Si53342/43
—
80
—
mA
Si53344/45
—
280
—
mA
CLK0 and CLK1 pins with respect to GND
Table 3.3. DC Common Characteristics
VDD = 1.8 V, 2.5 V, or 3.3 V; TA = –40 to 85 °C
Parameter
Core Supply Current
Symbol
IDD1
Output Supply Current
(Per Clock Output)
IDDO1
Si53342/43
—
21
—
mA
Input High Voltage
VIH
CLK_SEL, OEAb, OEBb
VDD x 0.8
—
—
V
Input Low Voltage
VIL
CLK_SEL, OEAb, OEBb
—
—
VDD x 0.2
V
Internal Pull-down Resistor
RDOWN
CLK_SEL, OEAb, OEBb
—
25
—
kΩ
Note:
1. Measured using ac-coupled termination at VDD/VDDOX = 3.3 V.
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Si53340-45 Data Sheet
Electrical Specifications
Table 3.4. Output Characteristics (LVDS)
VDD = 1.8 V, 2.5 V, or 3.3 V; TA = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Output Swing1
VSE
RL = 100 Ω across QN and QbN
200
—
490
mV
Output Common Mode Voltage
(VDD = 2.5 or 3.3 V)
VCOM1
VDD = 2.38 to 2.63 V, 2.97 to 3.63 V,
RL = 100 Ω across QN and QbN
1.10
1.25
1.35
V
0.83
0.97
1.25
V
Test Condition
Min
Typ
Max
Unit
Si53341/43/45
dc
—
200
MHz
Si53340/42/44
dc
—
1250
MHz
20/80% TR/TF