S i53 3 4
P I N -C O N T R O L L E D A N Y - F R E Q U E N C Y, A N Y -O U T P U T Q U A D
CLOCK GENERATOR
Features
Low-power MultiSynth technology
enables independent, any-frequency
synthesis on four differential output
drivers
Highly-configurable output drivers
support up to four differential outputs
or eight single-ended clock outputs or
a combination of both
Low phase jitter: 0.7 ps RMS typ
High-precision synthesis allows true
0 ppm frequency accuracy on all
outputs
Flexible input reference
External
crystal: 8 to 30 MHz
input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Differential input: 5 to 710 MHz
CMOS
Independently-configurable outputs
support any frequency or format
LVPECL/LVDS:
0.16 to 710 MHz
0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
HCSL:
Independent output voltage per driver
1.5,
1.8,
1.8, 2.5, or 3.3 V
Independent core supply voltage
2.5, or 3.3 V
Frequency increment/decrement
feature enables glitchless frequency
adjustments in 1 ppm steps
Phase adjustment on each of the
output drivers with 5 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
Rev. 1.3
11
Si5 334
Table 10. Jitter Specifications1,2,3 (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
3
15
ps pk-pk
—
2
10
ps pk-pk
Output MultiSynth
operated in fractional
mode7
—
13
36
ps pk-pk
Output MultiSynth
operated in integer
mode7
—
12
20
ps pk-pk
Output MultiSynth
operated in fractional
Deterministic Jitter
mode7
DJ
Output MultiSynth
operated in integer
7
mode
Total Jitter
(12 kHz–20 MHz)
TJ = DJ+14xRJ
(See Note 9)
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver.1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
Table 11. Typical Phase Noise Performance
12
Offset Frequency
25MHz XTAL
to 156.25 MHz
27 MHz Ref In
to 148.3517 MHz
19.44 MHz Ref In
to 155.52 MHz
Units
100 Hz
–90
–87
–110
dBc/Hz
1 kHz
–120
–117
–116
dBc/Hz
10 kHz
–126
–123
–123
dBc/Hz
100 kHz
–132
–130
–128
dBc/Hz
1 MHz
–132
–132
–128
dBc/Hz
10 MHz
–145
–145
–145
dBc/Hz
Rev. 1.3
Si5334
Table 12. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
JA
Still Air
37
°C/W
Thermal Resistance Junction to Case
JC
Still Air
25
°C/W
Test Condition
Value
Unit
Table 13. Absolute Maximum Ratings1
Parameter
Symbol
DC Supply Voltage
VDD
–0.5 to 3.8
V
Storage Temperature Range
TSTG
–55 to 150
°C
ESD Tolerance
HBM
(100 pF, 1.5 k)
2.5
kV
ESD Tolerance
CDM
550
V
ESD Tolerance
MM
175
V
Latch-up Tolerance
Junction Temperature
JESD78 Compliant
TJ
Peak Soldering Reflow Temperature2
150
°C
260
°C
Notes:
1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. Refer to JEDEC J-STD-020 standard for more information.
Rev. 1.3
13
Si5 334
2. Functional Description
2.1. Overview
Figure 1. Si5334 Block Diagram
The Si5334 is a high-performance, low-jitter clock
generator capable of synthesizing any frequency on
each of the device's four differential output clocks. The
device accepts an external crystal from 8 to 30 MHz or
an input clock ranging from 5 to 710 MHz. Each output
is independently factory-programmable to any
frequency up to Fvco/8 (max of 350 MHz) and select
frequencies to 710 MHz.
The Si5334 fractional-N PLL, comprised of a phase
detector, charge pump, loop filter, VCO, and dividers, is
fully integrated on chip to simplify design. Using Silicon
Labs' patented MultiSynth technology, each output
clock is generated with low jitter and zero ppm
frequency error. The device has four MultiSynth output
dividers to provide non-integer frequency synthesis on
every differential output clock.
The Si5334 output driver is highly flexible. The signal
format of each output clock can be user-specified to
support LVPECL, LVDS, HCSL, CMOS, HSTL, or SSTL.
Each output clock has its own supply voltage to allow
for the utmost flexibility in mixed supply operations. The
core of the Si5334 has its own supply voltage that can
be 1.8, 2.5, or 3.3 V.
14
The Si5334 supports an optional zero delay mode of
operation. In this mode, one of the device output clocks
is fed back to the FDBK/FDBKB clock input pins to
implement the PLL feedback path and nullify the phase
difference between the reference input and the output
clocks.
The Si5334D/E/F has a pin-controlled phase increment/
decrement feature that allows the user to adjust the
phase of each output clock in relation to the other output
clocks. The phase of each differential output clock can
be set to an accuracy of 20 ps over a range of ±45 ns.
This feature is available over the 0.16 to Fvco/8 MHz
frequency range at a maximum rate of phase change of
1.5 MHz.
The Si5334G/H/J has a pin-controlled frequency
increment/decrement feature that allows the user to
change frequency in steps as small as 1 ppm of the
initial frequency to as large as possible as long as the
frequency at the output of the MultiSynth stays within
the range of 5 MHz to Fvco/8 MHz. This feature is
available on CLK0A/B only. The frequency step is
glitchless. This feature is useful in applications that
require a variable clock frequency. It can also be used in
frequency margining applications to margin test system
clocks during design/verification/test or manufacturing
test applications.
For EMI reduction, the Si5334K/L/M supports PCI
Express 2.0 compliant spread spectrum on all output
clocks that are 100 MHz.
Rev. 1.3
Si5334
The Si5334 is pin-controlled. No I2C interface is
provided. The LOLLOS output pin indicates the lock
condition of the PLL. An output enable input pin is
available on the Si5334A/B/C which affects all the
programmed clock outputs. All device specifications are
guaranteed across these three core supply voltages.
Packaged in a ROHS-6, Pb-free 4x4 mm QFN package,
the device supports the industrial temperature range of
–40 to +85 °C.
After core power is applied, the Si5334 downloads the
factory-programmed NVM into RAM and begins
operation.
2.2. Crystal/Clock Input
The device can be driven from either a low frequency
fundamental mode crystal (8–30 MHz) or an external
reference clock (5–710 MHz). The crystal is connected
across pins IN1 and IN2.
The PCB traces between the crystal and the device
must be kept very short to minimize stray capacitance.
To ensure maximum compatibility with crystals from
multiple vendors, the internal crystal oscillator provides
adaptive crystal drive strength based upon the crystal
frequency.
The crystal load capacitors are placed on-chip to reduce
external component count. If a crystal with a load
capacitance outside the range specified in Tables 2, 3,
and 12 is supplied to the device, it will result in a slight
ppm error in the device clock output frequencies. This
error can be compensated for by a small change in the
input to output multiplication ratio.
If a reference clock is used, the device accepts a singleended input reference on IN3 or a differential LVPECL,
LVDS, or HCSL source on IN1 and IN2. The input at IN3
can accept an input frequency up to 200 MHz. The
signal applied at IN3 should be dc-coupled because
internally this signal is ac-coupled to the receive input. A
single-ended reference clock up to 350 MHz can be accoupled to IN1. A differential reference clock, such as
LVPECL, LVDS or HCSL, is input on IN1,2 for
frequencies up to 700 MHz. The differential input to
IN1,2 requires 0.1 μF ac coupling caps to be located
near the device and a 100 termination resistor to be
located between these caps and the transmission line
going back to the differential driver. See “AN408:
Termination Options for Any-Frequency, Any-Output
Clock Generators and Clock Buffers” for more
information on connecting input signals to IN1,2,3. This
application
note
can
be
downloaded
from
www.silabs.com/timing.
2.3. Zero Delay Mode
A clock that is input to the Si5334 will have an
unspecified amount of delay from the input pins to the
output pins. The zero delay mode can be used to
reduce the delay through the Si5334 to typically less
than 100 ps. This is accomplished by feeding back the
CLK3 output to either IN4 or IN5,6. Using CLK3 allows
for an easy PCB route of this signal back to the input.
The R3 divider must be set to 1 when using feedback
from CLK3 to implement the zero delay mode. All output
clocks that are required to have zero delay must also
have their Rn divider set to 1. A single-ended signal up
to 200 MHz from CLK3 can be input to IN4. A singleended signal up to 350 MHz from CLK3 can be input to
IN5 using the technique shown in AN408. A differential
signal up to 710 MHz from CLK3a,b must be input to
IN5,IN6.
The IN4 input is electrically the same as IN3 described
above. The IN5,IN6 inputs are electrically the same as
the IN1,IN2 inputs described above. See AN408 for
additional information on signal connections for the zero
delay mode.
2.4. Breakthrough MultiSynth Technology
Next-generation timing IC architectures require a wide
range of frequencies which are often non-integer
related. Traditional clock architectures address this by
using multiple single PLL ICs, often at the expense of
BOM complexity and power. The Si5334 and Si5338
use patented MultiSynth technology to dramatically
simplify timing architectures by integrating the
frequency synthesis capability of 4 Phase-Locked
Loops (PLLs) in a single device, greatly minimizing size
and power requirements versus traditional solutions.
Based on a fractional-N PLL, the heart of the
architecture is a low phase noise, high frequency VCO.
The VCO supplies a high frequency output clock to the
MultiSynth block on each of the four independent output
paths. Each MultiSynth operates as a high speed
fractional divider with Silicon Labs' proprietary phase
error correction to divide down the VCO clock to the
required output frequency with very low jitter.
The first stage of the MultiSynth architecture is a
fractional-N divider which switches seamlessly between
the two closest integer divider values to produce the
exact output clock frequency with 0 ppm error. To
eliminate phase error generated by this process,
MultiSynth calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
Rev. 1.3
15
Si5 334
Based on this architecture, the output of each
MultiSynth can produce any frequency from 5 to Fvco/8
MHz. To support higher frequency operation, the
MultiSynth divider can be bypassed. In bypass mode
integer divide ratios of 4 and 6 are supported, which
allows for output frequencies of Fvco/4 and Fvco/6 MHz
which translates to 367–473.3 MHz and 550–710 MHz
respectively. Because each MultiSynth uses the same
VCO output there are output frequency limitations when
output frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz.
Only two unique frequencies above Fvco/8 can be
output: Fvco/6 and Fvco/4.
2.5. Output Driver
There are four clock output channels on the Si5334
(CLK0,CLK1,CLK2,CLK3) with two signal outputs per
channel. Each channel may be programmed to be a
differential driver or a dual single ended driver. If a
channel is factory-programmed to be single ended, then
the two outputs for that channel can be factoryprogrammed to be in-phase or out-of-phase. Si5334
output drivers can be configured as single ended
CMOS, SSTL, HSTL or differential LVPECL, LVDS, and
HCSL formats.
The supply voltage requirement for each driver format is
selectable as shown in Table 14. All unused clock
output channels must have their respective VDD0x
supply voltage connected to pin 7 and 24 VDD.
Figure 2. Silicon Labs’ MultiSynth Technology
Table 14. Output Driver Signal Format Selection
VDD0x
Supply
Voltage
CMOS
SSTL
1.5
16
HSTL
LVPECL
LVDS
HCSL
X
X
X
1.8
X
X
2.5
X
X
X
X
X
3.3
X
X
X
X
X
Rev. 1.3
Si5334
An OEB pin is provided to enable/disable the output
clocks. When OEB = 0, all outputs that have been
factory programmed will be on. When OEB = 1, all clock
outputs that have been factory programmed will be off
and held to a low level.
2.6. Output Clock Initial Phase Offset
Each CLKn output of the Si5334 can have its own
unique initial phase offset over a range of +- 45 ns with
an accuracy of 20 ps. When the respective R divider is
not set to 1, this function is not supported.
2.7. Output Clock Phase Increment and
Decrement
The Si5334D/E/F has a pin-controlled phase increment/
decrement feature that allows the user to adjust the
phase of 1 or more output clocks via pin control. Since
their is only 1 pin for increment and 1 pin for decrement,
each output clock channel needs to be enabled or
disabled for this feature. In addition, the magnitude of
the phase step must be set for each clock output
channel. The phase adjustment accuracy is 20 ps over
a range of ±45 ns, and the phase transition is glitchless.
This feature is not available on any clock output that has
Spread Spectrum enabled. The maximum clock output
frequency supported in this mode of operation is Fvco/
8, where Fvco is the frequency of the device's internal
voltage controlled oscillator for the configured frequency
plan. The phase can be changed at a maximum rate of
1.5 MHz. In order to increment or decrement phase it is
necessary to input a positive pulse of >100ns followed
by a low of >100 ns. Since this feature uses pins 3 and
4, the reference clock must be input at pins 1 and 2 or
the crystal used across these pins. Once a Si5334/D/E/
F is factory-programmed, the phase increment/
decrement parameters cannot be changed. If one
desires to subsequently change the phase increment/
decrement parameters on a factory-programmed part,
the Si5338 clock generator must be used.
If a phase decrement causes a single MultiSynth clock
period to be less than 8/Fvco, all clock outputs may turn
off for up to 10 clock periods and then come back on
with the phase setting before the illegal decrement.
2.8. Output Clock Frequency Increment
and Decrement
The Si5334G/H/J has a pin-controlled frequency
increment/decrement feature that allows the user to
adjust the frequency at the output of MultiSynth0 only.
MultiSynth0 can be connected to any or all of the four
output clock buffers with the muxes shown in the
" Functional Block Diagram" on page 2. If frequency
increment and decrement is required on the other clock
outputs the Si5338 should be used. The magnitude of a
single frequency step must be factory-programmed.
Spread Spectrum and frequency increment/decrement
cannot both be active on the same clock output. There
is a single pin to control the frequency increment and a
single pin to control the frequency decrement. The
frequency increment or decrement step size can be
factory-programmed from as low as 1 ppm of the initial
frequency to a maximum that keeps the output of the
MultiSynth within the limits of 5 MHz to Fvco/8. If a
frequency increment causes the MultiSynth0 output
frequency to go above Fvco/8, then all output clocks
may turn off for up to 10 clock cycles and then come
back on at the frequency before the increment. If the
output frequency needs to go below 5 MHz, refer to
"2.9. R Divider Considerations" on page 17 for further
information. The frequency transition is glitchless. The
frequency can be changed at a maximum rate of
1.5 MHz. In order to increment or decrement frequency
it is necessary to input a positive pulse of >100 ns
followed by a low of > 100 ns. Since this feature uses
pins 3 and 4, the reference clock must be input at pins 1
and 2 or the crystal used across these pins. Once a
Si5334/G/H/J is factory-programmed, the frequency
increment/decrement parameters cannot be changed. If
one desires to subsequently change the frequency
increment/decrement parameters on a programmed
part, the Si5338 clock generator must be used.
2.9. R Divider Considerations
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider will
automatically be set and enabled. When the Rn divider
is active the step size range of the frequency increment
and decrement function will decrease by the Rn divide
ratio. The Rn divider can be set to {1, 2, 4, 8, 16, 32}.
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase of the CLKn output with
respect to other CLKn outputs is not guaranteed.
Rev. 1.3
17
Si5 334
2.10. Spread Spectrum
2.11. Device Reset
To reset the device, a power cycle must be performed.
2.12. LOSLOL Pin
Figure 3. Spread Spectrum Triangle Waveform
To reduce the electromagnetic interference (EMI), the
Si5334K/L/M supports PCI Express compliant spread
spectrum on all outputs that are 100 MHz. If CLK0 has
spread spectrum enabled, then the Finc/Fdec function
is not available on CLK0. Spread spectrum modulation
spreads the energy across many frequencies to reduce
the EMI across a narrow range of frequencies.
The modulation rate is the time required to transition
from the maximum spread spectrum frequency to the
minimum spread spectrum frequency and then back to
the maximum frequency as shown in Figure 3.
The Si5334K/L/M supports 0.5% downspread at a 30–
33 kHz rate with a clock frequency of 100 MHz in
compliance with the PCI Express standard. When pin
12 (SSPB) is low the factory-programmed clock outputs
will have spread spectrum turned on.
18
When either a Loss of Lock (LOL) or Loss of Signal
(LOS) condition occurs, the LOSLOL pin will assert.
The LOS condition occurs when there is no input clock
input to the Si5334. The loss of lock algorithm works by
continuously monitoring the frequency difference
between the two inputs of the phase frequency detector.
When this frequency difference is greater than
1000 ppm, a loss of lock condition is declared. Note that
the VCO will track the input clock frequency for up to
~50000 ppm, which will keep the inputs to the phase
frequency detector at the same frequency until the PLL
comes out of lock. When a clock input is removed, the
LOSLOL pin will assert, and the clock outputs may drift
up to 5%. When the input clock with an appropriate
frequency is re-applied, the PLL will again lock.
2.13. Power-Up
Upon powerup, the device performs an internal selfcalibration before operation to optimize loop parameters
and jitter performance. While the self-calibration is
being performed, the device VCO is being internally
controlled by the self-calibration state machine and the
LOL alarm is masked. The output clocks appear after
the device finishes self calibration.
2.14. Factory Programming Options
Silicon Labs Si5334 clock generators are factoryprogrammable devices. The functions and frequency
plans can be customized to meet the needs of your
applications. Contact your local Silicon Labs sales
representative.
Refer to www.silabs.com/ClockBuilder to access
downloadable software to configure the Si5334.
Rev. 1.3
Si5334
3. Pin Descriptions
Note: Center pad must be tied to GND for normal operation.
Table 15. Si5334 Pin Descriptions
Pin #
1,2
Pin Name
IN1/IN2
I/O
I
Signal Type
Description
Multi
CLKIN/CLKINB.
These pins are used as the main differential clock input
or as the XTAL input. Clock inputs to these pins must be
ac-coupled. A crystal should be directly connected to
pins 1,2 with the shortest traces possible. Keep the
traces from pins 1,2 to the crystal as short as possible
and keep other signals and radiating sources away from
the crystal.
When not in use, leave IN1 unconnected and IN2
connected to GND.
Rev. 1.3
19
Si5 334
Table 15. Si5334 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
Keep the input level > –0.1 V and < VDD+.1 V.
3
IN3
I
Multi
REFCLKSE
High impedance input for single-ended clock signals
such as CMOS. The input should be dc-coupled.
PINC
This pin function is active for devices Si5334D/E/F. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will increase the input to output device
latency by a factory-programmed amount. The function
of this pin is factory programmed.
FINC
This pin function is active for devices Si5334G/H/J. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will increase the output frequency of the
clock output by a factory-programmed amount. The
function of this pin is factory-programmed.
If this pin is unused, it should be grounded.
4
IN4
I
LVCMOS
Keep the input level > –0.1 V and < VDD+ 0.1 V.
FDBKSE
High Impedance input for single-ended clock signals,
such as CMOS, when the zero delay mode of operation
is required. This input should be dc-coupled.
PDEC
This pin function is active for devices Si5334D/E/F. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will decrease the input to output device
latency by a factory-programmed amount. The function
of this pin is factory-programmed.
FDEC
This pin function is active for devices Si5334G/H/J. A
positive pulse of greater than 100 ns width (followed by
>100 ns low) will decrease the output frequency of the
clock output by a factory-programmed amount. The
function of this pin is factory-programmed.
If this pin is unused, it should be grounded.
5,6
7
20
IN5/IN6
VDD
I
VDD
Multi
FDBK/FDBKB
These pins form a differential input for feedback clock
signals when a zero delay mode of operation is in effect.
Always AC couple into these pins. When not is use
leave FDBK unconnected and connect FDBKB to
ground.
Supply
Core Supply Voltage
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 μF bypass capacitor should be located very close to
this pin.
Rev. 1.3
Si5334
Table 15. Si5334 Pin Descriptions (Continued)
Pin #
8
9
10
11
12
Pin Name
LOSLOL
CLK3B
CLK3A
VDDO3
IN7
I/O
O
O
O
VDD
I
Signal Type
Open Drain
Description
Loss of Signal or Loss of Lock Indicator.
0 = No LOS or LOL condition.
1 = A LOS or LOL condition has occurred.
For this pin a 1–5 k pull-up resistor to a voltage is
required. This voltage may be as high as 3.63 V
regardless of the voltage on pin 7.
Multi
Output Clock B for Channel 3
May be a single-ended output or half of a differential output with CLK3A being the other differential half. If
unused leave this pin floating.
Multi
Output Clock A for Channel 3
May be a single-ended output or half of a differential
output with CLK3B being the other differential half. If
unused leave this pin floating.
Supply
LVCMOS
Output Clock Supply Voltage
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A
0.1 μF capacitor must be located very close to this pin. If
CLK3 is not used, this pin must be tied to VDD (pin 7,
24).
SSPB*.
When low, Spread Spectrum is enabled on every output
clock that is programmed for Spread Spectrum. This
option is available on the Si5334K/L/M.
On an Si5334 that does not contain the spread spectrum
functionality, this pin should be connected to GND.
13
14
15
16
CLK2B
CLK2A
VDDO2
VDDO1
O
O
VDD
VDD
Multi
Output Clock B for Channel 2
May be a single-ended output or half of a differential
output with CLK2A being the other differential half. If
unused leave this pin floating.
Multi
Output Clock A for Channel 2
May be a single-ended output or half of a differential
output with CLK2B being the other differential half. If
unused leave this pin floating.
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
A 0.1 μF capacitor must be located very close to this pin.
If CLK2 is not used, this pin must be tied to VDD (pin 7,
24).
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.
A 0.1 μF capacitor must be located very close to this pin.
If CLK1 is not used, this pin must be tied to VDD (pin 7,
24).
Rev. 1.3
21
Si5 334
Table 15. Si5334 Pin Descriptions (Continued)
Pin #
17
18
19
20
21
CLK1B
CLK1A
OEB
VDDO0
CLK0B
I/O
O
O
I
VDD
O
Signal Type
Description
Multi
Output Clock B for Channel 1
May be a single-ended output or half of a differential
output with CLK1A being the other differential half.
If unused, this pin must be tied to VDD pin 24. If unused
leave this pin floating.
Multi
Output Clock A for Channel 1
May be a single-ended output or half of a differential
output with CLK1B being the other differential half. If
unused leave this pin floating.
LVCMOS
Output Enable Low
When low, all the factory-programmed outputs are
enabled. When high all factory programmed outputs are
forced to a logic low.
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.
A 0.1 μF capacitor must be located very close to this pin.
If CLK0 is not used, this pin must be tied to VDD (pin 7,
24).
Multi
Output Clock B for Channel 0
May be a single-ended output or half of a differential
output with CLK0A being the other differential half. If
unused leave this pin floating.
22
CLK0A
O
Multi
Output Clock A for Channel 0
May be a single-ended output or half of a differential
output with CLK0B being the other differential half. If
unused leave this pin floating.
23
RSVD_GND
GND
GND
Ground.
Must be connected to system ground.
24
GND
PAD
22
Pin Name
VDD
GND
VDD
GND
Supply
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A
0.1 μF bypass capacitor should be located very close to
this pin.
GND
Ground Pad.
This is the large pad in the center of the package.
Device specifications cannot be guaranteed unless the
ground pad is properly connected to a ground plane on
the PCB. See section 6.0 for the PCB pad sizes and
ground via requirements.
Rev. 1.3
Si5334
4. Device Pinout by Part Number
The Si5334 is orderable in three different speed grades: Si5334A/D/G/K have a maximum output clock frequency
limit of 710 MHz. Si5338B/E/H/L have a maximum output clock frequency of 350 MHz. Si5338C/F/J/M have a
maximum output clock frequency of 200 MHz.
Brief pin functions follow.
or one side of differential input clock
or one side of differential input clock
REFCLKSE—single-ended reference clock input
FDBKSE—single-ended feedback clock input
FDBK—differential feedback input
FDBKB—differential feedback input inverted
FINC—frequency increment pin
FDEC—frequency decrement pin
PINC—phase increment pin
PDEC—phase decrement pin
OEB—output enable low
See the four groupings below for the available pin control functions on pins 3, 4 and 12.
XTAL/CLKIN—crystal
XTAL/CLKINB—crystal
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
XTAL/CLKIN
13
CLK2B
1
XTAL/CLKIN
13
CLK2B
2
XTAL/CLKINB
14
CLK2
2
XTAL/CLKINB
14
CLK2
3
REFCLKSE
15
VDDO2
3
PINC
15
VDDO2
4
FDBKSE
16
VDDO1
4
PDEC
16
VDDO1
5
FDBK
17
CLK1B
5
FDBK
17
CLK1B
6
FDBKB
18
CLK1
6
FDBKB
18
CLK1
7
VDD
19
OEB
7
VDD
19
OEB
8
INTR
20
VDDO0
8
INTR
20
VDDO0
9
CLK3B
21
CLK0B
9
CLK3B
21
CLK0B
10
CLK3
22
CLK0
10
CLK3
22
CLK0
11
VDDO3
23
RSVDGND
11
VDDO3
23
RSVDGND
12
GND
24
VDD
12
GND
24
VDD
Rev. 1.3
23
Si5 334
24
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
XTAL/CLKIN
13
CLK2B
1
XTAL/CLKIN
13
CLK2B
2
XTAL/CLKINB
14
CLK2
2
XTAL/CLKINB
14
CLK2
3
FINC
15
VDDO2
3
REFCLKSE
15
VDDO2
4
FDEC
16
VDDO1
4
FDBKSE
16
VDDO1
5
FDBK
17
CLK1B
5
FDBK
17
CLK1B
6
FDBKB
18
CLK1
6
FDBKB
18
CLK1
7
VDD
19
OEB
7
VDD
19
OEB
8
INTR
20
VDDO0
8
INTR
20
VDDO0
9
CLK3B
21
CLK0B
9
CLK3B
21
CLK0B
10
CLK3
22
CLK0
10
CLK3
22
CLK0
11
VDDO3
23
RSVDGND
11
VDDO3
23
RSVDGND
12
GND
24
VDD
12
SSPB
24
VDD
Rev. 1.3
Si5334
5. Ordering Information and Standard Frequency Plans
5.1. Ordering Information
5.2. Evaluation Boards
The Si5338 evaluation board allows creation of custom and standard configurations for the Si5334. Refer to
www.silabs.com/Si5338-EVB for more information.
Rev. 1.3
25
Si5 334
5.3. Standard Frequency Plans
Table 16. Si5334 Standard Frequency Plans
CLKIN
Application
SONET/SDH
26
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Si5334CB00099-GM
Clock
19.4400
3.3 V
CMOS
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
77.7600
3.3 V
LVPECL
77.7600
3.3 V
LVPECL
Si5334CB00101-GM
Clock
19.4400
3.3 V
CMOS
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Si5334AB00102-GM
Clock
19.4400
3.3 V
CMOS
622.0800
3.3 V
LVPECL
622.0800
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Si5334CB00103-GM
Clock
38.8800
3.3 V
CMOS
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
77.7600
3.3 V
LVPECL
77.7600
3.3 V
LVPECL
Si5334CB00104-GM
Clock
38.8800
3.3 V
CMOS
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Si5334AB00105-GM
Clock
38.8800
3.3 V
CMOS
622.0800
3.3 V
LVPECL
622.0800
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Si5334CB00106-GM
Clock
155.5200
3.3 V
LVPECL
161.1328
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Rev. 1.3
S i5334
Table 16. Si5334 Standard Frequency Plans (Continued)
CLKIN
Application
Ethernet/Fibre
Channel
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Si5334CB00107-GM
Xtal
25.0000
n/a
161.1328
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
25.0000
3.3 V
CMOS
Si5334CB00108-GM
Clock
25.0000
3.3 V
CMOS
161.1328
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
25.0000
3.3 V
CMOS
Si5334BB00109-GM
Xtal
25.0000
n/a
312.5000
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
62.5000
3.3 V
CMOS
Si5334BB00110-GM
Clock
25.0000
3.3 V
CMOS
312.5000
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
62.5000
3.3 V
CMOS
Si5334CB00111-GM
Xtal
25.0000
n/a
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
Si5334CB00112-GM
Clock
25.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
Si5334CB00113-GM
Xtal
25.0000
n/a
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
Si5334CB00114-GM
Clock
25.0000
3.3 V
CMOS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
Si5334CB00115-GM
Xtal
25.0000
n/a
156.2500
1.8 V
LVDS
156.2500
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
Rev. 1.3
27
Si5 334
Table 16. Si5334 Standard Frequency Plans (Continued)
CLKIN
Application
Ethernet/Fibre
Channel
(Continued)
28
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Si5334CB00116-GM
Clock
25.0000
3.3 V
CMOS
156.2500
1.8 V
LVDS
156.2500
1.8 V
LVDS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
Si5334CB00117-GM
Xtal
25.0000
n/a
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
106.2500
3.3 V
CMOS
106.2500
3.3 V
CMOS
Si5334CB00118-GM
Clock
25.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
125.0000
3.3 V
CMOS
106.2500
3.3 V
CMOS
106.2500
3.3 V
CMOS
Si5334CB00119-GM
Xtal
25.0000
n/a
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
106.2500
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
Si5334CB00120-GM
Clock
25.0000
3.3 V
CMOS
125.0000
1.8 V
LVDS
125.0000
1.8 V
LVDS
106.2500
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
Si5334BB00121-GM
Xtal
25.0000
n/a
212.5000
3.3 V
LVPECL
212.5000
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
Si5334BB00122-GM
Clock
25.0000
3.3 V
CMOS
212.5000
3.3 V
LVPECL
212.5000
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
106.2500
3.3 V
LVPECL
Si5334BB00123-GM
Xtal
25.0000
n/a
212.5000
3.3 V
LVDS
212.5000
3.3 V
LVDS
106.2500
3.3 V
LVDS
106.2500
3.3 V
LVDS
Si5334BB00124-GM
Clock
25.0000
3.3 V
CMOS
212.5000
3.3 V
LVDS
212.5000
3.3 V
LVDS
106.2500
3.3 V
LVDS
106.2500
3.3 V
LVDS
Si5334CB00125-GM
Xtal
25.0000
n/a
156.2500
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
125.0000
1.8 V
LVDS
106.2500
3.3 V
LVPECL
Si5334CB00126-GM
Clock
25.0000
3.3 V
CMOS
156.2500
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
125.0000
1.8 V
LVDS
106.2500
3.3 V
LVPECL
Si5334CB00127-GM
Clock
125.0000
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
156.2500
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
Si5334CB00128-GM
Clock
156.2500
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
155.5200
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
125.0000
3.3 V
LVPECL
Rev. 1.3
S i5334
Table 16. Si5334 Standard Frequency Plans (Continued)
CLKIN
Application
Synchronous
Ethernet
(RX-Side)
PDH
Broadcast
Video
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Si5334CB00129-GM
Clock
19.4400
3.3 V
CMOS
25.0000
3.3 V
CMOS
25.0000
3.3 V
CMOS
25.0000
3.3 V
CMOS
25.0000
3.3 V
CMOS
Si5334CB00130-GM
Clock
25.0000
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
Si5334CB00131-GM
Clock
125.0000
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
Si5334CB00132-GM
Clock
156.2500
3.3 V
LVPECL
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
Si5334CB00133-GM
Clock
161.1328
3.3 V
LVPECL
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
19.4400
3.3 V
CMOS
Si5334CB00134-GM
Clock
19.4400
3.3 V
CMOS
1.5440
3.3 V
CMOS
1.5440
3.3 V
CMOS
1.5440
3.3 V
CMOS
1.5440
3.3 V
CMOS
Si5334CB00135-GM
Clock
19.4400
3.3 V
CMOS
2.0480
3.3 V
CMOS
2.0480
3.3 V
CMOS
2.0480
3.3 V
CMOS
2.0480
3.3 V
CMOS
Si5334CB00136-GM
Clock
19.4400
3.3 V
CMOS
2.0480
3.3 V
CMOS
2.0480
3.3 V
CMOS
1.5440
3.3 V
CMOS
1.5440
3.3 V
CMOS
Si5334CB00137-GM
Clock
19.4400
3.3 V
CMOS
8.1920
3.3 V
CMOS
4.0960
3.3 V
CMOS
2.0480
3.3 V
CMOS
2.0480
3.3 V
CMOS
Si5334CB00138-GM
Clock
19.4400
3.3 V
CMOS
44.7360
3.3 V
CMOS
44.7360
3.3 V
CMOS
34.3680
3.3 V
CMOS
34.3680
3.3 V
CMOS
Si5334CB00139-GM
Xtal
27.0000
n/a
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
54.0000
3.3 V
CMOS
27.0000
3.3 V
CMOS
Si5334CB00140-GM
Clock
27.0000
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
54.0000
3.3 V
CMOS
27.0000
3.3 V
CMOS
Si5334CB00141-GM
Xtal
27.0000
n/a
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
27.0000
3.3 V
CMOS
Si5334CB00142-GM
Clock
27.0000
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
27.0000
3.3 V
CMOS
Si5334CB00143-GM
Xtal
27.0000
n/a
108.0000
3.3 V
LVDS
74.2500
3.3 V
LVDS
74.1758
3.3 V
LVDS
54.0000
3.3 V
LVDS
Si5334CB00144-GM
Clock
27.0000
3.3 V
CMOS
108.0000
3.3 V
LVDS
74.2500
3.3 V
LVDS
74.1758
3.3 V
LVDS
54.0000
3.3 V
LVDS
Rev. 1.3
29
Si5 334
Table 16. Si5334 Standard Frequency Plans (Continued)
CLKIN
Application
Broadcast
Video
(Continued)
30
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Si5334CB00145-GM
Xtal
27.0000
n/a
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00146-GM
Clock
27.0000
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00147-GM
Xtal
27.0000
n/a
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
Si5334CB00148-GM
Clock
27.0000
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
Si5334CB00149-GM
Xtal
27.0000
n/a
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00150-GM
Clock
27.0000
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00151-GM
Xtal
27.0000
n/a
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00152-GM
Clock
27.0000
3.3 V
CMOS
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
Si5334CB00153-GM
Xtal
27.0000
n/a
156.2500
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
108.0000
3.3 V
LVDS
Si5334BB00154-GM
Clock
27.0000
3.3 V
CMOS
156.2500
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
108.0000
3.3 V
LVDS
Si5334CB00155-GM
Xtal
27.0000
n/a
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
Si5334BB00156-GM
Clock
27.0000
3.3 V
CMOS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
Si5334CB00157-GM
Xtal
27.0000
n/a
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
Si5334CB00158-GM
Clock
27.0000
3.3 V
CMOS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
Si5334CB00159-GM
Xtal
27.0000
n/a
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
Si5334CB00160-GM
Clock
27.0000
3.3 V
CMOS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
Rev. 1.3
3.3 V
LVDS
3.3 V
LVDS
3.3 V
LVDS
3.3 V
LVDS
3.3 V
LVDS
3.3 V
LVDS
S i5334
Table 16. Si5334 Standard Frequency Plans (Continued)
CLKIN
Application
Broadcast
Video
(Continued)
PCIe*
CLK0
CLK1
CLK2
CLK3
OPN
Input
Freq
Format
Freq
Format
Freq
Format
Freq
Format
Freq
Si5334CB00161-GM
Clock
74.1758
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
3.3 V
CMOS
74.2500
Si5334CB00162-GM
Clock
74.2500
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
3.3 V
CMOS
74.1758
Si5334CB00163-GM
Clock
148.3516
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
3.3 V
LVDS
148.5000
Si5334BB00164-GM
Clock
148.3516
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
Si5334CB00165-GM
Clock
148.5000
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
3.3 V
LVDS
148.3516
270.0000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
3.3 V
LVDS
270.0000
Format
3.3 V
CMOS
3.3 V
CMOS
3.3 V
LVDS
3.3 V
LVDS
3.3 V
LVDS
Si5334BB00166-GM
Clock
148.5000
3.3 V
LVDS
Si5334MB00167-GM
Xtal
25.0000
n/a
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
Si5334MB00168-GM
Clock
25.0000
3.3 V
CMOS
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
100.0000
3.3 V
HCSL
3.3 V
LVDS
Notes:
1. –0.5% downspread enabled on CLK0-CLK3
2. To request new frequency plans/device configurations, please contact your local Silicon Labs sales representative.
Rev. 1.3
31
Si5 334
6. Package Outline: 24-Lead QFN
Figure 4. 24-Lead Quad Flat No-lead (QFN)
Table 17. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
4.00 BSC.
2.35
2.50
e
0.50 BSC.
E
4.00 BSC.
2.65
E2
2.35
2.50
2.65
L
0.30
0.40
0.50
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.05
Notes:
1.
2.
3.
4.
32
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing per ANSI Y14.5M-1994.
This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Rev. 1.3
Si5334
7. Recommended PCB Land Pattern
Table 18. PCB Land Pattern
Dimension
Min
Nom
Max
P1
2.50
2.55
2.60
P2
2.50
2.55
2.60
X1
0.20
0.25
0.30
Y1
0.75
0.80
0.85
C1
3.90
C2
3.90
E
0.50
Notes
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no
more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground
plane is allowed if more vias are used to keep the inductance from increasing.
Solder Mask Design:
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to
be 60 μm minimum, all the way around the pad.
Stencil Design:
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly:
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.3
33
Si5 334
8. Top Marking
8.1. Si5334 Top Marking
8.2. Top Marking Explanation
Line
Characters
Description
Line 1
Si5334
Base part number.
Line 2
Xxxxxx
X = Frequency and configuration code. See "5. Ordering Information
and Standard Frequency Plans" on page 25 for more information.
xxxxx = NVM code.
See “5. Ordering Information and Standard Frequency Plans” .
Line 3
RTTTTT
R = Product revision.
TTTTT = Manufacturing trace code.
Circle with 0.5 mm diameter;
Pin 1 indicator.
left-justified
Line 4
YYWW
34
YY = Year.
WW = Work week.
Characters correspond to the year and work week of package assembly.
Rev. 1.3
Si5334
9. Device Errata
Please visit www.silabs.com to access the device errata document.
Rev. 1.3
35
Si5 334
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.15
Added
Updated tables for ac/dc specs to remove TBDs.
Updated ordering OPN in Table 10 from 34C to
34M-00167/00168-GM.
Updated SSC information for correct part number.
Removed diagram in Section 3.
Corrected Pin 12 description
Removed low-power LVPECL mode.
Updated pin descriptions to say 710 MHz.
Added PCB layout notes on via requirements for
GND pad.
Removed description of field programming as this is
not supported.
Revision 0.15 to Revision 0.16
Updated Table 3, “Performance Characteristics,” on
page 5.
Revision 1.2 to Revision 1.3
Updated Table 4, “Input and Output Clock
Characteristics,” on page 6.
CML Output specs.
VI to 3.73 V.
Corrected tR/tF (15 pF) to 2.0 ns.
Corrected LVPECL Output Voltage (typ) to
VDDO – 1.45.
Corrected
Updated Table 5, “Control Pins,” on page 9.
Updated
VIH to 3.73 V.
VIL and VOL.
Corrected
Expanded Tables 6–9 with recommended and
supported crystal load capacitance values.
Updated Table 10, “Jitter Specifications1,2,3,” on
page 11.
Updated
typical specifications for total jitter for PCI
Express 1.1 Common clocked topology.
Updated typical specifications for RMS jitter for PCI
Express 2.1 Common clocked topology.
Removed RMS jitter specification for PCI Express 2.1
and 3.0 Data clocked topology.
36
Removed down spread errata that has been
corrected in revision B.
Updated ordering information to refer to Revision B
silicon.
Updated top marking explanation in section 8.2.
Updated “Device Pinout by Part Number” part
number references.
Standard frequency plan OPNs in Table 16 updated
to reflect Rev B part numbers.
Revision 1.1 to Revision 1.2
Added
“Supply” to “LVCMOS” for IN7 (pin 12).
Updated and moved "5. Ordering Information and
Standard Frequency Plans" on page 25.
Added "8. Top Marking" on page 34.
Added "9. Device Errata" on page 35.
dc characteristics for CMOS loads.
core supply current in buffer mode.
Added CML output buffer supply current in CML mode.
Lock Range test changed to PLL Tracking Range
and added typical specification.
Added Maximum Propragation Delay value.
Corrected Table 15, “Si5334 Pin Descriptions,” on
page 19.
Revision 1.0 to Revision 1.1
Updated Table 2, “DC Characteristics,” on page 4.
PLL
MSL level information.
Peak Soldering Reflow Temperature.
Changed
Added
Updated
Added
Changed cycle-cycle jitter spec from pk-pk to pk.
Change refclk1 pin name to refclkse.
Revision 0.16 to Revision 1.0
Updated Table 13, “Absolute Maximum Ratings1,”
on page 13
Updated Table 12, “Thermal Characteristics,” on
page 13.
Rev. 1.3
Added link to errata document.
Removed MSL rating.
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