SI533DA00100DG

Si 5 33 REVISION D D U A L F R E Q U E N C Y C R Y S TA L O S C I L L A T O R ( XO ) (10 M H Z T O 1 .4 G H Z ) Features Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz 2 selectable output frequencies 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW-based oscillators Pin 1 output enable (OE) Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Si5602 Applications SONET/SDH Networking SD/HD video Clock and data recovery FPGA/ASIC clock generation Ordering Information: See page 7. Description The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si533 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si533 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si533 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Pin Assignments: See page 6. (Top View) OE FS GND 1 2 3 6 5 4 VDD CLK– CLK+ LVDS/LVPECL/CML Functional Block Diagram V DD CLK– CLK+ OE FS 1 2 3 CMOS 6 5 4 VDD NC CLK+ Fixed Frequency XO A ny-rate 10–1400 MHz DSPLL® Clock Synthesis GND OE FS GND Rev. 1.1 6/07 Copyright © 2007 by Silicon Laboratories Si533 S i5 33 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current IDD Output enabled LVPECL CML LVDS CMOS Tristate mode Output Enable (OE) and Frequency Select (FS)2 Operating Temperature Range TA VIH VIL Min 2.97 2.25 1.71 — — — — — 0.75 x VDD — –40 Typ 3.3 2.5 1.8 111 99 90 81 60 — — — Max 3.63 2.75 1.89 121 108 98 88 75 — 0.5 85 V ºC V Units mA Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE and FS pins include a 17 kΩ pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Symbol fO Test Condition LVPECL/LVDS/CML CMOS Min 10 10 — –7 –20 –50 Typ — — ±1.5 — — — — — Max 945 160 — +7 +20 +50 ±3 ±10 Units MHz Initial Accuracy fi Measured at +25 °C at time of shipping ppm Temperature Stability1,3 Frequency drift over first year Frequency drift over 15 year life ppm ppm ppm Aging fa — — Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Rev. 1.1 S i533 Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Symbol Test Condition Temp stability = ±7 ppm Total Stability Temp stability = ±20 ppm Temp stability = ±50 ppm Powerup Time4 Settling Time After FS Change tOSC tFRQ Min — — — — — Typ — — — — — Max ±20 ±31.5 ±61.5 10 10 Units ppm ppm ppm ms ms Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. Table 3. CLK± Output Levels and Symmetry Parameter LVPECL Output Option1 Symbol VO VOD VSE Test Condition mid-level swing (diff) swing (single-ended) mid-level swing (diff) Min VDD – 1.42 1.1 0.55 1.125 0.5 Typ — Max VDD – 1.25 1.9 0.95 1.275 0.9 Units V VPP VPP V VPP — — 1.20 0.7 LVDS Output Option2 VO VOD CML Output Option2 VO VOD mid-level swing (diff) IOH = 32 mA IOL = 32 mA — 0.70 0.8 x VDD VDD – 0.75 0.95 — — — 1 — — 1.20 VDD V VPP V CMOS Output Option3 VOH VOL — — — 45 0.4 350 — 55 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML CMOS with CL = 15 pF ps ns % Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF Rev. 1.1 3 S i5 33 Table 4. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)* for FOUT > 500 MHz Phase Jitter (RMS)* for FOUT of 125 to 500 MHz Symbol Test Condition 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min — — — — Typ 0.25 0.26 0.36 0.34 Max 0.40 0.37 0.50 0.42 ps Units ps φJ φJ 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz (OC-192) *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK± Output Period Jitter Parameter Period Jitter* Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ 2 14 Max — — Units ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Table 6. CLK± Output Phase Noise (Typical) Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 120.00 MHz LVDS –112 –122 –132 –137 –144 –150 n/a 156.25 MHz LVPECL –105 –122 –128 –135 –144 –147 n/a 622.08 MHz LVPECL –97 –107 –116 –121 –134 –146 –148 Units dBc/Hz 4 Rev. 1.1 S i533 Table 7. Absolute Maximum Ratings1 Parameter Maximum Operating Temperature Supply Voltage Input Voltage (any input pin) Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Symbol TAMAX VDD VI TS ESD TPEAK tP Rating 85 –0.5 to +3.8 –0.5 to VDD + 0.3 –55 to +125 2500 260 20–40 Units ºC Volts Volts ºC Volts ºC seconds Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Table 8. Environmental Compliance The Si533 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/Test Method MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016 Rev. 1.1 5 S i5 33 2. Pin Descriptions (Top View) OE FS GND 1 2 3 6 5 4 VDD OE FS GND 1 2 3 CMOS 6 5 4 VDD CLK– CLK+ NC CLK LVDS/LVPECL/CML Pin # 1 Symbol OE* LVDS/LVPECL/CML Function CMOS Function Output Enable* Output Enable* 0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated) 1 = clock output enabled 1 = clock output enabled Frequency Select* 0 = First frequency selected 1 = Second frequency selected Electrical and Case Ground Oscillator Output Complementary Output Power Supply Voltage Frequency Select* 0 = First frequency selected 1 = Second frequency selected Electrical and Case Ground Oscillator Output No Connection Power Supply Voltage 2 3 4 5 6 FS* GND CLK+ CLK– VDD *Note: FS and OE include a 17 kΩ pullup resistor to VDD. See Section 3. "Ordering Information" on page 7 for details on frequency value ordering. 6 Rev. 1.1 S i533 3. Ordering Information The Si533 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si533 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si533 is supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The Si533 supports output enable (OE) on pin 1. 533 533 Dual XO Product Family X X XXXXXX D G R R = Tape & Reel Blank = Trays 1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Operating Temp Range (°C) G –40 to +85 °C Device Revision Letter 6-digit Frequency Designator Code Two unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for the specified combination of frequencies. Codes > 000100 refer to dual XOs programmed with the lower frequency value selected when FS = 0, and the higher value when FS = 1. Six digit codes < 000100 refer to dual XOs programmed with the higher frequency value selected when FS = 0, and the lower value when FS = 1. 2nd Option Code Code Temperature Stability (ppm, max, ±) A 50 B 20 C 7 Total Stablility (ppm, max, ±) 61.5 31.5 20 Note: CMOS available to 160 MHz. Example Part Number: 533AB000108DGR is a 5x7mm Dual XO in a 6 pad package. Since the six digit code (000108) is > 000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output. Temperature stability is specified as ± 20 ppm. The part is specified for a -40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention Rev. 1.1 7 S i5 33 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si533. Table 9 lists the values for the dimensions shown in the illustration. Figure 2. Si533 Outline Diagram Table 9. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 L S R aaa bbb ccc ddd — — — — 4.30 1.07 6.10 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP. 7.00 BSC. 6.2 2.54 BSC. 5.00 BSC. 4.40 1.27 1.815 BSC. 0.7 REF. — — — — 0.15 0.15 0.10 0.10 4.50 1.47 6.30 Max 1.85 1.6 8 Rev. 1.1 S i533 5. Si533 Mark Specification Figure 3 illustrates the mark specification for the Si533. Table 10 lists the line information. 6 5 4 SiLabs 123 1234567890 R T T T T Y WW+ 1 2 Figure 3. Mark Specification Table 10. Si53x Top Mark Description Line 1 2 Position 1–10 1–10 Description “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) Si530, Si531: Option1 + Option2 + Freq(7) + Temp Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 3 Trace Code Position 1 Position 2 Position 3–6 Position 7 Position 8–9 Position 10 Pin 1 orientation mark (dot) Product Revision (D) Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Calendar Work Week number (1–53), to be assigned by assembly site “+” to indicate Pb-Free and RoHS-compliant Rev. 1.1 9 S i5 33 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si533. Table 11 lists the values for the dimensions shown in the illustration. Figure 4. Si533 PCB Land Pattern Table 11. PCB Land Pattern Dimensions (mm) Dimension D2 e E2 GD GE VD VE X Y ZD ZE — — 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 2.15 REF 6.78 6.30 Min 5.08 REF 2.54 BSC 4.15 REF — — Max Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 10 Rev. 1.1 S i533 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 Updated Table 1, “Recommended Operating Conditions,” on page 2. Device maintains stable operation over –40 to +85 ºC operating temperature range. Supply current specifications updated for revision D. Updated Table 2, “CLK± Output Frequency Characteristics,” on page 2. Added specification for ±20 ppm lifetime stability (±7 ppm temperature stability) XO. Updated Table 3, “CLK± Output Levels and Symmetry,” on page 3. Updated LVDS differential peak-peak swing specifications. Updated Table 4, “CLK± Output Phase Jitter,” on page 4. Updated Table 5, “CLK± Output Period Jitter,” on page 4. Revised period jitter specifications. Updated Table 7, “Absolute Maximum Ratings1,” on page 5 to reflect the soldering temperature time at 260 ºC is 20–40 sec per JEDEC J-STD-020C. Updated 3. "Ordering Information" on page 7. Changed ordering instructions to revision D. Added 5. "Si533 Mark Specification" on page 9. Rev. 1.1 11 S i5 33 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Rev. 1.1