SI5342H-D-GM

Si5344H/42H Rev D H I G H -F R E Q U E N C Y, U LTR A -L O W J I T T E R AT T E N U ATO R C L O C K W I T H D IG ITALLY -C O NTR O L L ED O SC ILLATO R Features VDD I2C_SEL RSVD_GND NC NC VDDS 36 35 34 37 38 NC VDD 39 41 VDD LOS1 30 LOS0 29 VDDS 28 LOS_XAXB 27 LOL 8 26 VDDS VDDA 9 25 OUT1 NC 10 24 OUT1 NC 11 23 VDDO1 21 22 NC 20 7 OUT0 VDD X2 VDDA GND Pad 19 6 18 5 VDDO0 OUT0 4 XB 17 X1 XA Description IN0 NC NC VDD VDD I2C_SEL IN_SEL1 OUT3 OUT3 VDDO3 43 41 39 38 36 35 34 37 IN0 44 Si5344H 44QFN Top View IN1 1 33 INTR IN1 2 32 IN_SEL0 3 31 VDD OUT2 XGND 4 30 OUT2 XA 5 29 VDDO2 XB 6 28 LOS_XAXB XGND VDDA 7 27 LOL 8 26 VDDS VDDA 9 25 OUT1 NC 10 24 OUT1 NC 11 23 VDDO1 22 18 VDDO0 OUT0 NC 17 21 16 RST 20 15 A1/SDO A0/CS 19 14 SCLK OUT0 VDD 13 12 GND Pad OE SDA/SDIO This specialized jitter attenuating clock multiplier combines fourth-generation DSPLL with ultra-low phase jitter and MultiSynth™ technologies to enable high data rate coherent optical transceiver design. Up to four outputs can be assigned to High Frequency Mode capable of up to 2.75 GHz at 50 fs-rms typical phase jitter (1 MHz-40 MHz). Each output may also be configured as MultiSynth Mode any-frequency outputs when added frequency flexibility is required, such as clocking Forward Error Correction (FEC) while still delivering