SI5345C-D-GM

Si5345/44/42 Rev D Data Sheet 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/Clock Multiplier KEY FEATURES These jitter attenuating clock multipliers combine fourth-generation DSPLL™ and MultiSynth™ technologies to enable any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) so they always power up with a known frequency configuration. They support free-run, synchronous, and holdover modes of operation, and offer both automatic and manual input clock switching. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Furthermore, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. Programming the Si5345/44/42 is easy with Silicon Labs’ ClockBuilder Pro™ software. Factory preprogrammed devices are also available. Applications: • OTN muxponders and transponders • 10/40/100 G networking line cards • GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262) • Carrier Ethernet switches • SONET/SDH line cards • Broadcast video • Test and measurement • ITU-T G.8262 (SyncE) compliant • Generates any combination of output frequencies from any input frequency • Ultra-low jitter of 90 fs rms • External Crystal: 25 to 54 MHz • Input frequency range • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range • Differential: 100 Hz to 1028 MHz • LVCMOS: 100 Hz to 250 MHz • Meets G.8262 EEC Option 1, 2 (SyncE) • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude • Si5345: 4 input, 10 output, 64-QFN 9×9 mm • Si5344: 4 input, 4 output, 44-QFN 7×7 mm • Si5342: 4 input, 2 output, 44-QFN 7×7 mm 25-54 MHz XTAL XA XB IN0 ÷FRAC IN2 ÷FRAC IN3/FB_IN ÷FRAC I2C / SPI Status Monitor Control OUT0 MultiSynth ÷INT OUT1 MultiSynth ÷INT OUT2 MultiSynth ÷INT OUT3 MultiSynth ÷INT OUT4 ÷INT OUT5 ÷INT OUT6 ÷INT OUT7 ÷INT OUT8 ÷INT OUT9 Up to 10 Output Clocks Si5345 Status Flags DSPLL ÷INT Si5344 IN1 4 Input Clocks 1 ÷FRAC MultiSynth Si5342 OSC NVM Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 1 Si5345/44/42 Rev D Data Sheet • Features List 1. Features List The Si5345/44/42 Rev D features are listed below: • Generates any combination of output frequencies from any input frequency • Ultra-low jitter of 90 fs rms • Input frequency range • Differential: 8 kHz–750 MHz • LVCMOS: 8 kHz–250 MHz • Output frequency range • Differential: 100 Hz to 1028 MHz • LVCMOS: 100 Hz to 250 MHz • Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz • Meets G.8262 EEC Option 1, 2 (SyncE) • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude • Status monitoring (LOS, OOF, LOL) • Hitless input clock switching: automatic or manual • Locks to gapped clock inputs • Free-run and holdover modes 2 • • • • • Optional zero delay mode Fastlock feature for low nominal bandwidths Glitchless on the fly output frequency changes DCO mode: as low as 0.001 ppb step size Core voltage • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% • Independent output clock supply pins • 3.3 V, 2.5 V, or 1.8 V • Serial interface: I2C or SPI • • • • • • • In-circuit programmable with non-volatile OTP memory ClockBuilder Pro software simplifies device configuration Si5345: 4 input, 10 output, 64-QFN 9×9 mm Si5344: 4 input, 4 output, 44-QFN 7×7 mm Si5342: 4 input, 2 output, 44-QFN 7×7 mm Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 2 Si5345/44/42 Rev D Data Sheet • Ordering Guide 2. Ordering Guide Ordering Part Number (OPN) Number of Input/Output Clocks Output Clock Frequency Supported Frequency Range (MHz) Synthesis Modes Package Temperature Range Si5345 Si5345A-D-GM1, 2 Si5345B-D-GM1, 2 Si5345C-D-GM1, 2 4/10 Si5345D-D-GM1, 2 0.001 to 1028 MHz Integer and 0.001 to 350 MHz Fractional 0.001 to 1028 MHz 0.001 to 350 MHz 64-QFN 9×9 mm –40 to 85 °C Integer Only Si5344 Si5344A-D-GM1, 2 Si5344B-D-GM1, 2 Si5344C-D-GM1, 2 4/4 Si5344D-D-GM1, 2 0.001 to 1028 MHz Integer and 0.001 to 350 MHz Fractional 0.001 to 1028 MHz 0.001 to 350 MHz 44-QFN 7×7 mm –40 to 85 °C Integer Only Si5342 Si5342A-D-GM1, 2 Si5342B-D-GM1, 2 Si5342C-D-GM1, 2 4/2 Si5342D-D-GM1, 2 0.001 to 1028 MHz Integer and 0.001 to 350 MHz Fractional 0.001 to 1028 MHz 0.001 to 350 MHz 44-QFN 7×7 mm –40 to 85 °C Integer Only Si5345/44/42-D-EVB Si5345-D-EVB Si5344-D-EVB — — — Evaluation Board — Si5342-D-EVB Notes: 1. Add an R at the end of the OPN to denote tape and reel ordering options. 2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder Pro software. Custom part number format is “Si5345A-Dxxxxx-GM” where “xxxxx” is a unique numerical sequence representing the preprogrammed configuration. 3 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 3 Si5345/44/42 Rev D Data Sheet • Ordering Guide Figure 2.1. Ordering Part Number Fields 4 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 4 Table of Contents 1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . .10 3.7 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . 3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3) . 3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3) 3.7.3 Hitless Input Switching . . . . . . . . 3.7.4 Ramped Input Switching . . . . . . . 3.7.5 Glitchless Input Switching . . . . . . . 3.7.6 Input Configuration and Terminations . . . 3.7.7 Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .11 .11 .11 .11 .12 .13 3.8 Fault Monitoring . . . 3.8.1 Input LOS Detection. 3.8.2 XA/XB LOS Detection 3.8.3 OOF Detection . . 3.8.4 LOL Detection . . . 3.8.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .14 .14 .14 .15 .16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 .17 .17 .18 .18 .18 .19 .19 .19 .19 .19 .19 .20 .20 . . 3.4 Modes of Operation . . 3.4.1 Initialization and Reset 3.4.2 Freerun Mode . . . 3.4.3 Lock Acquisition Mode 3.4.4 Locked Mode . . . 3.4.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Outputs . . . . . . . . . . . . . . . . . . . . 3.9.1 Output Crosspoint . . . . . . . . . . . . . . . 3.9.2 Output Signal Format . . . . . . . . . . . . . . 3.9.3 Differential Output Terminations . . . . . . . . . . . 3.9.4 LVCMOS Output Terminations . . . . . . . . . . . 3.9.5 Programmable Common Mode Voltage For Differential Outputs 3.9.6 LVCMOS Output Impedance Selection . . . . . . . . 3.9.7 LVCMOS Output Signal Swing . . . . . . . . . . . 3.9.8 LVCMOS Output Polarity . . . . . . . . . . . . . 3.9.9 Output Enable/Disable . . . . . . . . . . . . . . 3.9.10 Output Driver State When Disabled . . . . . . . . . 3.9.11 Synchronous Output Disable Feature . . . . . . . . 3.9.12 Zero Delay Mode . . . . . . . . . . . . . . . 3.9.13 Output Divider (R) Synchronization . . . . . . . . . 5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 7 8 8 8 8 9 5 3.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.11 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.12 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.13 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .21 3.14 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .21 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 39 7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . 43 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 . . . 10.1 Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . .51 10.2 Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . .52 11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 . . . Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 6 Si5345/44/42 Rev D Data Sheet • Functional Description 3. Functional Description The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional input dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency. 3.1 Frequency Configuration The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software. 3.2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 3.3 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once lock acquisition has completed. 3.4 Modes of Operation Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 8. The following sections describe each of these modes in greater detail. 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 7 Si5345/44/42 Rev D Data Sheet • Functional Description 3.4.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected Lock Acquisition (Fast Lock) An input is qualified and available for selection No valid input clocks available for selection Phase lock on selected input clock is achieved Locked Mode Holdover Mode Input Clock Switch Selected input clock fails Yes Yes No Holdover History Valid? Other Valid Clock Inputs No Available? Figure 3.1. Modes of Operation 3.4.2 Freerun Mode The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. 3.4.3 Lock Acquisition Mode The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls in to the input clock frequency. 3.4.4 Locked Mode Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved. See 3.8.4 LOL Detection for more details on the operation of the loss-of-lock circuit. 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 8 Si5345/44/42 Rev D Data Sheet • Functional Description 3.4.5 Holdover Mode The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120 seconds Programmable historical data window used to determine the final holdover value Programmable delay 0 Figure 3.2. Programmable Holdover Window When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth. The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 3.7.4 Ramped Input Switching. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 3.5 External Reference (XA/XB) An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 3.3 Crystal Resonator and External Reference Clock Connection Options on page 10. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to Table 5.12 Crystal Specifications on page 37 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. The Si5345/44/42 Rev D Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE pizza box applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to provide a stable holdover reference. See the Si5345/44/42 Rev D Family Reference Manual for more information. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode. Refer to Table 5.3 Input Clock Specifications on page 26 for REFCLK requirements when using this mode. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance. 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 9 Si5345/44/42 Rev D Data Sheet • Functional Description 3.6 Digitally Controlled Oscillator (DCO) Mode The output MultiSynths support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. Any number of MultiSynths can be updated at once or independently controlled. The DCO mode is available when the DSPLL is operating in either free-run or locked mode. 25-54 MHz XO/Clock LVCMOS 25-54 MHz XO/Clock C1 is recommended to increase the slew rate at Xa C1 R1 See the Reference Manual for the recommended R1, R2, C1 values R2 25-54 MHz XTAL X2 XB XA 2xCL Note: See Pin Descriptions for X1/X2 connections NC X1 XB 2xCL 2xCL NC X1 XA NC XB X2 2xCL 2xCL OSC OSC ÷ PREF X2 2xCL OSC ÷ PREF Crystal Resonator Connection NC X1 XA ÷ PREF Differential XO/Clock Connection LVCMOS XO/Clock Connection Figure 3.3. Crystal Resonator and External Reference Clock Connection Options Note: See Table 5.3 Input Clock Specifications on page 26. 3.7 Inputs (IN0, IN1, IN2, IN3) There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-ended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities. 3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3) Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a clock input. Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] 10 Selected Input Zero Delay Mode Disabled Zero Delay Mode Enabled 0 0 IN0 IN0 0 1 IN1 IN1 1 0 IN2 IN2 1 1 IN3 Reserved Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 10 Si5345/44/42 Rev D Data Sheet • Functional Description 3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3) An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated. 3.7.3 Hitless Input Switching Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz. 3.7.4 Ramped Input Switching When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover see 3.4.5 Holdover Mode. 3.7.5 Glitchless Input Switching The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no abrupt phase change at the output during the transition. 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 11 Si5345/44/42 Rev D Data Sheet • Functional Description 3.7.6 Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in Figure 14. Differential signals must be ac-coupled, while single-ended LVCMOS signals can be ac- or dc-coupled. Unused inputs can be disabled and left unconnected when not in use. Standard AC-Coupled Differential (IN0-IN3) 50 INx Standard INxb 50 LVDS, LVPECL, CML Pulsed CMOS Standard AC-Coupled Single-Ended (IN0-IN3) C1 RS R1 50 INx 3.3/2.5/1.8V LVCMOS R2 Standard INxb RS matches the CMOS driver to a 50 ohm transmission line (if used) Pulsed CMOS When 3.3V LVCMOS driver is present, C1 (optional), R1 and R2 may be needed to keep the signal at INx < 3.6 Vpp_se. See the Reference Manual for details. Pulsed CMOS DC-Coupled Single Ended only for Frequencies < 1MHz 3.3V, 2.5V, 1.8V LVCMOS RS R1 INx Standard 50 RS matches the CMOS driver to a 50 ohm transmission line (if used) INxb R2 Pulsed CMOS See the Reference Manual for details on R1 and R2 values. Figure 3.4. Termination of Differential and LVCMOS Input Signals Note: See Table 5.3 Input Clock Specifications on page 26 and the Si5345/44/42 Rev D Family Reference Manual for more information. 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 12 Si5345/44/42 Rev D Data Sheet • Functional Description 3.7.7 Synchronizing to Gapped Input Clocks The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in the following figure. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 2 3 4 5 6 7 8 9 1 10 Period Removed 10 ns 2 3 4 5 6 7 8 9 11.11111... ns Figure 3.5. Generating an Averaged Clock Output Frequency from a Gapped Clock Input A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification in Table 5.8 Performance Characteristics on page 32 when the switch occurs during a gap in either input clock. 3.8 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization. XA XB Si5345/44/42 OSC IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3/FB_INb ÷P0 LOS OOF Precision Fast ÷P1 LOS OOF Precision Fast ÷P2 LOS OOF Precision Fast ÷P3 LOS OOF Precision Fast LOS DSPLL LOL PD LPF ÷M Figure 3.6. Si5345/44/42 Fault Monitors 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 13 Si5345/44/42 Rev D Data Sheet • Functional Description 3.8.1 Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro software. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 3.7. LOS Status Indicators 3.8.2 XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 3.8.3 OOF Detection Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This OOF reference can be selected as either: • XA/XB pins • Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky register bit stays asserted until cleared. Monitor OOF Sticky en Precision LOS OOF Fast en Live Figure 3.8. OOF Status Indicator 14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 14 Si5345/44/42 Rev D Data Sheet • Functional Description 3.8.3.1 Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configurable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register configurable. OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) +4 ppm (Clear) 0 ppm +6 ppm (Set) OOF Reference Figure 3.9. Example of Precise OOF Monitor Assertion and Deassertion Triggers 3.8.3.2 Fast OOF Monitor Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. 3.8.4 LOL Detection The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor. LOL Monitor Sticky LOL Clear Timer LOL Set LOS LOL Live LOLb DSPLL fIN PD Feedback Clock LPF ÷M Si5345/44/42 Figure 3.10. LOL Status Indicators The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 15 Si5345/44/42 Rev D Data Sheet • Functional Description An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure. Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.1 1 10,000 Phase Detector Frequency Difference (ppm) Figure 3.11. LOL Set and Clear Thresholds Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro software. 3.8.5 Interrupt Pin (INTRb) An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the interrupt. 3.9 Outputs Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 16 Si5345/44/42 Rev D Data Sheet • Functional Description 3.9.1 Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in the figure below. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up. Multi N0n ÷ Synth N0d ÷R0 VDDO0 OUT0 OUT0b Multi N1n ÷ Synth N1d ÷R1 VDDO1 OUT1 OUT1b Multi N2n ÷ Synth N2d ÷R2 VDDO2 OUT2 OUT2b Multi N3n ÷ Synth N3d ÷R3 VDDO3 OUT3 OUT3b Multi N4n ÷ Synth N4d ÷R4 VDDO4 OUT4 OUT4b ÷R5 VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b ÷R7 VDDO7 OUT7 OUT7b ÷R8 VDDO8 OUT8 OUT8b ÷R9 VDDO9 OUT9 OUT9b Figure 3.12. MultiSynth to Output Driver Crosspoint 3.9.2 Output Signal Format The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 17 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 17 Si5345/44/42 Rev D Data Sheet • Functional Description 3.9.3 Differential Output Terminations The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below. Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. DC Coupled LVDS AC Coupled CML VDD – 1.3V VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V 50 50 OUTx 50 OUTx 100 OUTxb OUTxb 50 50 AC Coupled LVDS/LVPECL AC Coupled HCSL VDDRX LVDS: VDDO = 3.3V, 2.5V, 1.8V LVPECL: VDDO = 3.3V, 2.5V VDDO = 3.3V, 2.5V, 1.8V R1 OUTx 50 50 OUTx 50 100 OUTxb OUTxb 50 R1 50 Internally self-biased R2 R2 Standard HCSL Receiver Figure 3.13. Supported Differential Output Terminations Note: See the Si5345/44/42 Rev D Family Reference Manual for resistor values. 3.9.4 LVCMOS Output Terminations LVCMOS outputs are dc-coupled, as shown in the following figure. DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V 50 OUTx Rs OUTxb Si5345/44/42 50 Rs Figure 3.14. LVCMOS Output Terminations 3.9.5 Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential modes are programmable so that LVDS specifications can be met and for the best signal integrity with different supply voltages. When dc coupling the output driver, it is essential that the receiver have a relatively high common mode impedance so that the common mode current from the output driver is very small. 18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 18 Si5345/44/42 Rev D Data Sheet • Functional Description 3.9.6 LVCMOS Output Impedance Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source termination resistor is recommended to help match the selected output impedance to the trace impedance, where Rs = Transmission line impedance – ZO. There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each VDDO option as shown in the following table. Table 3.2. Typical Output Impedance (ZS) VDDO CMOS Drive Selections OUTx_CMOS_DRV = 1 OUTx_CMOS_DRV = 2 OUTx_CMOS_DRV = 3 3.3 V 38 Ω 30 Ω 22 Ω 2.5 V 43 Ω 35 Ω 24 Ω 1.8 V — 46 Ω 31 Ω 3.9.7 LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. 3.9.8 LVCMOS Output Polarity When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configurable, enabling complementary clock generation and/or inverted polarity with respect to other output drivers. 3.9.9 Output Enable/Disable The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high, all outputs are disabled. When held low, the outputs are enabled. Outputs in the enabled state can be individually disabled through register control. 3.9.10 Output Driver State When Disabled The disabled state of an output driver is configurable as disable low or disable high. 3.9.11 Synchronous Output Disable Feature The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete. 19 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 19 Si5345/44/42 Rev D Data Sheet • Functional Description 3.9.12 Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. Note that the hitless switching feature is not available when zero delay mode is enabled. IN0 ÷P0 IN0b IN1 Si5345/44/42 DSPLL ÷P1 IN1b IN2 PD ÷P2 IN2b LPF ÷M IN3/FB_IN 100 ÷P3 ÷R0 VDDO0 OUT0 OUT0b ÷N0 ÷R1 VDDO1 OUT1 OUT1b ÷N1 ÷R2 VDDO2 OUT2 OUT2b ÷R7 VDDO7 OUT7 OUT7b ÷R8 VDDO8 OUT8 OUT8b ÷R9 VDDO9 OUT9 OUT9b IN3/FB_INb ÷N2 ÷N3 ÷N4 External Feedback Path Figure 3.15. Si5345 Zero Delay Mode Setup 3.9.13 Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same result. 3.10 Power Management Unused inputs and output drivers can be powered down when unused. Consult the Si5345/44/42 Rev D Family Reference Manual and ClockBuilder Pro software for details. 3.11 In-Circuit Programming The Si5345/44/42 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5345/44/42 Rev D Family Reference Manual for a detailed procedure for writing registers to NVM. 20 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 20 Si5345/44/42 Rev D Data Sheet • Functional Description 3.12 Serial Interface Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire. See the Si5345/44/42 Rev D Family Reference Manual for details. 3.13 Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory preprogrammed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. The ClockBuilder Pro software can be used to quickly and easily generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your preprogrammed device will typically ship in about two weeks. 3.14 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices As with essentially all modern software utilities, the ClockBuilder Pro software is continually being updated and enhanced. By registering at www.silabs.com, you will be notified about changes and their impact. This update process will ultimately enable ClockBuilder Pro software users to access all features and register setting values documented in this data sheet and the Si5345/44/42 Rev D Family Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown in the following table. Table 3.3. Setting Overrides 21 Location Name Type Target Dec Value Hex Value 0x04535[0] FORCE_HOLD No NVM N/A 1 0x1 0x0B48[0:4] OOF_DIV_CLK_DIS User OPN&EVB 0 0x00 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 21 Si5345/44/42 Rev D Data Sheet • Functional Description Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the NVM file. The flowchart for this process is shown in the following figure. End: Place sample order Start Do I need a pre-programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Generate Custom OPN in CBPro Configure device using CBPro Yes Contact Silicon Labs Technical Support to submit & review your non-standard configuration request & CBPro project file Receive updated CBPro project file from Silicon Labs with “Settings Override” Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 3.16. Process for Requesting Non-Standard CBPro Features Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx. 22 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 22 Si5345/44/42 Rev D Data Sheet • Register Map 4. Register Map Refer to the Si5345/44/42 Rev D Family Reference Manual for a complete list of register descriptions and settings. 23 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 23 Si5345/44/42 Rev D Data Sheet • Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions1 VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Junction Temperature TJMAX — — 125 °C VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V 3.14 3.30 3.47 V 2.37 2.50 2.62 V 1.71 1.80 1.89 V 3.14 3.30 3.47 V 1.71 1.80 1.89 V Core Supply Voltage Clock Output Driver Supply Voltage Status Pin Supply Voltage VDDO VDDS Note: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. 24 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 24 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Table 5.2. DC Characteristics VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Core Supply Current1, 2, 3 Test Condition Min Typ Max Unit IDD — 135 260 mA IDDA — 120 130 mA — 22 26 mA — 15 18 mA — 22 30 mA — 18 23 mA — 12 16 mA Si53451 — 900 1200 mW Si53442 — 730 1000 mW Si53423 — 670 950 mW LVPECL Output4 @ 156.25 MHz LVDS Output4 @ 156.25 MHz Output Buffer Supply Current IDDOx 3.3 V LVCMOS Output5 @ 156.25 MHz 2.5 V LVCMOS Output5 @ 156.25 MHz 1.8 V LVCMOS Output5 @ 156.25 MHz Total Power Dissipation6 Pd Notes: 1. Si5345 test configuration: 7 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors. 2. Si5344 test configuration: 4 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors. 3. Si5342 test configuration: 2 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors. 4. Differential outputs terminated into an AC-coupled 100 Ω load. 5. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 4.7 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5345/44/42 Rev D Family Reference Manual for more details on register Differential Output Test Configuration LVCMOS Output Test Configuration Trace length 5 inches 499 IDDO OUT 50 0.1 uF OUTx 100 OUTb 50 50 Scope Input 50 IDDO 4.7pF 56 OUTxb 499 0.1 uF 50 Scope Input 50 4.7pF 56 settings. 6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 25 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Table 5.3. Input Clock Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit Standard AC-Coupled Differential or Single-Ended (IN0/IN0b, IN1/IN1b, IN2/IN2b, IN3/IN3b, FB_IN/FB_INb) Differential Input Frequency Range fIN All Single-ended signals (including LVCMOS) Differential AC-coupled fIN < 250 MHz Voltage Swing1 VIN Differential AC-coupled 250 MHz < fIN < 750 MHz Single-ended AC-coupled fIN < 250 MHz 0.008 — 750 MHz 0.008 — 250 MHz 100 — 1800 mVpp_se 225 — 1800 mVpp_se 100 — 3600 mVpp_se Slew Rate2, 3 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Input Capacitance CIN — 2.4 — pF RIN_DIFF — 16 — kΩ RIN_SE — 8 — kΩ fIN_LVCMOS 0.008 — 250 MHz fIN_PULSED_CMOS 0.008 — 1.0 MHz VIL –0.2 — 0.4 V VIH 0.8 — — V Slew Rate2, 3 SR 400 — — V/µs Minimum Pulse Width PW 1.6 — — ns Input Resistance RIN — 8 — kΩ Full operating range. Jitter performance may be reduced. 24.97 — 54.06 MHz Range for best jitter. 48 — 54 MHz TCXO frequency for SyncE applications. Jitter performance may be reduced. — 40 — MHz VIN_SE 365 — 2000 mVpp_se VIN_DIFF 365 2500 mVpp_diff SR 400 — V/µs Input Resistance Differential Input Resistance Single-Ended LVCMOS / Pulsed CMOS, DC-Coupled, Single-Ended (IN0, IN1, IN2, IN3, FB_IN)3 Input Frequency Input Voltage Pulse Input REFCLK (Applied to XA/XB) REFCLK Frequency Input Single-ended Voltage Swing Input Differential Voltage Swing Slew Rate2, 3 26 fIN_REF — Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 26 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Parameter Symbol Input Duty Cycle Test Condition DC Min Typ Max Unit 40 — 60 % Note: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Recommended for specified jitter performance. Jitter performance could degrade if the minimum slew rate specification is not met. (See the Si5345/44/42 Rev D Family Reference Manual for more information.) 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively) refer to the input attenuator circuit for dc-coupled pulsed LVCMOS in the Si5345/44/42 Rev D Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or Single-Ended ac-coupled input mode. Table 5.4. Control Input Pin Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit Si5345 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO) VIL — — 0.3 × VDDIO1 V VIH 0.7 × VDDIO1 — — V Input Capacitance CIN — 1.5 — pF Input Resistance RIN — 20 — kΩ Minimum Pulse Width PW RSTb, FINC and FDEC 100 — — ns Update Rate TUR FINC and FDEC 1 — — µs Input Voltage Si5344/42 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO) VIL — — 0.3 × VDDIO1 V VIH 0.7 × VDDIO1 — — V Input Capacitance CIN — 1.5 — pF Input Resistance RIN — 20 — kΩ Minimum Pulse Width PW 100 — — ns Input Voltage RSTb Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5345/44/42 Rev D Family Reference Manual for more details on the proper register settings. 27 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 27 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Table 5.5. Differential Clock Output Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ Max Unit 0.0001 — 720 MHz 733.33 — 800.00 MHz 825 — 1028 MHz MultiSynth used 0.0001 — 720 MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 1028 MHz 45 — 55 % — 0 75 ps — 0 50 ps Si5345/44/42 Output Frequency Duty Cycle DC Output-Output Skew Using Same MultiSynth OUT-OUTb Skew Output Voltage fOUT Swing1 TSKS MultiSynth not used Outputs on same MultiSynth (Measured at 712.5 MHz) TSK_OUT Measured from the positive to negative output pins VDDO = 3.3 V,2.5 V, 1.8 V LVDS 350 430 510 mVpp_se VDDO = 3.3 V, 2.5 V LVPECL 640 750 900 mVpp_se LVDS 1.10 1.2 1.3 V LVPECL 1.90 2.0 2.1 V 1.1 1.2 1.3 V 0.8 0.9 1.0 V tR/tF — 100 150 ps ZO — 100 — Ω 10 kHz sinusoidal noise — –101 — dBc 100 kHz sinusoidal noise — –96 — dBc 500 kHz sinusoidal noise — –99 — dBc 1 MHz sinusoidal noise — –97 — dBc Si5345 — –72 — dBc Si5342/44 — –88 — dBc VOUT VDDO = 3.3 V Common Mode Voltage1, 2 VCM (100 Ω load line-to-line) VDDO = 1.8 V Rise and Fall Times (20% to 80%) Differential Output Impedance Power Supply Noise Rejection2 Output-output Crosstalk3 28 PSRR XTALK LVPECL VDDO = 2.5 V LVDS sub-LVDS Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 28 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/EIA-644 maximum. Refer to the Si5345/44/42 Rev D Family Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude measured. 3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. 29 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 29 Si5345/44/42 Rev D Data Sheet • Electrical Specifications Table 5.6. LVCMOS Clock Output Specifications VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C Parameter Symbol Output Frequency fOUT Duty Cycle DC Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT