SI5347D-D-GM

Si5347/46 Rev D Data Sheet Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenuators The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5347/46 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration. Programming the Si5347/46 is easy with Silicon Labs' ClockBuilder Pro™ software. Factory preprogrammed devices are also available. KEY FEATURES • Four or two independent DSPLLs, any output frequency from any input frequency • Ultra-low jitter of 95 fs rms • Input frequency range: • External Crystal: 25–54 MHz • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range: • Differential: 100 Hz to 720 MHz • LVCMOS: 100 Hz to 250 MHz • Status Monitoring • Hitless switching • Si5347: 4 input, 8 output, 64-QFN 9×9 mm Applications • OTN Muxponders and Transponders • 10/40/100G network line cards • GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262) • Carrier Ethernet switches • Broadcast video • Si5346: 4 input, 4 output, 44-QFN 7×7 mm 25-54 MHz XTAL XA XB OSC OUT1 ÷INT OUT2 DSPLL A IN1 ÷FRAC DSPLL B ÷INT OUT3 IN2 ÷FRAC DSPLL C ÷INT OUT4 IN3 ÷FRAC DSPLL D ÷INT OUT5 ÷INT OUT6 ÷INT OUT7 I2C / SPI Si5347A/B ÷FRAC Si5347C/D ÷INT IN0 Status Flags 1 OUT0 Si5346A/B 4 Input Clocks ÷INT Status Monitor Control NVM Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 1 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 DSPLL Loop Bandwidth . 3.2.1 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . 6 3.3 Modes of Operation . . 3.3.1 Initialization and Reset 3.3.2 Free-run Mode . . 3.3.3 Lock Acquisition Mode 3.3.4 Locked Mode . . . 3.3.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . 8 3.5 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . 9 3.6 Inputs (IN0, IN1, IN2, IN3) . . . . . . 3.6.1 Input Selection . . . . . . . . 3.6.2 Manual Input Selection . . . . . . 3.6.3 Automatic Input Selection . . . . . 3.6.4 Input Configuration and Terminations . 3.6.5 Hitless Input Switching . . . . . . 3.6.6 Ramped Input Switching . . . . . 3.6.7 Glitchless Input Switching . . . . . 3.6.8 Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .10 .10 .11 .12 .12 .12 .12 3.7 Fault Monitoring . . . 3.7.1 Input LOS Detection. 3.7.2 XA/XB LOS Detection 3.7.3 OOF Detection . . 3.7.4 LOL Detection . . . 3.7.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .13 .14 .15 .17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 .18 .19 .19 .19 .19 .20 .20 .20 .21 .21 .21 .21 .21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Outputs . . . . . . . . . . . . . . . . . . . . 3.8.1 Output Crosspoint . . . . . . . . . . . . . . . 3.8.2 Differential Output Terminations . . . . . . . . . . . 3.8.3 LVCMOS Output Terminations . . . . . . . . . . . 3.8.4 Output Signal Format . . . . . . . . . . . . . . 3.8.5 Programmable Common Mode Voltage For Differential Outputs 3.8.6 LVCMOS Output Impedance Selection . . . . . . . . 3.8.7 LVCMOS Output Signal Swing . . . . . . . . . . . 3.8.8 LVCMOS Output Polarity . . . . . . . . . . . . . 3.8.9 Output Enable/Disable . . . . . . . . . . . . . . 3.8.10 Output Disable During LOL . . . . . . . . . . . . 3.8.11 Output Disable During XAXB_LOS . . . . . . . . . 3.8.12 Output Driver State When Disabled . . . . . . . . . 3.8.13 Synchronous/Asynchronous Output Disable . . . . . . 2 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 6 6 7 7 7 8 2 3.8.14 Output Divider (R) Synchronization . 3.9 Power Management . . . . . . . . . . . . . . . . . . . . .22 . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.10 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.11 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.12 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .22 3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 39 7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8. Typical Operating Characteristics (Jitter and Phase Noise) . . . . . . . . . . . . . 42 9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 . . . 10.1 Si5347 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . .49 10.2 Si5346 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . .50 11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 3 Si5347/46 Rev D Data Sheet • Feature List 1. Feature List The Si5347/46-D features are listed below: • Four or two DSPLLs to synchronize to multiple inputs • Generates any combination of output frequencies from any input frequency • Ultra low jitter: • 95 fs typ (12 kHz – 20 MHz) • Input frequency range: • Differential: 8 kHz to 750 MHz • LVCMOS: 8 kHz to 250 MHz • Output frequency range: • Differential: up to 720 MHz • LVCMOS: up to 250 MHz • Flexible crosspoints route any input to any output clock • Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz • Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude • Status monitoring (LOS, OOF, LOL) • Hitless input clock switching: automatic or manual 4 • • • • • • Locks to gapped clock inputs Automatic free-run and holdover modes Fastlock feature for low nominal bandwidths Glitchless on-the-fly DSPLL frequency changes DCO mode: as low as 0.01 ppb steps per DSPLL Core voltage: • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% • Independent output clock supply pins: 3.3, 2.5, or 1.8 V • Output-output skew: • Using same DSPLL: 65 ps (Max) • Serial interface: I2C or SPI • • • • • • In-circuit programmable with non-volatile OTP memory ClockBuilder Pro software simplifies device configuration Si5347: Quad DSPLL, 64-QFN 9×9 mm Si5346: Dual DSPLL, 44-QFN 7×7 mm Temperature range: –40 to +85 °C Pb-free, RoHS-6 compliant Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 4 Si5347/46 Rev D Data Sheet • Ordering Guide 2. Ordering Guide Table 2.1. Si5347/46 Ordering Guide Ordering Part Number Si5347A-D-GM1,2 Number Of DSPLLs Number of Outputs Output Clock Frequency Range Package RoHS-6, Pb-Free Temp Range 4 8 0.0001 to 720 MHz 64-Lead 9x9 QFN Yes –40 to 85 °C — — — — 0.0001 to 350 MHz Si5347B-D-GM1,2 4 Si5347C-D-GM1,2 0.0001 to 720 MHz 0.0001 to 350 MHz Si5347D-D-GM1,2 Si5346A-D-GM1,2 2 4 0.0001 to 720 MHz 0.0001 to 350 MHz Si5346B-D-GM1,2 Si5347-D-EVB — — — Si5346-D-EVB — — — 44-Lead 7x7 QFN Evaluation Board Notes: 1. Add an R at the end of the device part number to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software. Part number format is: Si5347A-Dxxxxx-GM or Si5346A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. Si534fg-Rxxxxx-GM Timing product family f = Multi-PLL clock family member (7, 6) g = Device grade (A, B, C, D) Product Revision* Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (QFN, -40 °C to +85°C) *See Ordering Guide table for current product revision ** 5 digits; assigned by ClockBuilder Pro Figure 2.1. Ordering Part Number Fields 5 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 5 Si5347/46 Rev D Data Sheet • Functional Description 3. Functional Description The Si5347 takes advantage of Silicon Labs’ 4th generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller form factor dual DSPLL version with four inputs and four outputs. 3.1 Frequency Configuration The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software. 3.2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. 3.2.1 Fastlock Feature Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting, as described in Section 3.2 DSPLL Loop Bandwidth. The fastlock feature can be enabled or disabled independently for each of the DSPLLs. 3.3 Modes of Operation Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 7. The following sections describe each of these modes in greater detail. 3.3.1 Initialization and Reset Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs, while a soft reset can either affect all or each DSPLL individually. 6 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 6 Si5347/46 Rev D Data Sheet • Functional Description Power-Up Reset and Initialization No valid input clocks selected Free-run Valid input clock selected Lock Acquisition (Fast Lock) An input is qualified and available for selection No valid input clocks available for selection Phase lock on selected input clock is achieved Locked Mode Holdover Mode Input Clock Switch Selected input clock fails Yes Yes No Holdover History Valid? Other Valid Clock Inputs No Available? Figure 3.1. Modes of Operation 3.3.2 Free-run Mode Once power is applied to the Si5347 and initialization is complete, all four DSPLLs will automatically enter Free-run Mode. The frequency accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in Free-run Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Holdover Mode. 3.3.3 Lock Acquisition Mode Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency. 3.3.4 Locked Mode Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point, any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is achieved. See 3.7.4 LOL Detection for more details on the operation of the loss of lock circuit. 7 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 7 Si5347/46 Rev D Data Sheet • Functional Description 3.3.5 Holdover Mode Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and delay are programmable, as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency data that may be corrupt just before the input clock failure. Clock Failure and Entry into Holdover Historical Frequency Data Collected time 120 seconds Programmable historical data window used to determine the final holdover value Programmable delay Figure 3.2. Programmable Holdover Window When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register programmable. Add new section The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on ramped input switching, see 3.6.6 Ramped Input Switching. Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable holdover exit BW. 3.4 Digitally-Controlled Oscillator (DCO) Mode The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words (FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO mode is available when the DSPLL is operating in either Free-run or Locked Mode. 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 8 Si5347/46 Rev D Data Sheet • Functional Description 3.5 External Reference (XA/XB) An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low jitter reference clock for the DSPLLs and for providing a stable reference for the Free-run and Holdover Modes. A simplified diagram is shown in the figure below. The device includes internal XTAL loading capacitors, which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to Table 5.12 Crystal Specifications1 on page 36 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. The Si5347-46 Rev D Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE line card PLL applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to provide a stable holdover reference. See the Si5347-46 Rev D Reference Manual for more information. Selection between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode. Refer to Table 5.3 Input Clock Specifications on page 27 for REFCLK requirements when using this mode. The Si5347-46 Rev D Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Although the REFCLK frequency range of 25 MHz to 54 MHz is supported, frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance. 25-54 MHz XO/Clock LVCMOS 25-54 MHz XO/Clock C1 is recommended to increase the slew rate at Xa C1 R1 See the Reference Manual for the recommended R1, R2, C1 values R2 25-54 MHz XTAL X2 XB XA 2xCL Note: See Pin Descriptions for X1/X2 connections NC X1 XB 2xCL 2xCL OSC NC X1 XA Crystal Resonator Connection NC X1 XA 2xCL 2xCL OSC ÷ PREF NC XB X2 X2 2xCL OSC ÷ PREF Differential XO/Clock Connection ÷ PREF LVCMOS XO/Clock Connection Figure 3.3. Crystal Resonator and External Reference Clock Connection Options Note: See Table 5.3 Input Clock Specifications on page 27 and the Si5347-46 Rev D Reference Manual for more information. 9 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 9 Si5347/46 Rev D Data Sheet • Functional Description 3.6 Inputs (IN0, IN1, IN2, IN3) There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs, as shown in the figure below. Si5347 Input Crosspoint IN0 IN0b IN1 IN1b IN2 IN2b IN3 IN3b ÷ P0n P0d ÷ P1n P1d P2n ÷ P2d P3n ÷ P3d 0 1 2 3 DSPLL A 0 1 2 3 DSPLL B 0 1 2 3 DSPLL C 0 1 2 3 DSPLL D Figure 3.4. DSPLL Input Selection Crosspoint 3.6.1 Input Selection Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine. 3.6.2 Manual Input Selection In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will automatically enter Holdover Mode. 3.6.3 Automatic Input Selection When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection. All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both the LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter the Holdover mode if there are no valid inputs available. 10 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 10 Si5347/46 Rev D Data Sheet • Functional Description 3.6.4 Input Configuration and Terminations Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be dc-coupled. Unused inputs can be disabled and left unconnected when not in use. Standard AC-Coupled Differential (IN0-IN3) 50 INx Standard INxb 50 LVDS, LVPECL, CML Pulsed CMOS Standard AC-Coupled Single-Ended (IN0-IN3) C1 RS R1 50 INx 3.3/2.5/1.8V LVCMOS R2 Standard INxb RS matches the CMOS driver to a 50 ohm transmission line (if used) Pulsed CMOS When 3.3V LVCMOS driver is present, C1 (optional), R1 and R2 may be needed to keep the signal at INx < 3.6 Vpp_se. See the Reference Manual for details. Pulsed CMOS DC-Coupled Single Ended only for Frequencies < 1MHz 3.3V, 2.5V, 1.8V LVCMOS RS R1 INx Standard 50 RS matches the CMOS driver to a 50 ohm transmission line (if used) INxb R2 Pulsed CMOS See the Reference Manual for details on R1 and R2 values. Figure 3.5. Termination of Differential and LVCMOS Input Signals Note: See Table 5.3 Input Clock Specifications on page 27 and the Si5347-46 Rev D Reference Manual for more information. 11 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 11 Si5347/46 Rev D Data Sheet • Functional Description 3.6.5 Hitless Input Switching Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL basis. 3.6.6 Ramped Input Switching When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.3.5 Holdover Mode. 3.6.7 Glitchless Input Switching The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output during the transition. 3.6.8 Synchronizing to Gapped Input Clocks Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in the figure below. Gapped Input Clock Periodic Output Clock 100 MHz clock 1 missing period every 10 90 MHz non-gapped clock 100 ns 100 ns DSPLL 1 10 ns 2 3 4 5 6 7 8 9 Period Removed 10 1 2 3 4 5 6 7 8 9 11.11111... ns Figure 3.6. Generating an Averaged Clock Output Frequency from a Gapped Clock Input A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification in Table 5.8 Performance Characteristics on page 32 when the switch occurs during a gap in either input clock. 12 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 12 Si5347/46 Rev D Data Sheet • Functional Description 3.7 Fault Monitoring All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF, as shown in the figure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indicator, which is asserted when synchronization is lost with their selected input clock. XA XB Si5347 OSC LOS DSPLL A LOL PD LPF ÷M IN0 IN0b IN1 IN1b IN2 IN2b ÷ P0n P0d LOS OOF Precision Fast ÷ P1n P1d LOS OOF Precision Fast ÷ P2n P2d LOS OOF Precision Fast ÷ P3n P3d LOS OOF Precision Fast DSPLL B LOL PD LPF ÷M DSPLL C LOL PD IN3 IN3b LPF ÷M DSPLL D LOL PD LPF ÷M Figure 3.7. Si5347 Fault Monitors 3.7.1 Input LOS Detection The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro software. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available. Monitor Sticky LOS LOS LOS en Live Figure 3.8. LOS Status Indicators 3.7.2 XA/XB LOS Detection A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected. 13 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 13 Si5347/46 Rev D Data Sheet • Functional Description 3.7.3 OOF Detection Each input clock is monitored for frequency accuracy with respect to an OOF reference, which it considers as its “0_ppm” reference. This OOF reference can be selected as either: • XA/XB pins • Any input clock (IN0, IN1, IN2, IN3) The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor, as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared. Monitor OOF Sticky en Precision LOS OOF Fast Live en Figure 3.9. OOF Status Indicator Precision OOF Monitor The precision OOF monitor circuit measures the frequency of all input clocks to within 1/16 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configurable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 – IN3) as the 0 ppm OOF reference instead of the XA/XB pins is available. This option is register-configurable. OOF Declared fIN Hysteresis Hysteresis OOF Cleared -6 ppm (Set) -4 ppm (Clear) 0 ppm OOF Reference +4 ppm (Clear) +6 ppm (Set) Figure 3.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers Fast OOF Monitor Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm. 14 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 14 Si5347/46 Rev D Data Sheet • Functional Description 3.7.4 LOL Detection There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has lost synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs (LOL_Ab, LOL_Bb, LOL_Cb, LOL_Db). The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL monitor. Si5347 Sticky LOS LOL Status Registers Live DSPLL D DSPLL C DSPLL B DSPLL A LOL Monitor LOL_Db LOL_Cb LOL Clear t LOL_Bb LOL_Ab LOL Set DSPLL A fIN PD LPF ÷M Figure 3.11. LOL Status Indicators Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more than 1 ppm frequency difference is shown in the figure below. 15 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 15 Si5347/46 Rev D Data Sheet • Functional Description Clear LOL Threshold Set LOL Threshold Lock Acquisition LOL Hysteresis Lost Lock LOCKED 0 0.1 1 10,000 Phase Detector Frequency Difference (ppm) Figure 3.12. LOL Set and Clear Thresholds An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro software. 16 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 16 Si5347/46 Rev D Data Sheet • Functional Description 3.7.5 Interrupt Pin (INTRb) An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers. Si5347 LOS_FLG 0x0012[0] IN0 OOF_FLG 0x0012[4] LOS_FLG 0x0012[1] IN1 OOF_FLG 0x0012[5] LOS_FLG 0x0012[2] IN2 OOF_FLG 0x0012[6] LOS_FLG 0x0012[3] IN2 OOF_FLG 0x0012[7] LOSXAXB_INTR_MSK 0x0017[1] CAL_FLG_PLL[A] 0x000F[4] CAL_FLG_PLL[B] 0x000F[5] CAL_FLG_PLL[C] 0x000F[6] INTRb CAL CAL_FLG_PLL[D] 0x000F[7] LOL_FLG_PLL[A] 0x0013[0] LOL_FLG_PLL[B] 0x0013[1] LOL_FLG_PLL[C] 0x0013[2] LOL LOL_FLG_PLL[D] 0x0013[3] HOLD_FLG_PLL[A] 0x0013[4] HOLD_FLG_PLL[B] 0x0013[5] HOLD_FLG_PLL[C] 0x0013[6] Hold HOLD_FLG_PLL[D] 0x0013[7] Figure 3.13. Interrupt Triggers and Masks 3.8 Outputs The Si5347 supports up to eight differential output drivers and the Si5346 supports four. Each driver has a configurable voltage amplitude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 16 single-ended outputs, or any combination of differential and single-ended outputs. 17 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 17 Si5347/46 Rev D Data Sheet • Functional Description 3.8.1 Output Crosspoint A crosspoint allows any of the output drivers to connect with any of the DSPLLs, as shown in the figure below. The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power-up. Si5347A/B DSPLL A DSPLL B DSPLL C DSPLL D Output Crosspoint A B C D ÷R0 VDDO0 OUT0 OUT0b A B C D ÷R1 VDDO1 OUT1 OUT1b A B C D ÷R2 VDDO2 OUT2 OUT2b A B C D ÷R3 VDDO3 OUT3 OUT3b ÷R4 VDDO4 OUT4 OUT4b A B C D ÷R5 VDDO5 OUT5 OUT5b A B C D ÷R6 VDDO6 OUT6 OUT6b A B C D ÷R7 VDDO7 OUT7 OUT7b A B C D Figure 3.14. Si5347A/B DSPLL to Output Driver Crosspoint 18 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 18 Si5347/46 Rev D Data Sheet • Functional Description 3.8.2 Differential Output Terminations Note: In this document, the terms "LVDS" and "LVPECL" refer to driver formats that are compatible with these signaling standards. The differential output drivers support both ac-coupled and dc-coupled terminations, as shown in the figure below. DC Coupled LVDS AC Coupled CML VDD – 1.3V LVDS: VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V 50 50 OUTx 50 OUTx 100 OUTxb OUTxb 50 50 AC Coupled LVDS/LVPECL AC Coupled HCSL VDDRX LVDS: VDDO = 3.3V, 2.5V, 1.8V LVPECL: VDDO = 3.3V, 2.5V VDDO = 3.3V, 2.5V, 1.8V R1 OUTx 50 50 OUTx 100 OUTxb OUTxb 50 Internally self-biased R1 50 50 R2 R2 Standard HCSL Receiver Figure 3.15. Supported Differential Output Terminations Note: See the Si5347/46 Rev D Family Reference Manual for resistor values. 3.8.3 LVCMOS Output Terminations LVCMOS outputs are dc-coupled, as shown in the figure below. DC Coupled LVCMOS 3.3 V, 2.5 V, 1.8 V LVCMOS VDDO = 3.3 V, 2.5 V, 1.8 V 50 OUTx Rs OUTxb Si5347/46 50 Rs Figure 3.16. LVCMOS Output Terminations 3.8.4 Output Signal Format The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 16 single-ended outputs or any combination of differential and single-ended outputs. 3.8.5 Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential modes is programmable and depends on the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers. 19 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 19 Si5347/46 Rev D Data Sheet • Functional Description 3.8.6 LVCMOS Output Impedance Selection Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO option, as shown in the table below. Note that selecting a lower source impedance may result in higher output power consumption. Table 3.1. Typical Output Impedance (ZS) VDDO CMOS_DRIVE_Selection OUTx_CMOS_DRV = 1 OUTx_CMOS_DRV = 2 OUTx_CMOS_DRV = 3 3.3 V 38 Ω 30 Ω 22 Ω 2.5 V 43 Ω 35 Ω 24 Ω 1.8 V — 46 Ω 31 Ω 3.8.7 LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. 3.8.8 LVCMOS Output Polarity When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configurable, which enables complementary clock generation and/or inverted polarity with respect to other output drivers. 20 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 20 Si5347/46 Rev D Data Sheet • Functional Description 3.8.9 Output Enable/Disable The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output enable pins are available (OE0b, OE1b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0b controls all of the outputs while OE1b remains unmapped and has no effect until configured. The figure below shows an example of an output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up. Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s) has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control. Si5346 Output Crosspoint DSPLL A DSPLL B A B ÷R0 OUT0 A B ÷R1 OUT1 ÷R2 OUT2 A B A B ÷R3 Si5346 Output Crosspoint OUT0b DSPLL A OUT1b A B ÷R0 OUT0 A B ÷R1 OUT1 OUT0b OUT1b OE0b OUT2b OUT3 DSPLL B A B ÷R2 A B ÷R3 OUT2 OUT2b OUT3b OUT3 OUT3b OE0b OE1b In its default state the OE0b pin enables/disables all outputs. The OE1b pin is not mapped and has no effect on outputs. OE1b An example of a configurable output enable scheme. In this case OE0b controls the outputs associated with DSPLL A, while OE1b controls the outputs of DSPLL B. Figure 3.17. Example of Configuring Output Enable Pins 3.8.10 Output Disable During LOL By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover. 3.8.11 Output Disable During XAXB_LOS The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition. 3.8.12 Output Driver State When Disabled The disabled state of an output driver is register configurable as disable low or disable high. 3.8.13 Synchronous/Asynchronous Output Disable Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete. 21 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 21 Si5347/46 Rev D Data Sheet • Functional Description 3.8.14 Output Divider (R) Synchronization All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same result. 3.9 Power Management Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5347-46 Rev D Reference Manual and the ClockBuilder Pro software for details. 3.10 In-Circuit Programming The Si5347/46 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5347-46 Rev D Reference Manual for a detailed procedure for writing registers to NVM. 3.11 Serial Interface Configuration and operation of the Si5347/46 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or 3-wire mode. See the Si5347-46 Rev D Reference Manual for details. 3.12 Custom Factory Preprogrammed Parts For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard to quickly and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in about two weeks. 3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices As with essentially all modern software utilities, the ClockBuilder Pro software is continuously updated and enhanced. By registering at www.silabs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will ultimately enable ClockBuilder Pro software users to access all features and register setting values documented in this data sheet and the Si5347-46 Rev D Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled using what is referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown in the table below. Table 3.2. Setting Overrides Location Name Type Target Dec Value Hex Value 0x0535[0] FORCE_HOLD_PLLB No NVM N/A 1 0x1 0x0B48[4:0] OOF_DIV_CLK_DIS User OPN and EVB 31 0x1F Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the NVM file. The flowchart for this process is shown in the figure below. 22 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 22 Si5347/46 Rev D Data Sheet • Functional Description End: Place sample order Start Do I need a pre-programmed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro Generate Custom OPN in CBPro Yes Contact Silicon Labs Technical Support to submit & review your non-standard configuration request & CBPro project file Receive updated CBPro project file from Silicon Labs with “Settings Override” Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 3.18. Process for Requesting Non-Standard CBPro Features Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx. 23 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 23 Si5347/46 Rev D Data Sheet • Register Map 4. Register Map Refer to the Si5347-46 Rev D Reference Manual for a complete list of register descriptions and settings. 24 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 24 Si5347/46 Rev D Data Sheet • Electrical Specifications 5. Electrical Specifications Table 5.1. Recommended Operating Conditions (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit Ambient Temperature TA –40 25 85 °C Junction Temperature TJMAX — — 125 °C VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V 3.14 3.30 3.47 V 2.37 2.50 2.62 V 1.71 1.80 1.89 V 3.14 3.30 3.47 V 1.71 1.80 1.89 V Core Supply Voltage Output Driver Supply Voltage Status Pin Supply Voltage VDDO VDDS Note: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. 25 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 25 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.2. DC Characteristics (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol IDD Core Supply Current1, 2 IDDA Test Condition Min Typ Max Unit Si5347, 4 DSPLLs — 300 450 mA S5347, 1 DSPLL — 190 340 mA Si5346 — 185 280 mA Si5347, 4 DSPLLs — 125 140 mA Si5347, 1 DSPLL — 125 140 mA Si5346 — 125 140 mA — 22 26 mA — 15 18 mA — 22 30 mA — 18 23 mA — 12 16 mA Si5347, 4 DSPLLs1 — 1200 1600 mW Si5347, 1 DSPLL1 — 1050 1420 mW Si53462 — 880 1100 mW LVPECL Output3 @ 156.25 MHz LVDS Output3 @ 156.25 MHz Output Buffer Supply Current 3.3 V LVCMOS4 Output IDDO @ 156.25 MHz 2.5 V LVCMOS4 Output @ 156.25 MHz 1.8 V LVCMOS4 Output @ 156.25 MHz Total Power Dissipation5 Pd Notes: 1. Si5347 test configuration: 7×2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5346 test configuration: 4×2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an AC coupled 100 Ω load. 4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 4.7 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347-46 Rev D Reference Manual for more details on register settings. 5. Detailed power consumption for any configuration can be estimated using the ClockBuilder Pro software when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. Differential Output Test Configuration LVCMOS Output Test Configuration Trace length 5 inches 499 IDDO OUT 50 0.1 uF OUTx 100 OUTb 50 50 Scope Input 50 IDDO 4.7pF 499 0.1 uF 50 Scope Input 50 4.7pF 26 56 OUTxb 56 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 26 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.3. Input Clock Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 0.008 — 750 MHz 0.008 — 250 MHz 100 — 1800 mVpp_se 225 — 1800 mVpp_se 100 — 3600 mVpp_se Standard AC-Coupled Differential or Single-Ended (IN0/IN0b, IN1/IN1b, IN2/IN2b, IN3/IN3b) Differential Input Frequency Range fIN All Single-ended signals (including LVCMOS) Differential AC-coupled fIN < 250 MHz Voltage Swing1 VIN Differential AC-coupled 250 MHz < fIN < 750 MHz Single-ended AC-coupled fIN< 250 MHz Slew Rate2,3 SR 400 — — V/µs Duty Cycle DC 40 — 60 % Input Capacitance CIN — 2.4 — pF RIN_DIFF — 16 — kΩ RIN_SE — 8 — kΩ 0.008 — 250 MHz 0.008 — 1.0 MHz VIL –0.2 — 0.4 V VIH 0.8 — — V Slew Rate2,3 SR 400 — — V/µs Minimum Pulse Width PW 1.6 — — ns Input Resistance RIN — 8 — kΩ Full operating range. Jitter performance may be reduced. 24.97 — 54.06 MHz Range for best jitter. 48 — 54 MHz VIN_DIFF 365 — 2500 mVpp_diff VIN_SE 365 — 2000 mVpp_se 400 — — V/µs 40 — 60 % Input Resistance Differential Input Resistance Single-ended LVCMOS / Pulsed CMOS, DC-Coupled, Single-Ended (IN0, IN1, IN2, IN3)4 fIN_LVCMOS Input Frequency fIN_PULSED_CM OS Input Voltage Pulse Input REFCLK (Applied to XA/XB) REFCLK Frequency Input Voltage Swing fIN_REF Slew rate2,3 SR Input Duty Cycle DC 27 Imposed for best jitter performance Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 27 Si5347/46 Rev D Data Sheet • Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Voltage swing is specified as single-ended mVpp. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 2. Recommended for specified jitter performance. Jitter performance can degrade if the minimum slew rate specification is not met (see Si5347-46 Rev D Reference Manual). 3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR. 4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for DC-coupled Pulsed LVCMOS in the Si5347-46 Rev D Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard AC-coupled, Single-ended input mode. Table 5.4. Serial and Control Input Pin Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Si5347 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, A1/SDO, SCLK, A0/CSb, FINC, A0/CSb, SDA/SDIO, DSPLL_SEL[1:0]) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 1.5 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW RSTb, FINC 100 — — ns Update Rate FUR FINC — — 1 MHz VIL — — 0.3 x VDDS V VIH 0.7 x VDDS — — V Input Capacitance CIN — 1.5 — pF Minimum Pulse Width PW FDEC 100 — — ns Update Rate FUR FDEC — — 1 MHz Input Voltage Si5347 Control Input Pins (FDEC, OE1b) Input Voltage Si5346 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, OE1b, A1/SDO, SCLK, A0/CSb, SDA/SDIO) VIL — — 0.3 x VDDIO1 V VIH 0.7 x VDDIO1 — — V Input Capacitance CIN — 1.5 — pF Input Resistance RL — 20 — kΩ Minimum Pulse Width PW 100 — — ns Input Voltage RSTb Note: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. 28 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 28 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-Output Skew TSKS Using Same DSPLL TSK_OUT OUT-OUTb Skew Output Voltage Amplitude1 Test Condition Min Typ Max Unit 0.0001 — 720 MHz fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 720 MHz 45 — 55 % — 0 75 ps — 0 50 ps 350 430 510 Outputs on same DSPLL (Measured at 720 MHz) Measured from positive to negative output pins VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS VDDO = 3.3 V, 2.5 V LVPECL 640 750 900 LVDS 1.10 1.20 1.30 LVPECL 1.90 2.00 2.10 VDDO = 2.5 V LVPECL, LVDS 1.10 1.20 1.30 VDDO = 1.8 V sub-LVDS 0.80 0.90 1.00 tR/tF — 100 150 ps ZO — 100 — Ω 10 kHz sinusoidal noise — –101 — dBc 100 kHz sinusoidal noise — –96 — dBc 500 kHz sinusoidal noise — –99 — dBc 1 MHz sinusoidal noise — –97 — dBc Si5347 — –72 — dB Si5346 — –88 — dB VOUT mVpp_se VDDO = 3.3 V Common Mode Voltage1,2 Rise and Fall Times (20% to 80%) Differential Output Impedance Power Supply Noise Rejection2 Output-output Crosstalk3 VCM PSRR XTALK V Notes: 1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/ EIA-644 maximum. Refer to the Si5347-46 Rev D Reference Manual for more suggested output settings. Not all combinations of voltage amplitude and common mode voltages settings are possible. 2. Measured for 156.25 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO = 3.3 V and noise spur amplitude measured. 3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTxb 29 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 29 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.6. LVCMOS Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Test Condition Min Typ Max Unit 0.0001 — 250 MHz fOUT 1 MHz. Consult your CBPro Design report for the Fpfd frequency of your configuration. 32 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 32 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.9. I2C Timing Specifications (SCL, SDA) Parameter SCL Clock Frequency SMBus Timeout Symbol Fast Mode 100 kbps 400 kbps Test Condition fSCL — Standard Mode When Timeout is Enabled Unit Min Max Min Max — 100 — 400 kHz 25 35 25 35 ms Hold Time (repeated) START Condition tHD:STA 4.0 — 0.6 — µs Low Period of the SCL Clock tLOW 4.7 — 1.3 — µs HIGH Period of the SCL Clock tHIGH 4.0 — 0.6 — µs Set-up Time for a Repeated START Condition tSU:STA 4.7 — 0.6 — µs Data Hold Time tHD:DAT 100 — 100 — ns Data Set-up Time tSU:DAT 250 — 100 — ns Rise Time of Both SDA and SCL Signals tr — 1000 20 300 ns Fall Time of Both SDA and SCL Signals tf — 300 — 300 ns Set-up Time for STOP Condition tSU:STO 4.0 — 0.6 — µs Bus Free Time between a STOP and START Condition tBUF 4.7 — 1.3 — µs Data Valid Time tVD:DAT — 3.45 — 0.9 µs Data Valid Acknowledge Time tVD:ACK — 3.45 — 0.9 µs 33 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 33 Si5347/46 Rev D Data Sheet • Electrical Specifications Figure 5.1. I2C Serial Port Timing Standard and Fast Modes Table 5.10. SPI Timing Specifications (4-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Unit SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDO Active TD1 — — 18 ns Delay Time, SCLK Fall to SDO TD2 — — 15 ns Delay Time, CSb Rise to SDO Tri-State TD3 — — 15 ns Setup Time, CSb to SCLK TSU1 5 — — ns Hold Time, SCLK Fall to CSb TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CSb) TCS 2 — — TC 34 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 34 Si5347/46 Rev D Data Sheet • Electrical Specifications TSU1 TD1 TC SCLK TH1 CSb TSU2 TH2 TCS SDI TD2 TD3 SDO Figure 5.2. 4-Wire SPI Serial Interface Timing Table 5.11. SPI Timing Specifications (3-Wire) (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Min Typ Max Units SCLK Frequency fSPI — — 20 MHz SCLK Duty Cycle TDC 40 — 60 % SCLK Period TC 50 — — ns Delay Time, SCLK Fall to SDIO Turn-on TD1 — — 20 ns Delay Time, SCLK Fall to SDIO Next-bit TD2 — — 15 ns Delay Time, CSb Rise to SDIO Tri-State TD3 — — 15 ns Setup Time, CSb to SCLK TSU1 5 — — ns Hold Time, SCLK Fall to CSb TH1 5 — — ns Setup Time, SDI to SCLK Rise TSU2 5 — — ns Hold Time, SDI to SCLK Rise TH2 5 — — ns Delay Time Between Chip Selects (CSb) TCS 2 — — TC TSU1 TC SCLK TD1 CSb TSU2 TH1 TD2 TH2 TCS SDIO TD3 Figure 5.3. 3-Wire SPI Serial Interface Timing 35 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 35 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.12. Crystal Specifications1 Parameter Crystal Frequency Range Symbol Test Condition Min Typ Max Unit fXTAL Full operating range. Jitter performance may be reduced. 24.97 — 54.06 MHz Range for best jitter. 48 — 54 MHz Load Capacitance CL — 8 — pF Crystal Drive Level dL — — 200 µW Equivalent Series Resistance Shunt Capacitance rESR CO Refer to the Si5347-46 Rev D Reference Manual to determine ESR and shunt capacitance. Notes: 1. Refer to the Si534x/8x Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48 to 54 MHz crystals. The Si5348 is designed to only work with crystals that meet these specifications and not with XOs. 36 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 36 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.13. Thermal Characteristics Parameter Symbol Test Condition1 Value Still Air 22 Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.3 Unit Si5347–64QFN Thermal Resistance Junction to Ambient Thermal Resistance θJA θJC 9.5 Thermal Resistance θJB 9.4 Junction to Board ψJB 9.3 ψJT 0.2 Junction to Case Thermal Resistance Junction to Top Center °C/W Si5346–44QFN Thermal Resistance Junction to Ambient Thermal Resistance θJA Still Air 22.3 Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.4 θJC 10.9 Thermal Resistance θJB 9.3 Junction to Board ψJB 9.2 ψJT 0.23 Junction to Case Thermal Resistance Junction to Top Center °C/W Note: 1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4 37 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 37 Si5347/46 Rev D Data Sheet • Electrical Specifications Table 5.14. Absolute Maximum Ratings1, 2, 3, 4 Parameter DC Supply Voltage Symbol Value Unit VDD –0.5 to 3.8 V VDDA –0.5 to 3.8 V VDDO –0.5 to 3.8 V VDDS –0.5 to 3.8 V –1.0 to 3.8 V –0.5 to 3.8 V –0.5 to 2.7 V VI15 Test Condition IN0 – IN3 RSTb, OE0b, OE1b, I2C_SEL, Input Voltage Range VI2 FINC, FDEC, PLL_SEL[1:0] SDA/SDIO, A1/SDO, SCLK, A0/CSb VI3 Latch-up Tolerance XA/XB LU ESD Tolerance HBM Max Junction Temperature in Operation JESD78 Compliant 2.0 kV TJCT 125 °C Storage Temperature Range TSTG –55 to 150 °C Soldering Temperature (Pb-free profile)3 TPEAK 260 °C TP 20–40 s Soldering Temperature Time at TPEAK (Pb-free profile)4 100 pF, 1.5 kΩ Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. 64-QFN and 44-QFN packages are RoHS-6 compliant. 3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx. 4. The device is compliant with JEDEC J-STD-020. 5. The minimum voltage at these pins can be as low as –1.0 V when an AC input signal of 10 MHz or greater is applied. See Table 5.3 Input Clock Specifications on page 27 spec for Single-ended AC Coupled fIN < 250 MHz. 38 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 38 Si5347/46 Rev D Data Sheet • Typical Application Schematic 6. Typical Application Schematic OTN Muxponder Si5347 Client #1 Data Clock PD ÷ Gapped Clock PHY 10GbE PHY 10GbE PHY 10GbE PHY 10GbE LPF Mn_A Md_A DSPLL A Non-gapped Jitter Attenuated Clock Client #2 Data Clock 40G OTN PD LPF ÷ Gapped Clock Mn_B Md_B OTN De-Mapper DSPLL B Non-gapped Jitter Attenuated Clock Client #3 Data Clock PD LPF ÷ Gapped Clock Mn_C Md_C DSPLL C Non-gapped Jitter Attenuated Clock Client #4 Data Clock PD Gapped Clock LPF ÷ Mn_D Md_D DSPLL D Non-gapped Jitter Attenuated Clock Figure 6.1. Using the Si5347 to Clean Gapped Clocks in an OTN Application 39 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 39 Si5347/46 Rev D Data Sheet • Detailed Block Diagrams 48-54MHz XTAL or REFCLK VDDA VDD VDDS 7. Detailed Block Diagrams 3 XA Si5347 XB OSC ÷ PXAXB PD DSPLL A IN0b IN1 IN1b IN2 IN2b ÷ P0n P0d ÷ P1n P1d ÷ P2n P2d PD DSPLL B IN3b DSPLL C ÷ Mn_B Md_B LPF ÷ Mn_C Md_C LPF ÷ Mn_D Md_D ÷R1 VDDO1 OUT1 OUT1b ÷R2 VDDO2 OUT2 OUT2b ÷R3 VDDO3 OUT3 OUT3b ÷R4 VDDO4 OUT4 OUT4b ÷R5 VDDO5 OUT5 OUT5b ÷R6 VDDO6 OUT6 OUT6b ÷R7 VDDO7 OUT7 OUT7b NVM Si5347A/B PD DSPLL D Mn_A Md_A LPF PD P3n ÷ P3d IN3 ÷ VDDO0 OUT0 OUT0b Si5347C/D IN0 LPF ÷R0 I2C_SEL SDA/SDIO A1/SDO SCLK SPI/ I2C Status Monitors A0/CSb OE1b OE0b FDEC DSPLL_SEL[1:0] FINC LOS_XAXB INTRb LOL_Db LOL_Cb LOL_Bb LOL_Ab RSTb 2 Figure 7.1. Si5347 Block Diagram 40 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 40 VDDA VDD VDDS Si5347/46 Rev D Data Sheet • Detailed Block Diagrams 4 2 Si5346 48-54MHz XTAL or REFCLK XA XB OSC ÷PREF IN0 ÷ IN0b IN1 ÷ IN1b P0n P0d P1n P1d P2n ÷ P2d IN2 IN2b P3n ÷ P3d IN3 IN3b PD DSPLL A PD VDDO0 OUT0 OUT0b ÷R1 VDDO1 OUT1 OUT1b ÷R2 VDDO2 OUT2 OUT2b ÷R3 VDDO3 OUT3 OUT3b LPF Mn_A ÷ Md_A LPF Mn_B ÷ Md_B DSPLL B ÷R0 I2C_SEL OE1b OE0b Status Monitors LOS_XAXB RSTb A0/CSb NVM INTRb SCLK SPI/ I2C LOL_Bb A1/SDO LOL_Ab SDA/SDIO Figure 7.2. Si5346 Block Diagram 41 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 41 Si5347/46 Rev D Data Sheet • Typical Operating Characteristics (Jitter and Phase Noise) 8. Typical Operating Characteristics (Jitter and Phase Noise) Figure 8.1. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS Figure 8.2. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS 42 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 42 Si5347/46 Rev D Data Sheet • Typical Operating Characteristics (Jitter and Phase Noise) Figure 8.3. Input = 19.44 MHz; Output = 644.53125 MHz, 2.5 V LVDS Figure 8.4. Input = 25 MHz; Output = 644.53125 MHz, 2.5 V LVDS 43 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 43 Si5347/46 Rev D Data Sheet • Pin Descriptions 9. Pin Descriptions VDD I2C_SEL OE1b OUT3 OUT3b VDDO3 38 37 35 34 IN3 VDD 39 IN3b 41 VDDO5 49 IN0 OUT5b 50 42 OUT5 51 IN0b VDDO6 52 48 2 47 LOL_Db LOL_Ab 3 46 VDD IN1 1 33 LOS_XAXBb LOL_Bb LOL_Cb 4 45 OUT4 IN1b 2 32 5 44 OUT4b RSTb 3 31 VDD OUT2 RSTb X1 6 43 VDDO4 X1 4 30 OUT2b 7 42 FDEC XA 5 29 VDDO2 XA 8 41 OE1b XB 6 XB 9 40 VDDS 7 8 26 VDDS 9 25 OUT1 36 1 40 IN1 IN1b GND Pad FINC 43 OUT6b 53 Si5346 44QFN Top View 44 RSVD OUT6 54 RSVD 56 55 VDDO7 57 VDD 60 OUT7 IN3 61 OUT7b IN3b 62 58 IN0 63 59 IN0b 64 Si5347A/B 64QFN Top View GND Pad 28 LOL_Ab 27 LOL_Bb 23 24 25 26 27 28 29 30 31 32 OUT0b OUT0 LOS_XAXBb DSPLL_SEL0 DSPLL_SEL1 NC VDDO1 OUT1b OUT1 VDD A1/SDO 22 VDDO0 SCLK 21 RSVD 12 OE0b SDA/SDIO 20 RSVD VDDO2 19 33 A0/CSb 16 17 OUT2b SCLK 18 34 A1/SDO 35 15 SDA/SDIO 14 22 OUT2 IN2 IN2b 21 VDDO1 NC OUT1b 23 20 24 11 19 10 IN2b OUT0 VDD IN2 VDDO3 OUT0b OUT3b 36 18 37 13 17 12 VDDA INTRb INTRb VDDO0 VDDA 16 OUT3 A0/CSb I2C_SEL 38 15 39 11 14 10 OE0b 13 X2 X2 VDDA RSVD RSVD RSVD RSVD RSVD RSVD OUT3 OUT3b VDDO3 57 56 55 54 53 52 51 50 49 VDD 60 RSVD IN3 61 RSVD IN3b 62 58 IN0 63 59 IN0b 64 Si5347C/D 64QFN Top View IN1 1 48 IN1b 2 47 LOL_Db LOL_Ab 3 46 VDD LOL_Bb LOL_Cb 4 45 OUT2 5 44 OUT2b RSTb X1 6 43 VDDO2 7 42 FDEC XA 8 41 OE1b 40 VDDS GND Pad FINC 28 29 30 31 NC RSVD RSVD RSVD VDD 32 27 DSPLL_SEL1 RSVD 26 RSVD 33 DSPLL_SEL0 34 16 25 15 24 IN2b SCLK OUT0 RSVD LOS_XAXBb 35 23 14 OUT0b VDDO1 IN2 22 OUT1b 36 21 37 13 RSVD 12 VDDA VDDO0 INTRb 20 OUT1 RSVD 38 19 11 A0/CSb I2C_SEL OE0b 18 39 SDA/SDIO 10 17 9 X2 A1/SDO XB Figure 9.1. Si5347/46 Pin Descriptions 44 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 44 Si5347/46 Rev D Data Sheet • Pin Descriptions Table 9.1. Si5347/46 Pin Descriptions1 Pin Name Pin Number Pin Type2 Function Crystal Input. Input pin for external crystal (XTAL). Alternatively these pins can be driven with an external reference clock (REFCLK). An internal register bit selects XTAL or REFCLK mode. Default is XTAL mode. Si5347A/B Si5347C/D Si5346 XA 8 8 5 I XB 9 9 6 I X1 7 7 4 I X2 10 10 7 I IN0 63 63 43 I IN0b 64 64 44 I IN1 1 1 1 I IN1b 2 2 2 I IN2 14 14 10 I IN2b 15 15 11 I IN3 61 61 41 I IN3b 62 62 42 I OUT0 24 24 20 O OUT0b 23 23 19 O OUT1 31 38 25 O OUT1b 30 37 24 O OUT2 35 45 31 O OUT2b 34 44 30 O OUT3 38 51 36 O OUT3b 37 50 35 O OUT4 45 — — O OUT4b 44 — — O OUT5 51 — — O OUT5b 50 — — O OUT6 54 — — O OUT6b 53 — — O OUT7 59 — — O OUT7b 58 — — O Inputs XTAL Ground. Connect these pins directly to the XTAL ground pins. X1, X2, and the XTAL ground pins should be separated from the PCB ground plane. Refer to the Si5347-46 Rev D Reference Manual for layout guidelines. These pins should be left disconnected when connecting XA/XB pins to an external reference clock (REFCLK). Clock Inputs. These pins accept an input clock for synchronizing the device. They support both differential and single-ended clock signals. Refer to 3.6.4 Input Configuration and Terminations for input termination options. These pins are high-impedance and must be terminated externally. The negative side of the differential input must be grounded when accepting a single-ended clock. Outputs 45 Output Clocks. These output clocks support a programmable signal amplitude and common mode voltage. Desired output signal format is configurable using register control. Termination recommendations are provided in 3.8.2 Differential Output Terminations and 3.8.3 LVCMOS Output Terminations. Unused outputs should be left unconnected. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 45 Si5347/46 Rev D Data Sheet • Pin Descriptions Pin Name Pin Number Pin Type2 Function Si5347A/B Si5347C/D Si5346 I2C_SEL 39 39 38 I SDA/SDIO 18 18 13 I/O Serial Data Interface.3 This is the bidirectional data pin (SDA) for the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When in I2C mode, this pin must be pulled-up using an external resistor of > 1 kΩ. No pull-up resistor is needed when in SPI mode. A1/SDO 17 17 15 I/O Address Select 1/Serial Data Output.3 In I2C mode this pin functions as the A1 address input pin. In 4-wire SPI mode this is the serial data output (SDO) pin. SCLK 16 16 14 I Serial Clock Input.3 This pin functions as the serial clock input for both I2C and SPI modes. When in I2C mode, this pin must be pulled-up using an external resistor of > 1 kΩ. No pull-up resistor is needed when in SPI mode. A0/CSb 19 19 16 I Address Select 0/Chip Select.3 This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin functions as the chip select input (active low). This pin is internally pulled-up. INTRb 12 12 17 O Interrupt.3 This pin is asserted low when a change in device status has occurred. It should be left unconnected when not in use. RSTb 6 6 3 I Device Reset.3 Active low input that performs power-on reset (POR) of the device. Resets all internal logic to a known state and forces the device registers to their default values. Clock outputs are disabled during reset. This pin is internally pulled-up. OE0b 11 11 12 I Output Enable 0.3 This pin is used to enable (when held low) and disable (when held high) the output clocks. By default this pin controls all outputs. It can also be configured to control a subset of outputs. See 3.8.9 Output Enable/Disable for details. This pin is internally pulled-down. OE1b 41 41 — Output Enable 1. (Si5347)4 This is an additional output enable pin that can be configured to control a subset of outputs. By default it has no control on the outputs until configured. See 3.8.9 Output Enable/Disable for details. There is no internal pull-up/pull-down for this pin. This pin must be pulled up or down externally (do not leave floating when not in use). — — 37 Output Enable 1. (Si5346)3 This is an additional output enable pin that can be configured to control a subset of outputs. By default it has no control on the outputs until configured. See 3.8.9 Output Enable/Disable for details. This pin is internally pulled-down. Serial Interface I2C Select.3 This pin selects the serial interface mode as I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled high. Control/Status 46 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 46 Si5347/46 Rev D Data Sheet • Pin Descriptions Pin Name Pin Number Pin Type2 Function Si5347A/B Si5347C/D Si5346 LOL_Ab 3 3 28 O LOL_Bb 4 4 27 O LOL_Cb 5 5 — O LOL_Db 47 47 — O LOS_XAXBb 25 25 33 O Status Pins.3 This pin indicates a loss of signal alarm on the XA/XB pins. This either indicates a XTAL failure or a loss of external signal on the XA/XB pins. This pin can be left unconnected when unused. DSPLL_SEL 0 26 26 — I DSPLL_SEL 1 27 27 — I DSPLL Select Pins (Si5347 only).3 These pins are used in conjunction with the FINC and FDEC pins. The DSPLL_SEL[1:0] pins determine which DSPLL is affected by a frequency change using the FINC and FDEC pins. See 3.4 Digitally-Controlled Oscillator (DCO) Mode for details. These pins are internally pulled-down. FDEC 42 42 — I Frequency Decrement Pin (Si5347 only).4 This pin is used to step-down the output frequency of a selected DSPLL. The frequency change step size is register configurable. The DSPLL that is affected by the frequency change is determined by the DSPLL_SEL[1:0] pins. This pin must be pulled up or down externally (do not leave floating when not in use). FINC 48 48 — I Frequency Increment Pin (Si5347 only).3 This pin is used to step-up the output frequency of a selected DSPLL. The frequency change step size is register configurable. The DSPLL that is affected by the frequency change is determined by the DSPLL_SEL[1:0] pins. This pin is pulled low internally and can be left unconnected when not in use. RSVD 20 20 — — 21 21 — — — 29 — — — 30 — — — 31 — — — 33 — — — 34 — — — 35 — — — 52 — — — 53 — — — 54 — — 55 55 — — 56 56 — — — 57 — — — 58 — — — 59 — — 47 Loss Of Lock_A/B/C/D.3, 4 These output pins indicate when DSPLL A, B, C, D is out-of-lock (low) or locked (high). They can be left unconnected when not in use. Si5347: See Note 3, Si5346: See Note 4. Reserved. These pins are connected to the die. Leave disconnected. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 47 Si5347/46 Rev D Data Sheet • Pin Descriptions Pin Name Pin Number Pin Type2 Function Si5347A/B Si5347C/D Si5346 28 28 22 — No Connect. These pins are not connected to the die. Leave disconnected. 32 32 21 P 46 46 32 60 60 39 Core Supply Voltage. The device core operates from a 1.8 V supply. See the Si5347-46 Rev D Reference Manual for power supply filtering recommendations. A 0402 1 µF capacitor should be placed very near each of these pins. — — 40 13 13 8 P — — 9 P Core Supply Voltage 3.3 V. This core supply pin requires a 3.3 V power source. See the Si5347-46 Rev D Reference Manual for power supply filtering recommendations. A 0402 1 µF capacitor should be placed very near each of these pins. VDDS 40 40 26 P Status Output Voltage. The voltage on this pin determines VOL/VOH on the Si5346 LOL_Ab and LOL_Bb outputs. On the Si5347, this pin determines VIL/VIH for the FDEC and OE1b inputs. Connect to either 3.3 V or 1.8 V. A 0.1 µF bypass capacitor should be placed very close to this pin. VDDO0 22 22 18 P VDDO1 29 36 23 P VDDO2 33 43 29 P VDDO3 36 49 34 P VDDO4 43 — — P Output Clock Supply Voltage 0–7. Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTnb outputs. A 0.1 uF bypass capacitor should be placed very close to this pin. Leave VDDO pins of unused output drivers unconnected. An alternate option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption. A 0402 1 µF capacitor should be placed very near each of these pins. VDDO5 49 — — P VDDO6 52 — — P VDDO7 57 — — P GND PAD — — — P NC Power VDD VDDA Ground Pad. This pad provides connection to ground and must be connected for proper operation. Use as many vias as practical and keep the via length to an internal ground plan as short as possible. Notes: 1. Refer to the Si5347-46 Rev D Reference Manual for more information on register setting names. 2. I = Input, O = Output, P = Power. 3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation. 4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation. 5. All status pins except I2C and SPI are push-pull. 48 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 48 Si5347/46 Rev D Data Sheet • Package Outlines 10. Package Outlines 10.1 Si5347 9x9 mm 64-QFN Package Diagram The figure below illustrates the package details for the Si5347. The table below lists the values for the dimensions shown in the illustration. Figure 10.1. 64-Pin Quad Flat No-Lead (QFN) Table 10.1. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 5.10 5.20 e 0.50 BSC E 9.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.15 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 49 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 49 Si5347/46 Rev D Data Sheet • Package Outlines 10.2 Si5346 7x7 mm 44-QFN Package Diagram The figure below illustrates the package details for the Si5346. The table below lists the values for the dimensions shown in the illustration. Figure 10.2. 44-Pin Quad Flat No-Lead (QFN) Table 10.2. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 7.00 BSC 5.10 5.20 e 0.50 BSC E 7.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa — — 0.15 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 50 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 50 Si5347/46 Rev D Data Sheet • PCB Land Pattern 11. PCB Land Pattern The figure below illustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in the illustration. Refer to the Si5347-46 Rev D Reference Manual for information about thermal via recommendations. Si5347 Si5346 Figure 11.1. PCB Land Pattern 51 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 51 Si5347/46 Rev D Data Sheet • PCB Land Pattern Table 11.1. PCB Land Pattern Dimensions Dimension Si5347 (Max) Si5346 (Max) C1 8.90 6.90 C2 8.90 6.90 E 0.50 0.50 X1 0.30 0.30 Y1 0.85 0.85 X2 5.30 5.30 Y2 5.30 5.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 52 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 52 Si5347/46 Rev D Data Sheet • Top Marking 12. Top Marking Si5347gRxxxxx-GM YYWWTTTTTT e4 TW Si5346gRxxxxx-GM YYWWTTTTTT TW e4 Figure 12.1. Si5347/46 Top Marking Table 12.1. Si5347/46 Top Marking Explanation Line Characters Description 1 Si5347g- Base part number and Device Grade. Si5346g- Si5347: Quad PLL; 64-QFN Si5346: Dual PLL; 44-QFN g = Device Grade. See Section 2. Ordering Guide for more information. – = Dash character. 2 Rxxxxx-GM R = Product revision. (See Section 2. Ordering Guide for current revision.) xxxxx = Customer specific NVM sequence number. (Optional NVM code assigned for custom, factory pre-programmed devices. Characters are not included for standard, factory default configured devices). See Section 2. Ordering Guide for more information. -GM = Package (QFN) and temperature range (–40 to +85 °C). 3 YYWWTTTTTT YYWW = Characters correspond to the year (YY) and work week (WW) of package assembly. TTTTTT = Manufacturing trace code. 4 53 Circle w/ 1.6 mm (64-QFN) or 1.4 mm (44-QFN) diameter Pin 1 indicator; left-justified e4 Pb-free symbol; Center-Justified TW TW = Taiwan; Country of Origin (ISO Abbreviation) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 53 Si5347/46 Rev D Data Sheet • Device Errata 13. Device Errata Log in or register at www.silabs.com to access the device errata document. 54 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 54 Si5347/46 Rev D Data Sheet • Revision History 14. Revision History Revision 1.1 September, 2018 • Updated Figure 3.3 Crystal Resonator and External Reference Clock Connection Options on page 9. • Updated Figure 3.5 Termination of Differential and LVCMOS Input Signals on page 11. • Updated Figure 3.15 Supported Differential Output Terminations on page 19. • Updated . • Updated Note 4 and LVCMOS Output Test Configuration circuit. • Updated Table 5.3 Input Clock Specifications on page 27. • Updated . • Updated Input Capacitance values. • Updated Output-to-Output Skew specification in Table 5.5 Differential Clock Output Specifications on page 29. • Removed Output-to-Output Skew specification in Table 5.6 LVCMOS Clock Output Specifications on page 30. • Updated LVCMOS Output Test Configuration under Note 3. • Removed Input-to-Output Delay Variation specification in Table 5.8 Performance Characteristics on page 32. • Updated Note 2 and Removed Note 6. Revision 1.0 July, 2016 • Initial release. 55 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021 55 ClockBuilder Pro Customize Skyworks clock generators, jitter attenuators and network synchronizers with a single tool. With CBPro you can control evaluation boards, access documentation, request a custom part number, export for in-system programming and more! www.skyworksinc.com/CBPro Portfolio SW/HW Quality Support & Resources www.skyworksinc.com/ia/timing www.skyworksinc.com/CBPro www.skyworksinc.com/quality www.skyworksinc.com/support Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes. No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale. THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters. Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com, are incorporated by reference. Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |