SI5348B-D08231-GMR

Si5348 Rev D Data Sheet Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-TSC) Clocks The Si5348 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization. The three independent DSPLLs™ are individually configurable as a SyncE PLL, IEEE 1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digitally controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588 (PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/ OCXO reference input to determine the device’s frequency accuracy and stability. The Si5348 is programmable via a serial interface with in-circuit programmable non-volatile memory so it always powers up into a known configuration. Programming the Si5348 is easy with ClockBuilder Pro™ software. Factory pre-programmed devices are also available. Applications: • Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2 • Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2 • IEEE 1588 (PTP) slave clock synchronization • Stratum 3/3E, G.812, G.813 network synchronization 48-54 MHz XTAL • Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/ IEEE 1588 and SETS architectures • Ultra-low jitter of 100 fs • Input frequency range: • External crystal: 48 to 54 MHz • REF clock: 5 to 250 MHz • Diff clock: 8 kHz to 750 MHz • LVCMOS clock: 8 kHz to 250 MHz • Output frequency range: • Differential: 1 PPS to 718.5 MHz • LVCMOS: 1 PPS to 250 MHz • Meets the requirements of: • ITU-T G.8262 (SyncE) EEC Options 1 & 2 • ITU-T G.812 Type III, IV • ITU-T G.813 Option 1 • Telcordia GR-1244, GR-253 (Stratum-3/3E) TCXO/OCXO REFb XA KEY FEATURES REF XB OSC IN3 IN4 DSPLL D IN0 ÷FRAC IN1 ÷FRAC IN2 DSPLL C ÷FRAC DSPLL A Status Flags I2C / SPI ÷INT OUT0 ÷INT OUT1 ÷INT OUT2 ÷INT OUT3 ÷INT OUT4 ÷INT OUT5 ÷INT OUT6 Status Monitor Control silabs.com | Building a more connected world. NVM Si5348 Rev. 1.1 Si5348 Rev D Data Sheet Feature List 1. Feature List The Si5348 features are listed below: • Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures • Ultra-Low Jitter • 100 fs typ (12 kHz to 20 MHz) • Meets the requirements of: • ITU-T G.8273.2 T-BC • ITU-T G.8262 (SyncE) EEC Options 1 & 2 • ITU-T G.812 Type III, IV • ITU-T G.813 Option 1 • Telcordia GR-1244, GR-253 (Stratum-3/3E) • Each DSPLL generates any output frequency from any input frequency • Input frequency range: • External crystal: 48-54 MHz • REF clock: 5-250 MHz • Diff clock: 8 kHz-750 MHz • LVCMOS clock: 8 kHz-250 MHz • Output frequency range: • Differential: 1 PPS to 718.5 MHz • LVCMOS: 1 PPS to 250 MHz silabs.com | Building a more connected world. • Pin or software controllable DCO on each DSPLL with typical resolution to 1 ppt/step • TCXO/OCXO reference input determines DSPLL free-run/holdover accuracy and stability • Programmable jitter attenuation bandwidth per DSPLL: 0.001 Hz to 4 kHz • Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML • Core voltage: • VDD: 1.8 V ±5% • VDDA: 3.3 V ±5% • Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V • Built-in power supply filtering • Status monitoring: LOS, OOF, LOL • Serial Interface: I2C or SPI (3-wire or 4-wire) • ClockBuilderTM Pro software tool simplifies device configuration • 5 input, 7 output, 64 QFN • Temperature range: –40 to +85 °C • Pb-free, RoHS-6 compliant Rev. 1.1 | 2 Si5348 Rev D Data Sheet Ordering Guide 2. Ordering Guide Table 2.1. Si5348 Ordering Guide Ordering Part Number Si5348A-D-GM 1, 2 Si5348B-D-GM 1, 2 # of DSPLLs 3 Output Clock Frequency Range 1 Hz to 718.5 MHz 1 Hz to 350 MHz Package RoHS-6, Pb-Free Temperature Range 64-Lead 9x9 QFN Yes –40 to 85 °C Si5348-D-EVB — — Evaluation Board — — SiOCXO1-EVB — 12.800 MHz OCXO Evaluation Board — — Note: 1. Add an R at the end of the device part number to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software. Part number format is: Si5348A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration. Si534fg-Rxxxxx-GM Timing product family f = Multi-PLL clock family member (7, 6) g = Device grade (A, B) Product Revision* Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (QFN, -40 °C to +85°C) *See Ordering Guide table for current product revision ** 5 digits; assigned by ClockBuilder Pro Figure 2.1. Ordering Part Number Fields silabs.com | Building a more connected world. Rev. 1.1 | 3 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 DSPLL Loop Bandwidth . 3.3.1 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 . 6 3.4 Modes of Operation . . 3.4.1 Initialization and Reset 3.4.2 Free-run Mode . . 3.4.3 Lock Acquisition Mode 3.4.4 Locked Mode . . . 3.4.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . . 3.5.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC) 3.5.2 Frequency Increment/Decrement Using the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 9 . 9 3.6 External Reference (XA/XB, REF/REFb) . 3.6.1 External Crystal (XA/XB) . . . . . 3.6.2 External Reference (REF/REFb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .11 .12 3.7 Inputs (IN0, IN1, IN2, IN3, IN4) . . . . 3.7.1 Input Selection . . . . . . . . 3.7.2 Manual Input Selection . . . . . . 3.7.3 Automatic Input Selection . . . . . 3.7.4 Input Configuration and Terminations . 3.7.5 Hitless Input Switching . . . . . . 3.7.6 Ramped Input Switching . . . . . 3.7.7 Glitchless Input Switching . . . . . 3.7.8 Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .13 .13 .14 .15 .15 .15 .15 3.8 Fault Monitoring . . . . 3.8.1 Input LOS Detection. . 3.8.2 XA/XB LOS Detection . 3.8.3 OOF Detection . . . 3.8.4 Precision OOF Monitor . 3.8.5 Fast OOF Monitor . . 3.8.6 LOL Detection . . . . 3.8.7 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 .16 .17 .17 .17 .17 .18 .19 3.9 Outputs . . . . . . . . . . 3.9.1 Output Crosspoint . . . . . 3.9.2 Support For 1 Hz Output . . . 3.9.3 Differential Output Terminations . 3.9.4 LVCMOS Output Terminations . 3.9.5 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 .20 .21 .22 .23 .23 silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . 7 7 7 8 8 8 Rev. 1.1 | 4 3.9.6 Programmable Common Mode Voltage For Differential Outputs 3.9.7 LVCMOS Output Impedance Selection . . . . . . . . 3.9.8 LVCMOS Output Signal Swing . . . . . . . . . . . 3.9.9 LVCMOS Output Polarity . . . . . . . . . . . . . 3.9.10 Output Enable/Disable . . . . . . . . . . . . . 3.9.11 Output Disable During LOL . . . . . . . . . . . . 3.9.12 Output Disable During XAXB_LOS . . . . . . . . . 3.9.13 Output Driver State When Disabled . . . . . . . . . 3.9.14 Synchronous/Asynchronous Output Disable . . . . . . 3.9.15 Output Divider (R) Synchronization . . . . . . . . . 3.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 .23 .23 .23 .24 .24 .24 .25 .25 .25 . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.11 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.12 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . .25 3.13 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .25 3.14 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . .26 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 7. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8. Typical Operating Characteristics (Jitter and Phase Noise) 9. Pin Descriptions . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. PCB Land Pattern 12. Top Marking 44 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . silabs.com | Building a more connected world. 56 Rev. 1.1 | 5 Si5348 Rev D Data Sheet Functional Description 3. Functional Description The Si5348 offers three DSPLLs that have identical performance and flexibility which can be independently configured and controlled through the serial interface. Each of the DSPLLs support locked, free-run, and holdover modes of operation with an optional DCO mode for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The reference input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs (IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine. Two additional manually selected inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any of the DSPLLs using a flexible crosspoint connection. Output 6 is the only output that can be configured for a 1 Hz output to support 1 PPS. 3.1 Standards Compliance Each of the DSPLLs meet the requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia GR-1244 and GR-253 as shown in the compliance report. The DCO feature enables IEEE1588 (PTP) implementations in addition to hybrid SyncE + IEEE1588 (T-BC). 3.2 Frequency Configuration The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division (Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility. 3.3 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. Table 3.1. Loop Bandwidth Requirements for North America SONET (Telcordia) SDH (ITU-T) SyncE (ITU-T) Loop Bandwidth GR-253 Stratum 3E G.812 Type III — 0.001 Hz GR-253 Stratum 3 G.812 Type IV G.8262 EEC Option 2