S i 5 3 5 0 C -B
F ACTORY - P R O G R A M M A B L E A NY - F R E Q U E N C Y C M O S C L O C K
G EN ER ATOR + P L L
Features
https://www.skyworksinc.com/Products/Ti
ming/CMOS-Clock-Generators
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Loss of Lock Status (LOLB)
Supports static phase offset
Rise/fall time control
10-MSOP
Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 1.8V, 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption (25 mA
core, typ)
Available in three packages types:
10-MSOP: 3 outputs
16-QFN (3x3 mm): 4 output
20-QFN (4x4 mm): 8 output
PCIE Gen 1 compliant
Supports HCSL compatible swing
16-QFN
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
20-QFN
Description
The Si5350C generates free-running and/or synchronized clocks selectable on each
of its outputs. A dual PLL + high resolution MultiSynthTM fractional divider
architecture enables this user-definable custom timing device to generate any of the
specified output frequencies at any of its outputs. This allows the Si5350C to replace
a combination of crystals, crystal oscillators, and synchronized clocks (PLL). Custom
Si5350C configurations can be created using ClockBuilder Pro.
Ordering Information:
See page 22
Functional Block Diagram
Si5350C (20-QFN)
Si5350C (10-MSOP)
Si5350C (16-QFN)
VDDO
XA
XA
OSC
PLL
A
MultiSynth 0
CLK0
P0
OSC
PLL
A
XB
XB
PLL
B
CLKIN
Control
Logic
MultiSynth 1
MultiSynth 2
XA
CLK1
CLK2
CLKIN
P0
P1
P2
PLL
B
Control
Logic
OSC
VDDOA
CLK0
XB
R1
VDDOB
CLK1
CLKIN
R2
VDDOC
CLK2
R3
VDDOD
CLK3
MultiSynth
0
R0
MultiSynth
1
MultiSynth
2
MultiSynth
3
PLL
B
P2
P3
MultiSynth
0
VDDOA
MultiSynth
1
CLK1
Control
Logic
CLK0
MultiSynth
2
VDDOB
MultiSynth
3
CLK3
MultiSynth
4
P0
P1
PLL
A
MultiSynth
5
MultiSynth
6
MultiSynth
7
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
CLK2
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
Si5350C-B
1. Ordering Guide
Table 1. Complete Si5350/51 Clock Generator Family
Part Number
I2C or Pin Frequency Reference
Programmed?
Outputs
Data Sheet
Si5351A-B-GT
I2C
XTAL only
Blank
3
Si5351A/B/C-B
Si5351A-B-GM1
I2C
XTAL only
Blank
4
Si5351A/B/C-B
Si5351B-B-GM1
2
I C
XTAL and/or Voltage
Blank
4
Si5351A/B/C-B
Si5351C-B-GM1
I2C
XTAL and/or CLKIN
Blank
4
Si5351A/B/C-B
Si5351A-B-GM
I2C
XTAL only
Blank
8
Si5351A/B/C-B
Si5351B-B-GM
I2C
XTAL and/or Voltage
Blank
8
Si5351A/B/C-B
Si5351C-B-GM
I2C
XTAL and/or CLKIN
Blank
8
Si5351A/B/C-B
Si5351A-Bxxxxx-GT
I2C
XTAL only
Factory Preprogrammed
3
Si5351A/B/C-B
Si5351A-Bxxxxx-GM1
I2C
XTAL only
Factory Preprogrammed
4
Si5351A/B/C-B
Si5351B-Bxxxxx-GM1
I2C
XTAL and/or Voltage
Factory Preprogrammed
4
Si5351A/B/C-B
Si5351C-Bxxxxx-GM1
I2C
XTAL and/or CLKIN
Factory Preprogrammed
4
Si5351A/B/C-B
Si5351A-Bxxxxx-GM
I2C
XTAL only
Factory Preprogrammed
8
Si5351A/B/C-B
Si5351B-Bxxxxx-GM
I2C
XTAL and/or Voltage
Factory Preprogrammed
8
Si5351A/B/C-B
Si5351C-Bxxxxx-GM
I2C
XTAL and/or CLKIN
Factory Preprogrammed
8
Si5351A/B/C-B
Si5350A-Bxxxxx-GT
Pin
XTAL only
Factory Preprogrammed
3
Si5350A-B
Si5350A-Bxxxxx-GM1
Pin
XTAL only
Factory Preprogrammed
4
Si5350A-B
Si5350A-Bxxxxx-GM
Pin
XTAL only
Factory Preprogrammed
8
Si5350A-B
Si5350B-Bxxxxx-GT
Pin
XTAL and/or Voltage
Factory Preprogrammed
3
Si5350B-B
Si5350B-Bxxxxx-GM1
Pin
XTAL and/or Voltage
Factory Preprogrammed
4
Si5350B-B
Si5350B-Bxxxxx-GM
Pin
XTAL and/or Voltage
Factory Preprogrammed
8
Si5350B-B
Si5350C-Bxxxxx-GT
Pin
XTAL and/or CLKIN
Factory Preprogrammed
3
Si5350C-B
Si5350C-Bxxxxx-GM1
Pin
XTAL and/or CLKIN
Factory Preprogrammed
4
Si5350C-B
Si5350C-Bxxxxx-GM
Pin
XTAL and/or CLKIN
Factory Preprogrammed
8
Si5350C-B
2
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
2. Technical Support Resources
Table 2. Technical Support Resources
Resource
Si5350/51 Frequently Asked Questions
ClockBuilder Pro (CBPro) Software
Si535x Development Kits
URL
https://www.skyworksinc.com/en/Products/Timing
https://www.skyworksinc.com/en/Application-Pages/ClockbuilderPro-Software
https://www.skyworksinc.com/en/Products/Timing/EvaluationKits/si535x-b20qfn-evb-evaluation-kit
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
3
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
TABLE O F C ONTENTS
Section
Page
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2. Technical Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. Si5350C Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Configuring the Si5350C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. External Clock Input Pin (CLKIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4. Programmable Control Pins (P0–P3) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.5. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1. 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.2. 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.3. 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1. 20-Pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.2. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3. 16-Pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.4. Land Pattern: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.5. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.6. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
10.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.3. 16-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.5. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
3. Electrical Specifications
Table 3. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
TA
Core Supply Voltage
Output Buffer Voltage
Test Condition
VDD
VDDOx
Min
Typ
Max
Unit
–40
25
85
°C
1.71
1.8
1.89
V
2.25
2.5
2.75
V
3.0
3.3
3.60
V
1.71
1.8
1.89
V
2.25
2.5
2.75
V
3.0
3.3
3.60
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 4. DC Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Core Supply Current*
Output Buffer Supply
Current (Per Output)*
Input Current
Output Impedance
Symbol
Test Condition
Min
Typ
Max
Unit
Enabled 3 outputs
—
20
35
mA
Enabled 4 outputs
—
21
38
mA
Enabled 8 outputs
—
25
45
mA
Power Down (PDN = VDD)
—
—
50
µA
IDDOx
CL = 5 pF
—
2.2
5.6
IP1-P3
Pins P1, P2, P3
VP1-P3 < 3.6 V
—
—
10
µA
IP0
Pin P0
—
—
30
µA
ZOI
3.3 V VDDO, default high
drive.
—
50
—
IDD
mA
*Note: Output clocks less than or equal to 100 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
5
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 5. AC Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Power-Up Time
TRDY
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
2
10
ms
Powerup Time, PLL Bypass
Mode
TBYP
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
0.5
1
ms
Output Enable Time
TOE
From OEB assertion to valid
clock output, CL = 5 pF, fCLKn
> 1 MHz
—
—
10
µs
TFREQ
fCLKn > 1 MHz
—
—
10
µs
Down spread.
Selectable in 0.1% steps.
–0.1
—
–2.5
%
Center spread.
Selectable in 0.1% steps.
±0.1
—
±1.5
%
30
31.5
33
kHz
Output Frequency Transition
Time
Spread Spectrum Frequency
Deviation
SSDEV
Spread Spectrum
Modulation Rate
SSMOD_C
Table 6. Input Characteristics
(VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Min
Typ
Max
Units
fXTAL
25
—
27
MHz
P0-P3 Input Low Voltage
VIL_P0-3
–0.1
—
0.3 x VDD
V
P0-P3 Input High Voltage
VIH_P0-3
VDD = 2.5 V or 3.3 V
0.7 x VDD
—
3.60
V
VDD = 1.8 V
0.8 x VDD
—
3.60
V
CLKIN Frequency Range
fCLKIN
10
—
100
MHz
CLKIN Input Low Voltage
VIL_CLKIN
–0.1
—
0.3 x VDD
V
CLKIN Input High Voltage
VIH_CLKIN
0.7 x VDD
—
3.60
V
Crystal Frequency
6
Symbol
Test Condition
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 7. Output Characteristics
VDD = 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Frequency Range
Symbol
1
Test Condition
Min
Typ
Max
Units
0.0025
—
200
MHz
FCLK < 100 MHz
—
—
15
pF
FCLK < 160 MHz, Measured
at VDD/2
45
50
55
%
FCLK > 160 MHz, Measured
at VDD/2
40
50
60
%
20%–80%, CL = 5 pF
—
1
1.5
ns
VDD – 0.6
—
—
V
—
—
0.6
V
16, 20-QFN, 4 outputs running, 1 per VDDO
-
40
95
ps, pk-pk
10-MSOP or 20-QFN, all
outputs running
-
70
155
ps, pk-pk
16, 20-QFN, 4 outputs running, 1 per VDDO
—
50
90
ps, pk
10-MSOP or 20-QFN, all
outputs running
—
70
150
ps, pk
FCLK
Load Capacitance
CL
Duty Cycle
DC
Rise/Fall Time
tr/tf
Output High Voltage
VOH
Output Low Voltage
VOL
Period Jitter2,3
JPER
Cycle-to-cycle Jitter
2,3
JCC
CL = 5 pF
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10k cycles. Jitter is only specified at the default high drive strength (50 output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,
24.576, 22.5792, 28.322, 125, and 48 MHz. Four-output, 16-QFN package measured with clock outputs of 33.333, 27,
28.322, and 48 MHz.
Table 8. 25 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
25
—
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150
dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10
pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF capacitors on XA and XB).
ClockBuilder Pro can be used to configure the internal load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
7
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 9. 27 MHz Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
—
27
—
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150
dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10
pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF capacitors on XA and XB).
ClockBuilder Pro can be used to configure the internal load capacitors.
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 10. Thermal Characteristics (2-Layer Board)
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Board
Thermal Resistance
Junction to Top Center
Symbol
JA
ΨJB
ΨJT
Test Condition
Still Air1
Still Air1
Still Air1
Package
Value
Unit
10-MSOP
150
°C/W
16-QFN
103
°C/W
20-QFN
74.9
°C/W
10-MSOP
82
°C/W
16-QFN
37
°C/W
20-QFN
9.94
°C/W
10-MSOP
0.84
°C/W
16-QFN
4.26
°C/W
20-QFN
1.3
°C/W
Notes:
1. Based on environment and board designed per JESD51-2A and JESD51-3.
8
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 11. Thermal Characteristics (4-Layer Board)
Parameter
Thermal Resistance
Junction to Ambient
Symbol
JA
JB
Test Condition
Still Air1
Junction to Board2
Thermal Resistance
Junction to Board
ΨJB
Thermal Resistance
Junction to Top Center
ΨJT
Still Air1
Still Air1
Package
Value
Unit
10-MSOP
126
°C/W
16-QFN
65
°C/W
20-QFN
41
°C/W
10-MSOP
84
°C/W
16-QFN
48
°C/W
20-QFN
16
°C/W
10-MSOP
83
°C/W
16-QFN
31
°C/W
20-QFN
8.1
°C/W
10-MSOP
0.74
°C/W
16-QFN
3.8
°C/W
20-QFN
0.98
°C/W
Package
Value
Unit
10-MSOP
36
°C/W
16-QFN
82
°C/W
20-QFN
51
°C/W
Notes:
1. Based on environment and board designed per JESD51-2A, JESD51-5, and JESD51-7.
2. Based on conditions set in JESD51-8.
Table 12. Thermal Characteristics (Junction-to-Case)
Parameter
Thermal Resistance
Junction to Case1
Symbol
JC
Test Condition
Still Air
Notes:
1. Based on board designed per JESD51-1 (Top center of packages used).
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
9
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 13. Absolute Maximum Ratings1
Parameter
DC Supply Voltage
Input Voltage
Symbol
Test Condition
VDD_max
Value
Unit
–0.5 to 3.8
V
VIN_CLKIN
CLKIN
–0.5 to 3.8
V
VIN_P1-3
Pins P1, P2, P3
–0.5 to 3.8
V
VIN_P0
P0
–0.5 to (VDD + 0.3)
V
VIN_XA/B
Pins XA, XB
–0.5 to 1.3 V
V
Junction Temperature
TJ
–55 to 150
°C
Soldering Temperature
(Pb-free profile)2
TPEAK
260
°C
TP
20–40
Sec
Soldering Temperature Time at
TPEAK (Pb-free profile)2
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
10
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
4. Typical Application
4.1. Si5350C Replaces Multiple Clocks and XOs
The Si5350C is a clock generation device that provides both synchronous and free-running clocks for applications
where power, board size, and cost are critical. An example application is shown in Figure 1. Any other combination
is possible.
Free-running
Clocks
XA
27 MHz
OSC
XB
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
CLKIN
PLL
54 MHz
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Si5350C
CLK0
125 MHz
CLK1
48 MHz
CLK2
28.322 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
CLK3
74.25 MHz
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Video/Audio
Processor
Synchronous
Clocks
Figure 1. Replacing multiple XTAL/XOs and PLLs with one Si5350C
4.2. Applying a Reference Clock at XTAL Input
The Si5350C can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clock outputs in two synchronization domains; one reference clock can be provided at the CLKIN pin
and at XA.
VIN = 1 VPP
25/27 MHz
XA
0.1 µF
XB
PLLA
Multi
Synth
0
Multi
Synth
1
OSC
PLLB
Note: Float the XB input while driving
the XA input with a clock
Multi
Synth
N
Figure 2. Si5350C Driven by a Clock Signal
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
11
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
4.3. HCSL Compatible Outputs
The Si5350C can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. This functionality is only supported for the Si5350C in 10MSOP or 20-QFN packages.
PLLA
Multi
Synth
0
ZO = 50
0
R1
511
240
OSC
PLLB
Multi
Synth
1
ZO = 50
0
HCSL
CLKIN
R1
511
240
Multi
Synth
N
R2
R2
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 3. Si5350C Output is HCSL Compatible
12
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
5. Functional Description
The architecture of the Si5350C generates up to eight non-integer-related frequencies in any combination of freerunning and/or synchronous clocks. A block diagram of the 3-, 4-, and 8-output versions shown in Figure 4. Freerunning clocks are generated using the on-chip oscillator + PLL, and the clock input pin (CLKIN) provides an
external input reference for the synchronous clocks. Each MultiSynthTM is configurable with two frequencies (F1_x,
F2_x). This allows a pin controlled glitchless frequency change at each output (CLK0 to CLK2).
10-MSOP
XA
OSC
XB
VDDO
VDD
MultiSynth 0
F1_0
PLL
A
F2_0
VDD
R0
MultiSynth 0
F1_0
FS
PLL
B
CLKIN
MultiSynth 1
F1_1
F2_1
R1
CLK1
MultiSynth 2
F1_2
Control
Logic
F2_2
XA
F2_0
OSC
XB
FS
P0
20-QFN
CLK0
R2
CLK2
PLL
A
PLL
PLL
vcxo
B
B
CLKIN
FS
MultiSynth 1
F1_1
F2_1
MultiSynth 2
F1_2
F2_2
MultiSynth 3
VDD
16-QFN
MultiSynth 0
F1_0
F2_0
OSC
MultiSynth 1
F1_1
PLL
B
CLKIN
F2_1
R0
R1
FS
P1
F1_2
R2
VDDOC
P0
VDDOB
P1
CLK1
P2
R4
MultiSynth 5
F1_5
CLK5
R5
Control
Logic
VDDOD
MultiSynth 6
F1_6
CLK4
R6
MultiSynth 7
CLK6
F1_7
CLK2
CLK7
R7
VDDOD
MultiSynth 3
F1_3
MultiSynth 4
CLK3
VDDOC
Control
Logic
P2
CLK0
P3
MultiSynth 2
P0
F1_4
CLK2
R3
MultiSynth 4
VDDOA
FS
PLL
A
VDDOB
R2
MultiSynth 3
F1_3
XB
CLK1
R1
FS
GND
CLK0
FS
FS
XA
VDDOA
R0
R3
GND
CLK3
GND
Figure 4. Block Diagrams of 3-Output, 4-Output, and 8-Output Si5350C Devices
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
13
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
6. Configuring the Si5350C
The Si5350C is a factory-programmed custom clock generator that is user-definable with ClockBuilder Pro, which
provides a simple graphical interface that allows users to enter input and output frequencies along with other
custom features, as described in the following sections. All synthesis calculations are automatically performed by
ClockBuilder Pro to ensure an optimum configuration. A unique part number is assigned to each custom
configuration.
6.1. Crystal Inputs (XA, XB)
The Si5350C uses an optional fixed-frequency non-pullable standard AT-cut crystal as a reference to generate
free-running output clocks. Note that a XTAL is not required for generating synchronous clocks that are locked to
CLKIN.
6.1.1. Crystal Frequency
The Si5350C can operate using either a 25 MHz or a 27 MHz crystal.
6.1.2. Internal XTAL Load Capacitors
Internal load capacitors are provided to eliminate the need for external components when connecting a XTAL to the
Si5350C. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8 or 10 pF. XTALs with alternate
load capacitance requirements are supported using additional external load capacitance 2 pF (e.g., by using 4
pF capacitors on XA and XB) as shown in Figure 5.
XA
XB
Optional additional
external load
capacitance
(< 2 pF)
Optional internal
load capacitance
0, 6, 8,10 pF
Figure 5. External XTAL with Optional Load Capacitors
6.2. External Clock Input Pin (CLKIN)
The external clock input is used as a reference for generating synchronous clocks. The input frequency can be
specified from 10 to 100 MHz including fractional frequencies (e.g., 74.25 MHz x 1000/1001). The ClockBuilder
utility automatically determines the exact synthesis ratio to guarantee an output frequency with 0 ppm error with
respect to its reference.
6.3. Output Clocks (CLK0–CLK7)
The Si5350C is orderable as a 3-output (10-MSOP), 4-output (16-QFN), or 8-output (20-QFN) clock generator.
Output clocks CLK0 to CLK2 can be ordered with two clock frequencies (F1_x, F2_x) which are selectable with the
optional frequency select pins (FS0/1). See “6.4.3. Frequency Select (FS_0, FS_1)” for more details on the
operation of the frequency select pins. Each output clock can select its reference for either of the PLLs.
6.3.1. Output Clock Frequency
Outputs can be configured at any frequency from 2.5 kHz up to 200 MHz. However, only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
14
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
6.3.2. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB.
The Si5350C supports several levels of spread spectrum allowing the designer to choose an ideal compromise
between system performance and EMI compliance. If the CLKIN pin already has spread spectrum applied to it, it
will get passed through to the outputs that are referenced to it. In this case, do not configure the synchronous
outputs for spread spectrum as the device will erroneously try to add additional spread to them.
An optional spread spectrum enable pin (SSEN) is configurable to enable or disable the spread spectrum feature.
See “6.4.1. Spread Spectrum Enable (SSEN)” for details.
Reduced
Amplitude
and EMI
Reduced
Amplitude
and EMI
Center
Frequency
Amplitude
fc
fc
fc
No Spread
Spectrum
Center Spread
Down Spread
Figure 6. Available Spread Spectrum Profiles
6.3.3. Invert/Non-Invert
By default, each of the output clocks are generated in phase (non-inverted) with respect to each other. An option to
invert any of the clock outputs is also available.
6.3.4. Output State When Disabled
There are up to three output enable pins configurable on the Si5350C as described in “6.4.4. Output Enable
(OEB_0, OEB_1, OEB_2)” . The output state when disabled for each of the outputs is configurable as output high,
output low, or high-impedance.
6.3.5. Powering Down Unused Outputs
Unused clock outputs can be completely powered down to conserve power.
6.4. Programmable Control Pins (P0–P3) Options
Up to four programmable control pins (P0-P3) are configurable allowing direct pin control of the following features:
6.4.1. Spread Spectrum Enable (SSEN)
An optional control pin allows disabling the spread spectrum feature for all outputs that were configured with
spread spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient
method of evaluating the effect of using spread spectrum clocks during EMI compliance testing.
6.4.2. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350C to minimize power consumption when its
output clocks are not being used. The Si5350C is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 4 on
page 5.
6.4.3. Frequency Select (FS_0, FS_1)
The Si5350C offers the option of configuring up to two frequencies per clock output (CLK0–CLK2) for either freerunning or synchronous clocks. This is a useful feature for applications that need to support more than one freerunning or synchronous clock rate on the same output. An example of this is shown in Figure 7. The FS pins select
which frequency is generated from the clock output. In this example, FS0 selects the output frequency on CLK0
and FS1 selects the frequency on CLK1.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
15
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
27 MHz
FS0
Bit Level
F1_0:
74.25 MHz
1
F2_0:
74.25
MHz
1.001
FS1
Bit Level
XA
Free-running Frequency
0
FS0
FS1
Synchronous Frequency
0
F1_1:
24.576 MHz
1
F2_1:
22.5792 MHz
XB
CLK0
Si5350C
Synchronous Clock
CLK1
54MHz
Free-running Clock
74.25
MHz
1.001
74.25 MHz or
24.576 MHz or 22.5792 MHz
Video/Audio
Processor
CLKIN
Figure 7. Example of Generating Two Clock Frequencies from the Same Clock Output
Up to two frequency select pins are available on the Si5350C. Each of the frequency select pins can be linked to
CLK0, 1, and 2 for 20-QFN and 10-MSOP devices. 16-QFN devices allow frequency select on CLK0 and CLK1.
See Figure 8 for an example of a potential 20-QFN frequency select configuration. In this example, FS_0 is linked
to control clock frequency selection on CLK0; FS_1 can be used to control clock frequency selection on CLK1 and
CLK2. Any other combination is also possible. The frequency select feature is not available for CLK3/4/5/6/7 in 20QFN devices or for CLK2/3 in 16-QFN devices.
The Si5350C uses control circuitry to ensure that frequency changes are glitchless. This ensures that the clock
always completes its last cycle before starting a new clock cycle of a different frequency.
Customizable FS Control
FS
FS
FS_0 Output Frequency
0
F1_0
1
F2_0
FS_0
FS
Glitchless Frequency Changes
MultiSynth 0
CLK0
MultiSynth 1
CLK1
MultiSynth 2
CLK2
New frequency starts
at its leading edge
Frequency _A
CLK3
FS_1 Output Frequency
0
F1_1, F1_2
1
F2_1, F2_2
CLK4
FS_1
Cannot be controlled
by FS pins
Frequency _B
Frequency_A
CLKx
CLK5
CLK6
Full cycle completes before
changing to a new frequency
CLK7
Figure 8. Example Configuration of a Pin-Controlled Frequency Select (FS)
16
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
6.4.4. Output Enable (OEB_0, OEB_1, OEB_2)
Up to three output enable pins (OEB_0/1/2) are available on the Si5350C. Each OEB pin can be linked to any of
the output clocks. In the example shown in Figure 9, OEB_0 is linked to control CLK0, CLK3, and CLK5; OEB_1 is
linked to control CLK6 and CLK7, and OEB_2 is linked to control CLK1, CLK2, CLK4, and CLK5. Any other
combination is also possible. If more than one OEB pin is linked to the same CLK output, the pin forcing a disable
state will be dominant. Clock outputs are enabled when the OEB pin is held low.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is asserted (OEB = low). When OEB is released (OEB = high), the clock is allowed to complete its
full clock cycle before going into a disabled state. This is shown in Figure 9. When disabled, the output state is
configurable as disabled high, disabled low, or disabled in high-impedance.
Customizable OEB Control
Glitchless Output Enable
CLK0
OEB_0
0
1
Output State
CLK Enabled
CLK Disabled
OEB
OEB_0
CLK1
OEB
Clock starts on the
first leading edge
CLK2
OEB
OEB_1
0
1
Output State
CLK Enabled
CLK Disabled
Clock continues until
cycle is complete
CLK3
OEB_1
CLKx
OEB
CLK4
OEB
OEBx
CLK5
OEB
OEB_2
0
1
Output State
CLK Enabled
CLK Disabled
OEB_2
CLK6
OEB
CLK7
OEB
Figure 9. Example Configuration of a Pin-Controlled Output Enable
6.4.5. Loss Of Lock (LOLB)
A loss of lock pin (LOLB) is available to indicate the status of the synchronous clock outputs. The LOLB pin is set to
a high state when the synchronous clock outputs are locked to the clock input (CLKIN). This is the normal
operating state for the synchronous clocks. The LOLB pin will go low when the reference clock at the CLKIN input
is removed or if its frequency deviates by more than 2000 ppm from its defined center frequency. In this case, the
synchronous clocks will continue to free-run. An option to disable the synchronous output clocks during an LOLB
condition (LOLB pin = low) is available. This only affects the clock outputs that were designated as synchronous
clock outputs. An external pull up resistor (recommended 10 kohms) is needed on LOLB as it is an open-drain
signal, not a push-pull output.
6.5. Design Considerations
The Si5350C is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
6.5.1. Power Supply Decoupling/Filtering
The Si5350C has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 to 1.0 µF decoupling capacitor per power supply pin. This capacitor
should be mounted as close to the VDD and VDDO pins as possible without using vias.
6.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
17
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
6.5.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.5.4. External Crystal Load Capacitors
The Si5350C provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
6.5.5. Unused Pins
Unused control pins (P0–P3) should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "4.2. Applying a Reference Clock at XTAL Input" on page 11
when using XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left unconnected.
Unused VDDOx pins should be tied to VDD.
6.5.6. Trace Characteristics
The Si5350C features various output drive strength settings. It is recommended to configure the trace
characteristics as shown in Figure 10 when the default high output drive setting is used.
ZO = 50 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Figure 10. Recommended Trace Characteristics with Default Drive Strength Setting
18
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
7. Pin Descriptions
XA
1
XB
2
16 CLK6
17 CLK5
18 VDDOC
19 CLK4
20 VDD
7.1. 20-Pin QFN
GND
PAD
15
CLK7
14
VDDOD
13
CLK0
VDDOA
VDDOB 10
11
9
5
CLK2
P2
8
CLK1
CLK3
12
7
4
P3
P1
6
3
CLKIN
P0
Figure 11. Si5350C 20-QFN Top View
Table 14. Si5350C 20-QFN Pin Descriptions
Pin Name
Pin Number
Pin Type
Function
XA
1
I
Input pin for external XTAL.
XB
2
I
Input pin for external XTAL.
CLKIN
6
I
External reference clock input.
CLK0
13
O
Output Clock 0.
CLK1
12
O
Output Clock 1.
CLK2
9
O
Output Clock 2.
CLK3
8
O
Output Clock 3.
CLK4
19
O
Output Clock 4.
CLK5
17
O
Output Clock 5.
CLK6
16
O
Output Clock 6.
CLK7
15
O
Output Clock 7.
P0
3
I
User configurable pin 0. See Section 6.4.
P1
4
I
User configurable pin 1. See Section 6.4.
P2
5
I
User configurable pin 2. See Section 6.4.
P3
7
I
User configurable pin 3. See Section 6.4.
VDD
20
P
Core voltage supply pin. See Section 6.5.2.
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1. See Section 6.5.2.
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3. See Section 6.5.2.
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5. See Section 6.5.2.
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7. See Section 6.5.2.
GND
Center Pad
P
Ground.
Note: Pin Types: I = Input, O = Output, P = Power
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
19
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
13 CLK2
14 VDDOC
15 GND
16 VDD
7.2. 16-Pin QFN
XA 1
12 CLK3
XB 2
11 VDDOD
GND
PAD
P0 3
10 CLK0
5
6
7
8
CLKIN
CLK1
VDDOB
9 VDDOA
P2
P1 4
Figure 12. Si5350C 16-Pin QFN Top View
Table 15. Si5350C 16-QFN Pin Descriptions
Pin Name
Pin Number
Pin Type*
Function
XA
1
I
Input pin for external crystal.
XB
2
I
Input pin for external crystal.
P0
3
I
User configurable input P0. See Section 6.4.
P1
4
I
User configurable input P1. See Section 6.4.
P2
5
I
User configurable input P2. See Section 6.4.
CLKIN
6
I
External reference clock input.
CLK1
7
O
Output Clock 1.
VDDOB
8
P
Output voltage supply pin for CLK1. See Section 6.5.2.
VDDOA
9
P
Output voltage supply pin for CLK0. See Section 6.5.2.
CLK0
10
O
Output Clock 0.
VDDOD
11
P
Output voltage supply pin for CLK3. See Section 6.5.2.
CLK3
12
O
Output Clock 3.
CLK2
13
O
Output Clock 2.
VDDOC
14
P
Output voltage supply pin for CLK2. See Section 6.5.2.
GND
15
GND
VDD
16
P
GND PAD
Center Pad
GND
Ground.
Core voltage supply pin. See Section 6.5.2.
Ground pad. Use multiple vias to ensure a solid path to Ground.
*Note: I = Input, O = Output, P = Power; GND = Ground. Input pins are not internally pulled up.
20
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
7.3. 10-Pin MSOP
VDD
1
10
CLK0
XA
2
9
CLK1
XB
3
8
GND
P0
4
7
VDDO
CLKIN
5
6
CLK2
Figure 13. Si5350C 10-MSOP Top View
Table 16. Si5350C 10-MSOP Pin Descriptions
Pin Name Pin Number Pin Type
Function
XA
2
I
Input pin for external XTAL.
XB
3
I
Input pin for external XTAL.
CLKIN
5
I
External reference clock input.
CLK0
10
O
Output clock 0.
CLK1
9
O
Output clock 1.
CLK2
6
O
Output clock 2.
P0
4
I
User configurable pin 0. See Section 6.4.
VDD
1
P
Core voltage supply pin. See Section 6.5.2.
VDDO
7
P
Output voltage supply pin for CLK0, CLK1, and CLK2. See Section 6.5.2.
GND
8
P
Ground.
Note: Pin Types: I = Input, O = Output, P = Power
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
21
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
8. Ordering Information
Factory programmed Si5350B devices can be requested through ClockBuilder Pro. A unique part number is
assigned to each custom configuration as indicated in Figure 14. Use ClockBuilder Pro to create custom part
numbers or consult a Skyworks Solutions sales representative for other custom NVM configurations.
The Si5351x-B20QFN-EVB evaluation kit, along with ClockBuilder Pro, enables easy testing of any Si5350B
frequency plan. ClockBuilder Pro makes it simple to emulate all three Si5350B packages, including the 10-MSOP,
20-QFN, and 16-QFN, on the same evaluation board.
Si5350C
BXXXXX
XXX
Blank = Coil Tape
R = Tape and Reel
GT = 10-MSOP
GM1 = 16-QFN
GM = 20-QFN
B
= Product Revision B
XXXXX = Unique Custom Code
. A five character code will be
as signed for each unique custom configuration
Evaluation Boards
Si535x-B20QFN-EVB
For evaluation of:
Si5350C-Bxxxxx-GM (20-QFN)
Si5350C-Bxxxxx-GM1 (16-QFN)
Si5350C-Bxxxxx-GT (10-MSOP)
Figure 14. Custom Clock Part Numbers
22
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9. Packaging
9.1. 20-Pin QFN Package Outline
Seating Plane
Figure 15 illustrates the package details for the Si5350C-B in a 20-pin QFN package. Table 17 lists the values for
the dimensions shown in the illustration.
C
D2
B
D
A
D2/2
A1
L
E
E2
E2/2
A
b
e
Figure 15. 20-pin QFN Package Drawing
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
23
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 17. Package Dimensions
Dimension
A
Min
0.80
Nom
0.85
Max
0.90
A1
0.00
—
0.05
b
D
D2
e
E
E2
L
0.20
0.30
2.65
0.35
0.25
4.00 BSC
2.70
0.50 BSC
4.00 BSC
2.70
0.40
2.75
0.45
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
2.65
2.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
24
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9.2. Land Pattern: 20-Pin QFN
Figure 16 shows the recommended land pattern details for the Si5350 in a 20-Pin QFN package. Table 18 lists the
values for the dimensions shown in the illustration.
Figure 16. 20-Pin QFN Land Pattern
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
25
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 18. PCB Land Pattern Dimensions
Symbol
Millimeters
C1
4.0
C2
4.0
E
0.50 BSC
X1
0.30
X2
2.70
Y1
0.80
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum,
all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with
trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all
perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be
used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD020 specification for Small Body components.
26
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9.3. 16-Pin QFN Package Outline
Figure 17 illustrates the package details for the Si5350C-B in a 16-QFN package. Table 19 lists the values for the
dimensions shown in the illustration.
Figure 17. 16-Pin QFN Package Drawing
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
27
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 19. Package Dimensions
Dimension
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
A3
b
0.20 REF.
0.18
D
D2
0.25
0.30
3.0 BSC
1.70
1.80
e
0.50 BSC
E
3.0 BSC
1.90
E2
1.70
1.80
1.90
L
0.25
0.35
0.45
K
0.20
—
—
R
0.09
—
0.14
aaa
0.15
bbb
0.10
ccc
0.10
ddd
0.05
eee
0.08
fff
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
28
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9.4. Land Pattern: 16-Pin QFN
Figure 18 shows the recommended land pattern details for the Si5350 in a 16-QFN package. Table 20 lists the
values for the dimensions shown in the illustration.
Figure 18. 16-Pin QFN Land Pattern
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
29
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 20. PCB Land Pattern Dimensions
Symbol
Millimeters
C1
3.00
C2
3.00
E
0.50
X1
0.30
Y1
0.75
X2
1.80
Y2
1.80
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This land pattern design is based on IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the
center ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body components.
11. The above notes and stencil design are shared as recommendations only. A
customer or user may find it necessary to use different parameters and fine-tune
their SMT process as required for their application and tooling.
30
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9.5. 10-Pin MSOP Package Outline
Figure 19 illustrates the package details for the Si5350C-B in a 10-pin MSOP package. Table 21 lists the values for
the dimensions shown in the illustration.
Figure 19. 10-pin MSOP Package Drawing
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
31
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 21. 10-MSOP Package Dimensions
Dimension
A
A1
A2
b
c
D
E
E1
e
L
L2
q
aaa
bbb
ccc
ddd
Min
—
0.00
0.75
0.17
0.08
0.40
0
—
—
—
—
Nom
—
—
0.85
—
—
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.25 BSC
—
—
—
—
—
Max
1.10
0.15
0.95
0.33
0.23
0.80
8
0.20
0.25
0.10
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
32
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
9.6. Land Pattern: 10-Pin MSOP
Figure 20 shows the recommended land pattern details for the Si5350C-B in a 10-Pin MSOP package. Table 22
lists the values for the dimensions shown in the illustration.
Figure 20. 10-Pin MSOP Land Pattern
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
33
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Table 22. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
Max
C1
4.40 REF
E
0.50 BSC
G1
3.00
—
X1
—
0.30
Y1
Z1
1.40 REF
—
5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body components.
34
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
10. Top Marking
10.1. 20-Pin QFN Top Marking
Figure 21. 20-Pin QFN Top Marking
10.2. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5350
Line 2 Mark Format:
TTTTTT = Mfg Code*
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
35
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
10.3. 16-Pin QFN Top Marking
Figure 22. 16-Pin QFN Top Marking
10.4. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Circle (Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
5350
Line 2 Mark Format:
TTTT = Mfg Code*
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last digit of the current year.
WW = Work week of the assembly date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
36
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
10.5. 10-Pin MSOP Top Marking
Figure 23. 10-Pin MSOP Top Marking
10.6. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Mold Dimple (Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
5350
Line 2 Mark Format:
TTTT = Mfg Code*
Line 2 from the “Markings” section of the Assembly
Purchase Order form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
37
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
REVISION HISTORY
Revision 1.2
March, 2020
Added "1. Ordering Guide" on page 2.
Updated "3. Electrical Specifications" on page 5.
Updated Tables 5, 7, 12, and 13 to include 16-QFN parameters.
Updated thermal characteristics tables to include Table 10 (2-Layer Board), Table 11 (4-Layer Board), and
Table 12 (Junction-to-Case).
Updated "4. Typical Application" on page 11.
Updated "4.3. HCSL Compatible Outputs" on page 12.
Updated "5. Functional Description" on page 13.
Updated "6. Configuring the Si5350C" on page 14.
Updated "6.3. Output Clocks (CLK0–CLK7)" on page 14.
Updated "6.4.3. Frequency Select (FS_0, FS_1)" on page 15.
Updated "6.5.5. Unused Pins" on page 18.
Updated "7. Pin Descriptions" on page 19.
Added 16-QFN information.
Updated "8. Ordering Information" on page 22.
Updated EVB and 16-QFN information.
Updated "9. Packaging" on page 23.
Added 16-QFN information.
Revision 1.1
August, 2018
Updated "8. Ordering Information" on page 22.
Changed “Blank = Bulk” to “Blank = Coil Tape” in Figure 14.
Revision 1.0
April, 2015
Extended frequency range from 8 MHz-160 MHz to 2.5 kHz-200 MHz.
Added 1.8V VDD support.
Updated block diagrams for clarity.
Added complete Si5350/51 family table, Table 1.
Added top mark information.
Added landing pattern drawings.
Added PowerUp Time, PLL Bypass, Table 5.
Clarified Down Spread step sizes in Table 5.
Updated max jitter specs (typ unchanged) in Table 7.
Clarified power supply sequencing requirement, Section 6.5.2.
Updated 4.4.5 Loss of Lock (LOLB) section.
Revision 0.76
October, 2013
Updated Table 5 on page 6.
Updated spread-spectrum frequency deviation parameter test condition and minimum spec value.
Updated “8. Ordering Information” .
Updated Figure 14, “Custom Clock Part Numbers,” on page 22.
38
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
Si5350C-B
Revision 0.75
October, 2012
Initial release.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
39
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 22, 2021
ClockBuilder Pro
Customize Skyworks clock generators,
jitter attenuators and network
synchronizers with a single tool. With
CBPro you can control evaluation
boards, access documentation, request
a custom part number, export for
in-system programming and more!
www.skyworksinc.com/CBPro
Portfolio
SW/HW
Quality
Support & Resources
www.skyworksinc.com/ia/timing
www.skyworksinc.com/CBPro
www.skyworksinc.com/quality
www.skyworksinc.com/support
Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the
information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer.
Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation,
products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or
information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability
for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or
materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.
THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR
OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY
INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR
COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR
ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT
LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT
OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks
products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such
applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.
Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of
design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating
safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any
equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.
Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or
registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for
identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at
www.skyworksinc.com, are incorporated by reference.
Skyworks Solutions, Inc. | Nasdaq: SWKS | sales@skyworksinc.com | www.skyworksinc.com
USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540 |
工商网监
湘ICP备2023018690号
