SI5366-C-GQ

Si5366 P RECISION C L O C K M ULTIPLIER / J I T T E R A TTENUATOR Features       Selectable output frequencies  ranging from 8 kHz to 1050 MHz Ultra-low jitter clock outputs  w/jitter generation as low as 0.3 ps rms (12 kHz–20 MHz)  Integrated loop filter with  selectable loop bandwidth (60 Hz to 8.4 kHz)  Meets OC-192 GR-253-CORE  jitter specifications Four clock inputs w/manual or automatically controlled hitless  switching Five clock outputs with selectable  signal format (LVPECL, LVDS, CML, CMOS) SONET frame sync switching and regeneration Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Pin-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS-compliant Ordering Information: See page 25. Applications SONET/SDH OC-48/STM-16  Optical modules and OC-192/STM-64 line cards  Test and measurement  GbE/10GbE, 1/2/4/8/10G Fibre  Synchronous Ethernet Channel line cards  ITU G.709 line cards  Description The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel frequencies. The Si5366 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides anyfrequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5366 Si5366 Functional Block Diagram Xtal or Refclock CKIN1 CKIN2 DSPLL CKIN3 ® ÷ NF1 CKOUT1 ÷ NF2 CKOUT2 ÷ NF3 CKOUT3 N1_HS CKIN4 Input Clock Configuration Divider Select Manual/Auto Switch Clock Select ÷ NF4 CKOUT4 ÷ NF5 CKOUT5 (FS_OUT) Resonator/Rate Select LOL/LOS/FOS Alarms Control Output Clock2 Frequency Select Bandwidth Select Input Clock3 VDD (1.8, 2.5, or 3.3 V) Skew Control Input Clock4 GND FSYNC Align 2 Rev. 1.0 Si5366 TABLE O F C ONTENTS Section Page 1. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Pin Descriptions: Si5366 (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. Package Outline: 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1. Si5366 Top Marking (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Rev. 1.0 3 Si5366 Table 1. Recommended Operating Conditions1 Parameter Symbol Ambient Temperature TA Supply Voltage during Normal Operation VDD Test Condition Min Typ Max Unit –40 25 85 C 3.3 V Nominal2 2.97 3.3 3.63 V 2.5 V Nominal 2.25 2.5 2.75 V 1.8 V Nominal 1.71 1.8 1.89 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated. 2. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. SIGNAL + Differential I/Os VICM , VOCM V VISE , VOSE SIGNAL – (SIGNAL +) – (SIGNAL –) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM Single-Ended Peak-to-Peak Voltage t SIGNAL + VID = (SIGNAL+) – (SIGNAL–) SIGNAL – Figure 1. Differential Voltage Characteristics 80% CKIN, CKOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics 4 Rev. 1.0 Si5366 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit IDD LVPECL Format 622.08 MHz Out All CKOUTs Enabled — 394 435 mA LVPECL Format 622.08 MHz Out 1 CKOUT Enabled — 253 284 mA CMOS Format 19.44 MHz Out All CKOUTs Enabled — 278 400 mA CMOS Format 19.44 MHz Out 1 CKOUT Enabled — 229 261 mA Disable Mode — 165 — mA 1.8 V ± 5% 0.9 — 1.4 V 2.5 V ± 10% 1 — 1.7 V 3.3 V ± 10% 1.1 — 1.95 V CKNRIN Single-ended 20 40 60 k Single-Ended Input Voltage Swing (See Absolute Specs) VISE fCKIN < 212.5 MHz See Figure 1. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 1. 0.25 — — VPP Differential Input Voltage Swing (See Absolute Specs) VID fCKIN < 212.5 MHz See Figure 1. 0.2 — — VPP fCKIN > 212.5 MHz See Figure 1. 0.25 — — VPP Supply Current1,6 CKINn Input Pins2 Input Common Mode Voltage (Input Threshold Voltage) Input Resistance VICM Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. Rev. 1.0 5 Si5366 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit CKOVCM LVPECL 100  load line-to-line VDD –1.42 — VDD –1.25 V Differential Output Swing CKOVD LVPECL 100  load line-to-line 1.1 — 1.9 VPP Single Ended Output Swing CKOVSE LVPECL 100  load line-to-line 0.5 — 0.93 VPP Differential Output Voltage CKOVD CML 100  load line-toline 350 425 500 mVPP CKOVCM CML 100  load line-toline — VDD-0.36 — V CKOVD LVDS 100  load line-to-line 500 700 900 mVPP Low Swing LVDS 100  load line-to-line 350 425 500 mVPP CKOVCM LVDS 100 load lineto-line 1.125 1.2 1.275 V CKORD CML, LVPECL, LVDS — 200 —  Output Voltage Low CKOVOLLH CMOS — — 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD — — V CKOIO VDD = 1.8 V — 7.5 — mA VDD = 3.3 V — 32 — mA Output Clocks (CKOUTn)3,5,6 Common Mode Common Mode Output Voltage Differential Output Voltage Common Mode Output Voltage Differential Output Resistance Output Drive Current (CMOS driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally) Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. 6 Rev. 1.0 Si5366 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit VDD = 1.71 V — — 0.5 V VDD = 2.25 V — — 0.7 V VDD = 2.97 V — — 0.8 V VDD = 1.89 V 1.4 — — V VDD = 2.25 V 1.8 — — V VDD = 3.63 V 2.5 — — V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIL VIH Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. Rev. 1.0 7 Si5366 Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 3-Level Input Pins4 Input Voltage Low VILL — — 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD — 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD — — V Input Low Current IILL See Note 4 –20 — — µA Input Mid Current IIMM See Note 4 –2 — +2 µA Input High Current IIHH See Note 4 — — 20 µA VOL IO = 2 mA VDD = 1.71 V — — 0.4 V IO = 2 mA VDD = 2.97 V — — 0.4 V IO = –2 mA VDD = 1.71 V VDD –0.4 — — V IO = –2 mA VDD = 2.97 V VDD –0.4 — — V LVCMOS Output Pins Output Voltage Low Output Voltage Low Output Voltage High Output Voltage High VOH Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. 6. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS. 8 Rev. 1.0 Si5366 Table 3. AC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XARIN RATE[1:0] = LM, MH, ac-coupled — 12 — k Input Voltage Swing XAVPP RATE[1:0] = LM, MH, ac-coupled 0.5 — 1.2 VPP 0.5 — 2.4 VPP Differential Reference Clock Input Pins (XA/XB) Input Voltage Swing XA/XBVPP RATE[1:0] = LM, MH CKINn Input Pins Input Frequency CKNF .008 — 707.35 MHz CKIN3 and CKIN4 used as FSYNC pins CKNF — 8 — kHz 40 — 60 % 2 — — ns — — 3 pF — — 11 ns Input Duty Cycle (Minimum Pulse Width) CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF Whichever is smaller (i.e., the 40% / 60% limitation applies only to high frequency clocks) 20–80% See Figure 2 CKOUTn Output Pins (See ordering section for speed grade vs frequency limits) Output Frequency (Output not configured for CMOS or Disabled) CKOF 0.008 — 1050 MHz Maximum Output Frequency in CMOS Format CKOF — — 212.5 MHz Output Rise/Fall (20–80 %) @ 622.08 MHz output CKOTRF Output not configured for CMOS or Disabled See Figure 2 — 230 350 ps Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 1.71 CLOAD = 5 pF — — 8 ns *Note: Input to output phase skew after an ICAL is not controlled and can assume any value. Rev. 1.0 9 Si5366 Table 3. AC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD = 2.97 CLOAD = 5 pF — — 2 ns Output Duty Cycle Uncertainty @ 622.08 MHz CKODC 100  Load Line-to-Line Measured at 50% Point (Not for CMOS) — — ±40 ps tRSTMN 1 — — µs Cin — — 3 pF LVCMOS Input Pins Minimum Reset Pulse Width Input Capacitance LVCMOS Output Pins Rise/Fall Times tRF CLOAD = 20 pF See Figure 2 — 25 — ns LOSn Trigger Window LOSTRIG From last CKINn to  Internal detection of LOSn — — 4.5 x N3 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Fold = Fnew Stable XA/XB reference — 10 — ms Output Clock Skew tSKEW  of CKOUTn to  of CKOUT_m, CKOUTn and CKOUT_m at same frequency — — 100 ps Phase Change due to Temperature Variation* tTEMP Max phase changes from –40 to +85 °C — 300 500 ps Device Skew *Note: Input to output phase skew after an ICAL is not controlled and can assume any value. 10 Rev. 1.0 Si5366 Table 3. AC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit PLL Performance (fin = fout = 622.08 MHz; BW = 120 Hz; LVPECL) Lock Time tLOCKMP Start of ICAL to of LOL — 35 1200 ms Output Clock Phase Change tP_STEP After clock switch f3  128 kHz — 200 — ps — 0.05 0.1 dB Closed Loop Jitter Peaking JPK Jitter Tolerance JTOL Jitter Frequency Loop Bandwidth 5000/BW — — ns pk-pk CKOPN 1 kHz Offset — –106 — dBc/Hz 10 kHz Offset — –121 — dBc/Hz 100 kHz Offset — –132 — dBc/Hz 1 MHz Offset — –131 — dBc/Hz Max spur @ n x F3 (n  1, n x F3 < 100 MHz) — –93 –70 dBc Phase Noise fout = 622.08 MHz Spurious Noise SPSPUR *Note: Input to output phase skew after an ICAL is not controlled and can assume any value. Rev. 1.0 11 Si5366 Table 4. Jitter Generation Parameter Jitter Gen OC-192 Symbol JGEN Test Condition* Measurement Filter DSPLL BW2 0.02–80 MHz 120 Hz 4–80 MHz 0.05–80 MHz Jitter Gen OC-48 JGEN 0.12–20 MHz Min Typ Max GR-253Specification Unit — 4.2 6.2 30 psPP — .27 .42 N/A psrms — 3.7 6.4 10 psPP — .14 .31 N/A psrms — 4.4 6.9 10 psPP — .26 .41 1.0 ps rms — 3.5 5.4 40.2 psPP — .27 .41 4.02 ps rms 120 Hz 120 Hz 120 Hz *Note: Test conditions: 1. fIN = fOUT = 622.08 MHz. 2. Clock input: LVPECL . 3. Clock output: LVPECL. 4. PLL bandwidth: 120 Hz. 5. 114.285 MHz 3rd OT crystal used as XA/XB input. 6. VDD = 2.5 V. 7. TA = 85 °C. 8. Jitter integration bands include low-pass (–20 dB/Dec) and high-pass (–60 dB/Dec) roll-offs per Telecordia GR-253CORE. Table 5. Thermal Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Thermal Resistance Junction to Ambient 12 Symbol Test Condition Value Unit JA Still Air 31 C°/W Rev. 1.0 Si5366 - Table 6. Absolute Maximum Ratings* Parameter Symbol Test Condition Min Typ Max Unit — 3.8 V VDD+0.3 V DC Supply Voltage VDD –0.5 LVCMOS Input Voltage VDIG –0.3 CKINn Voltage Level Limits CKNVIN 0 — VDD V XA/XB Voltage Level Limits XAVIN 0 — 1.2 V Operating Junction Temperature TJCT –55 — 150 ºC Storage Temperature Range TSTG –55 — 150 ºC 2 — — kV ESD MM Tolerance; All pins except CKIN+/CKIN– 150 — — V ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN– 700 — — V ESD MM Tolerance; CKIN+/CKIN– 100 — — V ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– Latch-up Tolerance JESD78 Compliant *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Rev. 1.0 13 Si5366 1. Typical Phase Noise Performance Figure 3. Typical Phase Noise Plot Table 7. RMS Jitter by Band Jitter Band RMS Jitter SONET_OC48, 12 kHz to 20 MHz 249 fs SONET_OC192_A, 20 kHz to 80 MHz 274 fs SONET_OC192_B, 4 MHz to 80 MHz 166 fs SONET_OC192_C, 50 kHz to 80 MHz 267 fs Brick Wall_800 Hz to 80 MHz 274 fs *Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs per Telcordia GR-253-CORE. 14 Rev. 1.0 Si5366 2. Typical Application Schematic C10 System Power Supply Ferrite Bead Option 2: Ext. Refclk– Ext. Refclk+ C1–9 VDD = 3.3 V 0.1 µF 0.1 µF CKIN1+ XA XB XA XB 130  GND 0.1 µF VDD 130  Option 1: 114.285 MHz Crystal 1 µF CKIN1– 82  82  CKOUT1+ 0.1 µF + 100  CKOUT1– Input Clock Sources1 0.1 µF – VDD = 3.3 V 130  130  CKIN4+ CKIN4– 82  CKOUT4+ CKOUT4– VDD CKOUT5/FS_OUT+ 15 k RATE2 CKOUT5/FS_OUT– CK_CONF VDD + 0.1 µF 0.1 µF – + 100  15 k Input Clock Configuration Control Clock Outputs 100  82  Crystal/Ref Clk Rate 0.1 µF 0.1 µF – 15 k Manual/Automatic Clock Selection (L) 15 k AUTOSEL2 Input Clock Select VDD CKSEL[1:0]3 Si5366 15 k Frequency Offset Control VDD 15 k Frequency Table Select VDD 15 k Frequency Select Bandwidth Select FOS_CTL2 15 k FRQTBL2 15 k VDD 15 k FRQSEL[3:0]2 15 k BWSEL[1:0]2 15 k Skew Increment INC Skew Decrement VDD DEC 15 k Signal Format Select VDD 15 k CKOUT3 and CKOUT4 Divider Control 15 k Clock Output 2 Disable/ Bypass Mode Control Clock Outputs 3 and 4 Disable SFOUT[1:0]2 15 k VDD DIV34_[1:0]2 15 k DBL2_BY2 15 k VDD DBL34 15 k FS_OUT Disable DBL_FS2 15 k FSYNC Inputs to Clock Selection Enable FS_SW FSYNC Realignment Control FS_ALIGN Reset RST ALRMOUT Alarm Output Indicator CKnB CKINn Invalid Indicator (n = 1 to 3) LOL PLL Loss of Lock Indicator Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection. Figure 4. Si5366 Typical Application Circuit Rev. 1.0 15 Si5366 3. Functional Description The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequencymultiplied clock outputs ranging from 8 kHz to 1050 MHz. By default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. Two of the output clocks can be divided down further to generate an integer sub-multiple frequency. Optionally, the fifth clock output can be configured as a 8 kHz SONET/SDH frame synchronization output that is phase aligned with one of the high-speed output clocks. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel frequencies. In addition to providing clock multiplication in SONET and datacom applications, the Si5366 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid Si5366 frequency translations. This utility can be downloaded from http://www.silabs.com/timing (click on Documentation). The Si5366 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyfrequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5366 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5366 supports hitless switching between input clocks in compliance with GR-253-CORE and GR-1244CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (