SI5366

Si5366 P R E L I M I N A R Y D A TA S H E E T PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Description The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequencymultiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5366 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Features Selectable output frequencies ranging from 8 kHz to 1050 MHz Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) SONET frame sync switching and regeneration Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Pin-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Optical modules Test and measurement Xtal or Refclock CKIN1 CKIN2 CKIN3 CKIN4 ÷ Input Clock Configuration Manual/Auto Switch Clock Select Resonator/Rate Select LOL/LOS/FOS Alarms Frequency Select Bandwidth Select Latency Control FSYNC Align Input Clock3 Input Clock4 VDD (1.8 or 2.5 V) GND Control Output Clock2 ÷ NFS CKOUT5 (FS_OUT) ÷ CKOUT3 Divider Select CKOUT1 DSPLL ® CKOUT2 CKOUT4 Preliminary Rev. 0.2 3/07 Copyright © 2007 by Silicon Laboratories Si5366 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5366 Table 1. Performance Specifications (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Supply Current Symbol TA VDD IDD Test Condition Min –40 2.25 1.62 Typ 25 2.5 1.8 394 Max 85 2.75 1.98 435 Unit ºC V V mA fOUT = 622.08 MHz All CKOUTs enabled LVPECL format output Only CKOUT1 enabled fOUT = 19.44 MHz All CKOUTs enabled CMOS format output Only CKOUT1 enabled Tristate/Sleep Mode — — — 253 278 284 321 mA mA — — 0.008 229 TBD — 261 TBD 707.35 mA mA MHz Input Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4) Input Clock Frequency (CKIN3, CKIN4 used as FSYNC inputs) Output Clock Frequency (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5 used as fifth high-speed output) CKOUT5 used as frame sync output (FS_OUT) Differential Voltage Swing Common Mode Voltage Rise/Fall Time Duty Cycle CKF CKF CKOF Input frequency and clock multiplication ratio pin-selectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing for table selections. 0.008 — — MHz 0.008 — 1049.76 MHz CKOF 0.008 — — MHz Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4) CKNDPP CKNVCM CKNTRF CKNDC 1.8 V ±10% 2.5 V ±10% 20–80% Whichever is less 40 50 Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT) Common Mode Differential Output Swing Single Ended Output Swing Rise/Fall Time VOCM VOD VSE CKOTRF LVPECL 100 Ω load line-to-line 20–80% VDD – 1.42 1.1 0.5 — — — — 230 VDD – 1.25 1.9 0.93 350 V V V ps 0.25 0.9 1.0 — — — — — — 1.9 1.4 1.7 11 60 — VPP V V ns % ns Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.2 S i5366 Table 1. Performance Specifications (Continued) (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Duty Cycle PLL Performance Jitter Generation Symbol CKODC JGEN Test Condition Min 45 Typ — 0.3 Max 55 TBD Unit % ps rms fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz — — — — — — — — — — 0.3 0.05 TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Jitter Transfer Phase Noise JPK CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH SPSPUR Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air θJA — 40 — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 2.75 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V ºC ºC kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.2 3 S i5366 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Preliminary Rev. 0.2 S i5366 Figure 2. Si5366 Typical Application Circuit Preliminary Rev. 0.2 5 S i5366 1. Functional Description The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to 707 MHz and generates five frequencymultiplied clock outputs ranging from 8 kHz to 1050 MHz. By default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. Two of the output clocks can be divided down further to generate an integer sub-multiple frequency. Optionally, the fifth clock output can be configured as a 8 kHz SONET/SDH frame synchronization output that is phase aligned with one of the high-speed output clocks. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5366 supports SONETto-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to look up valid Si5366 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5366 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5366 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5366 supports hitless switching between input clocks in compliance with GR-253-CORE and GR-1244CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (