SI5367

Si5367 P R E L I M I N A R Y D A TA S H E E T µP-P R O G R A M M A B L E P R E C I S I O N C L O C K M U L T I P L I E R Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5367 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5367 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. Features Generates any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 10 to 710 MHz Low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz) Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement CKIN1 CKIN2 CKIN3 CKIN4 ÷ N31 ÷ N32 ÷ N33 ÷ N34 ÷ N2 ÷ NC3 CKOUT3 ÷ NC1 CKOUT1 DSPLL ® ÷ NC2 CKOUT2 ÷ NC4 I C/SPI Port Clock Select Device Interrupt LOS Alarms Control ÷ NC5 2 CKOUT4 CKOUT5 VDD (1.8 or 2.5 V) GND Preliminary Rev. 0.3 3/07 Copyright © 2007 by Silicon Laboratories Si5367 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5367 Table 1. Performance Specifications (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Supply Current Symbol TA VDD IDD Test Condition Min –40 2.25 1.62 Typ 25 2.5 1.8 394 Max 85 2.75 1.98 435 Unit ºC V V mA fOUT = 622.08 MHz All CKOUTs enabled LVPECL format output Only CKOUT1 enabled fOUT = 19.44 MHz All CKOUTs enabled CMOS format output Only CKOUT1 enabled Tristate/Sleep Mode — — — 253 278 284 321 mA mA — — 10 229 TBD — 261 TBD 707.35 mA mA MHz Input Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4) Output Clock Frequency (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) CKF CKOF Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. 10 970 1213 — — — 945 1134 1417 MHz Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4) Differential Voltage Swing CKNDPP Common Mode Voltage Rise/Fall Time Duty Cycle CKNVCM CKNTRF CKNDC 1.8 V ±10% 2.5 V ±10% 20–80% Whichever is less 0.25 0.9 1.0 — 40 50 Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) Common Mode Differential Output Swing Single Ended Output Swing VOCM VOD VSE LVPECL 100 Ω load line-to-line VDD – 1.42 1.1 0.5 — — — VDD – 1.25 1.9 0.93 V V V — — — — — — 1.9 1.4 1.7 11 60 VPP V V ns % ns Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.3 S i5367 Table 1. Performance Specifications (Continued) (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Rise/Fall Time Duty Cycle PLL Performance Jitter Generation Symbol CKOTRF CKODC JGEN Test Condition 20–80% Min 45 Typ 230 — 0.6 Max 350 55 TBD Unit ps % ps rms fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz 800 Hz–80 MHz — — — — — — — — — — — 0.6 TBD 0.05 TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD ps rms ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Jitter Transfer Phase Noise JPK CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient SPSUBH Phase Noise @ 100 kHz Offset SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air θJA — 40 — ºC/W Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 2.75 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V ºC ºC kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.3 3 S i5367 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot 4 Preliminary Rev. 0.3 S i5367 System Power Supply VDD = 3.3 V C10 Ferrite Bead 1 µF C1–9 0.1 µF CKIN1+ CKIN1– 82 Ω 82 Ω CKOUT1– Input Clock Sources* GND VDD 130 Ω 130 Ω CKOUT1+ 0.1 µF 100 Ω 0.1 µF 0.1 µF 100 Ω + – Clock Outputs + VDD = 3.3 V CKOUT5+ 130 Ω 130 Ω CKIN4+ CKIN4– Si5367 CKOUT5– 0.1 µF – INT_ALM CnB Interrupt/Alarm Output Indicator CKINn Invalid Indicator (n = 1 to 3) Serial Port Address Serial Data Serial Clock I2C Interface 82 Ω 82 Ω A[2:0] Control Mode (L) Reset CMODE RST SDA SCL *Note: Assumes differential LVPECL termination (3.3 V) on clock inputs. Figure 2. Si5367 Typical Application Circuit (I2C Control Mode) C10 Ferrite Bead 1 µF C1–9 0.1 µF CKIN1+ CKIN1– 82 Ω 82 Ω GND VDD System Power Supply VDD = 3.3 V 130 Ω 130 Ω CKOUT1+ 0.1 µF 100 Ω + CKOUT1– 0.1 µF – Clock Outputs + Input Clock Sources* VDD = 3.3 V CKOUT5+ 0.1 µF 100 Ω 130 Ω 130 Ω CKIN4+ CKIN4– CKOUT5– Si5367 INT_ALM CnB 0.1 µF – Interrupt/Alarm Output Indicator CKIN_n Invalid Indicator (n = 1 to 3) 82 Ω 82 Ω SS SDO Control Mode Reset CMODE RST *Note: Assumes differential LVPECL termination (3.3 V) on clock inputs. SDI SCL Slave Select Serial Data Out Serial Data In Serial Clock SPI Interface Figure 3. Si5367 Typical Application Circuit (SPI Control Mode) Preliminary Rev. 0.3 5 S i5367 1. Functional Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for every input clock and output clock, so the Si5367 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5367 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from www.silabs.com/timing. The Si5367 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5367 PLL loop bandwidth is digitally programmable and supports a range from 30 kHz to 1.3 MHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5367 monitors all input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on its inputs. In the case when the input clocks enter alarm conditions, the PLL will freeze the DCO output frequency near its last value to maintain operation with an internal state close to the last valid operating state. The Si5367 has five differential clock outputs. The signal format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, unused clock outputs can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. In addition, the phase of each output clock may be adjusted in relation to the other output clocks. The resolution varies from 800 ps to 2.2 ns depending on the PLL divider settings. Consult the DSPLLsim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combination. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8 or 2.5 V supply. 1.1. Further Documentation Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5367. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing. 6 Preliminary Rev. 0.3 S i5367 2. Pin Descriptions: Si5367 VDD CKOUT4+ CKOUT2+ CKOUT5+ CKOUT1+ CKOUT3+ CKOUT4– CKOUT2– CKOUT5– VDD CKOUT1– CKOUT3– CMODE VDD VDD NC VDD VDD VDD VDD VDD VDD NC NC RST NC VDD VDD GND GND C1B C2B C3B INT_ALM CS0_C3A GND VDD GND NC GND GND NC GND NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 VDD NC NC NC NC NC NC SDI A2_SS A1 A0 NC NC GND GND VDD VDD SDA_SDO SCL C2A C1A CS1_C4A NC NC NC NC NC NC Si5367 GND PAD 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CKIN4– VDD CKIN4+ CKIN2+ CKIN3+ CKIN1+ CKIN3– CKIN1– GND GND GND GND GND GND GND CKIN2– GND VDD VDD NC NC NC NC NC GND Table 3. Si5367 Pin Descriptions Pin # 1, 2, 4, 17, 20, 22, 23, 24, 25, 37, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 66, 67, 72, 73, 74, 75, 80, 85, 95 3 Pin Name NC I/O Signal Level Description No Connect. These pins must be left unconnected for normal operation. RST I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are tristated during reset. After rising edge of RST signal, the device will perform an internal self-calibration. This pin has a weak pull-up. Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. Preliminary Rev. 0.3 7 S i5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # 5, 6, 15, 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 Pin Name VDD I/O Vdd Signal Level Supply Description VDD. The device operates from a 1.8 or 2.5 V supply. Bypass capacitors should be associated with the following VDD pins: Pins Bypass Cap 5, 6 0.1 µF 15 0.1 µF 27 0.1 µF 62, 63 0.1 µF 76, 79 1.0 µF 81, 84 0.1 µF 86, 89 0.1 µF 91, 94 0.1 µF 96, 99, 100 0.1 µF Ground. This pin must be connected to system ground. Minimize the ground path impedance for optimal performance. 7, 8, 14, 16, 18, 19, 21, 26, 28, 31, 33, 36, 38, 41, 43, 46, 64, 65 9 GND GND Supply C1B O LVCMOS CKIN1 Invalid Indicator. This pin performs the CK1_BAD function if CK1_BAD_PIN = 1 and is tristated if CK1_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL. 0 = No alarm on CKIN1. 1 = Alarm on CKIN1. CKIN2 Invalid Indicator. This pin performs the CK2_BAD function if CK2_BAD_PIN = 1 and is tristated if CK2_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL. 0 = No alarm on CKIN2. 1 = Alarm on CKIN2. CKIN3 Invalid Indicator. This pin performs the CK3_BAD function if CK3_BAD_PIN = 1 and is tristated if CK3_BAD_PIN = 0. Active polarity is controlled by CK_BAD_POL. 0 = No alarm on CKIN3. 1 = Alarm on CKIN3. 10 C2B O LVCMOS 11 C3B O LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. 8 Preliminary Rev. 0.3 S i5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # 12 Pin Name INT_ALM I/O O Signal Level LVCMOS Description Interrupt/Alarm Output Indicator. This pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit. The INT output function can be turned off by setting INT_PIN = 0. If the ALRMOUT function is desired instead on this pin, set ALRMOUT_PIN = 1 and INT_PIN = 0. 0 = ALRMOUT not active. 1 = ALRMOUT active. The active polarity is controlled by CK_BAD_POL. If no function is selected, the pin tristates. Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator. If manual clock selection is chosen, and if CKSEL_PIN = 1, the CKSEL pins control clock selection and the CKSEL_REG bits are ignored. CS[1:0] 00 01 10 11 Active Input Clock CKIN1 CKIN2 CKIN3 CKIN4 13 57 CS0_C3A CS1_C4A I/O LVCMOS If CKSEL_PIN = 0, the CKSEL_REG register bits control this function and these inputs tristate. If these pins are not functioning as the CS[1:0] inputs and auto clock selection is enabled, then they serve as the CKIN_n active clock indicator. 0 = CKIN3 (CKIN4) is not the active input clock 1 = CKIN3 (CKIN4) is currently the active input to the PLL The CKn_ACTV_REG bit always reflects the active clock status for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be reflected on the CnA pin with active polarity controlled by the CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates. This pin has a weak pull-down. 29 30 CKIN4+ CKIN4– I MULTI Clock Input 4. Differential clock input. This input can also be driven with a single-ended signal. CKIN4 serves as the frame sync input associated with the CKIN2 clock when CK_CONFIG_REG = 1. Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. 34 35 CKIN2+ CKIN2– I MULTI Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. Preliminary Rev. 0.3 9 S i5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # 39 40 Pin Name CKIN3+ CKIN3– I/O I Signal Level MULTI Description Clock Input 3. Differential clock input. This input can also be driven with a single-ended signal. CKIN3 serves as the frame sync input associated with the CKIN1 clock when CK_CONFIG_REG = 1. Clock Input 1. Differential clock input. This input can also be driven with a single-ended signal. CKIN1 Active Clock Indicator. This pin serves as the CKIN1 active clock indicator. The CK1_ACTV_REG bit always reflects the active clock status for CKIN1. If CK1_ACTV_PIN = 1, this status will also be reflected on the C1A pin with active polarity controlled by the CK_ACTV_POL bit. If CK1_ACTV_PIN = 0, this output tristates. CKIN2 Active Clock Indicator. This pin serves as the CKIN2 active clock indicator. The CK2_ACTV_REG bit always reflects the active clock status for CKIN_2. If CK2_ACTV_PIN = 1, this status will also be reflected on the C2A pin with active polarity controlled by the CK_ACTV_POL bit. If CK2_ACTV_PIN = 0, this output tristates. Serial Clock. This pin functions as the serial port clock input for both SPI and I2C modes. This pin has a weak pull-down. Serial Data. In I2C microprocessor control mode (CMODE = 0), this pin functions as the bidirectional serial data port.In SPI microprocessor control mode (CMODE = 1), this pin functions as the serial data output. Serial Port Address. In I2C control mode (CMODE = 0), these pins function as hardware controlled address bits. In SPI control mode (CMODE = 1), these pins are ignored. This pin has a weak pull-down. Serial Port Address/Slave Select. In I2C microprocessor control mode (CMODE = 0), this pin functions as a hardware controlled address bit. In SPI microprocessor control mode (CMODE = 1), this pin functions as the slave select input. This pin has a weak pull-down. 44 45 58 CKIN1+ CKIN1– C1A I MULTI O LVCMOS 59 C2A O LVCMOS 60 SCL I LVCMOS 61 SDA_SDO I/O LVCMOS 68 69 A0 A1 I LVCMOS 70 A2_SS I LVCMOS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. 10 Preliminary Rev. 0.3 S i5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # 71 Pin Name SDI I/O I Signal Level LVCMOS Description Serial Data In. In SPI microprocessor control mode (CMODE = 1), this pin functions as the serial data input. In I2C microprocessor control mode (CMODE = 0), this pin is ignored. This pin has a weak pull-down. Clock Output 3. Differential clock output. Output signal format is selected by SFOUT3_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 1. Differential clock output. Output signal format is selected by SFOUT1_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 5. Differential clock output. Output signal format is selected by SFOUT5_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Control Mode. Selects I2C or SPI control mode for the device. 0 = I2C Control Mode. 1 = SPI Control Mode. Clock Output 2. Differential clock output. Output signal format is selected by SFOUT2_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Clock Output 4. Differential clock output. Output signal format is selected by SFOUT4_REG register bits. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. 77 78 CKOUT3+ CKOUT3– O MULTI 82 83 CKOUT1– CKOUT1+ O MULTI 87 88 CKOUT5– CKOUT5+ O MULTI 90 CMODE I 3-Level 92 93 CKOUT2+ CKOUT2– O MULTI 97 98 CKOUT4– CKOUT4+ O MULTI GND PAD GND PAD GND Supply Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. Preliminary Rev. 0.3 11 S i5367 3. Ordering Guide Ordering Part Number Si5367A-B-GQ Output Clock Frequency Range 10–945 MHz 970–1134 MHz 1.213–1.417 GHz 10–808 MHz 10–346 MHz Package 100-Pin 14 x 14 mm TQFP Temperature Range –40 to 85 °C Si5367B-B-GQ Si5367C-B-GQ 100-Pin 14 x 14 mm TQFP 100-Pin 14 x 14 mm TQFP –40 to 85 °C –40 to 85 °C 12 Preliminary Rev. 0.3 S i5367 4. Package Outline: 100-Pin TQFP Figure 4 illustrates the package details for the Si5367. Table 4 lists the values for the dimensions shown in the illustration. Figure 4. 100-Pin Thin Quad Flat Package (TQFP) Table 4. 100-Pin Package Diagram Dimensions Dimension A A1 A2 b c D D1 D2 e 3.85 Min — 0.05 0.95 0.17 0.09 Nom — — 1.00 0.22 — 16.00 BSC. 14.00 BSC. 4.00 0.50 BSC. 4.15 Max 1.20 0.15 1.05 0.27 0.20 Dimension E E1 E2 L aaa bbb ccc ddd θ 3.85 0.45 — — — — 0º Min Nom 16.00 BSC. 14.00 BSC. 4.00 0.60 — — — — 3.5º 4.15 0.75 0.20 0.20 0.08 0.08 7º Max Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant AED-HD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.3 13 S i5367 5. Recommended PCB Layout Figure 5. PCB Land Pattern Diagram 14 Preliminary Rev. 0.3 S i5367 Table 5. PCB Land Pattern Dimensions Dimension e E D E2 D2 GE GD X Y ZE ZD R1 R2 — — — 0.15 REF 1.00 3.90 3.90 13.90 13.90 — 1.50 REF. 16.90 16.90 MIN 0.50 BSC. 15.40 REF. 15.40 REF. 4.10 4.10 — — 0.30 MAX Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.3 15 S i5367 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 3. Updated “2. Pin Descriptions: Si5367”. Changed FSOUT (pins 87 and 88) to CLKOUT5. Changed FS_ALIGN (pin 21) control pin to GND. Changed pin 16 to ground. Revision 0.2 to Revision 0.3 Removed references to latency control, INC, and DEC pins. Updated block diagram on page 1. Added Figure 1, “Typical Phase Noise Plot,” on page 4. Updated “2. Pin Descriptions: Si5367”. Changed font of register names to underlined italics. Updated "3. Ordering Guide" on page 12. Added “5. Recommended PCB Layout”. 16 Preliminary Rev. 0.3 S i5367 NOTES: Preliminary Rev. 0.3 17 S i5367 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 18 Preliminary Rev. 0.3