SI5368

Si5368 P R E L I M I N A R Y D A TA S H E E T A N Y -R A T E P R E C I S I O N C L O C K M U L T I P L I E R /J I T T E R A T T E N U A T O R Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5368 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5368 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) SONET frame sync switching and regeneration Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement Xtal or Refclock CKIN1 CKIN2 CKIN3 CKIN4 ÷ N31 ÷ N32 ÷ N33 ÷ N34 ÷ N2 ÷ NC3 CKOUT3 ÷ NC1 CKOUT1 DSPLL ® ÷ NC2 CKOUT2 I2C/SPI Port Rate Select Clock Select Latency Control FSYNC Realignment Device Interrupt LOL/LOS/FOS Alarms Control Output Clock 2 Input Clock 3 Input Clock 4 ÷ NFS CKOUT5/FS_OUT VDD (1.8 or 2.5 V) GND ÷ NC4 CKOUT4 Preliminary Rev. 0.3 3/07 Copyright © 2007 by Silicon Laboratories Si5368 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5368 Table 1. Performance Specifications (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD IDD Test Condition Min –40 2.25 1.62 Typ 25 2.5 1.8 394 Max 85 2.75 1.98 435 Unit ºC V V mA Supply Current fOUT = 622.08 MHz All CKOUTs enabled LVPECL format output Only CKOUT1 enabled fOUT = 19.44 MHz All CKOUTs enabled CMOS format output Only CKOUT1 enabled Tristate/Sleep Mode — — — 253 278 284 321 mA mA — — 0.002 229 TBD — 261 TBD 710 mA mA MHz Input Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4) Input Clock Frequency (CKIN3, CKIN4 used as FSYNC inputs) Output Clock Frequency (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5 used as fifth high-speed output) CKOUT5 used as frame sync output (FS_OUT) Differential Voltage Swing Common Mode Voltage CKF CKF CKOF Input frequency and clock multiplication ratio determined by programming device PLL dividers. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing to determine PLL divider settings for a given input frequency/clock multiplication ratio combination. 0.002 — 0.512 MHz 0.002 970 1213 — — — 945 1134 1417 MHz CKOF 0.002 — 710 MHz Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4) CKNDPP CKNVCM CKNTRF CKNDC 1.8 V ±10% 2.5 V ±10% Rise/Fall Time Duty Cycle 20–80% Whichever is less 0.25 0.9 1.0 — 40 50 — — — — — — 1.9 1.4 1.7 11 60 — VPP V V ns % ns Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. 2 Preliminary Rev. 0.3 S i5368 Table 1. Performance Specifications (Continued) (VDD = 1.8 or 2.5 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT) Common Mode Differential Output Swing Single Ended Output Swing PLL Performance Jitter Generation JGEN fOUT = 622.08 MHz, LVPECL output format 50 kHz–80 MHz 12 kHz–20 MHz Jitter Transfer External Reference Jitter Transfer Phase Noise JPK JPKEXTN CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient θJA Still Air — 40 — ºC/W SPSUBH Phase Noise @ 100 kHz Offset SPSPUR Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) — 0.3 TBD ps rms VOCM VOD VSE LVPECL 100 Ω load line-to-line VDD – 1.42 1.1 0.5 — — — VDD – 1.25 1.9 0.93 V VDD Vpp — — — — — — — — — — 0.3 0.05 TBD TBD TBD TBD TBD TBD TBD TBD TBD 0.1 TBD TBD TBD TBD TBD TBD TBD TBD ps rms dB dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. Preliminary Rev. 0.3 3 S i5368 155.52 MHz in, 622.08 MHz out 0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 2.75 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 JESD78 Compliant Unit V V ºC ºC kV V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 4 Preliminary Rev. 0.3 S i5368 Figure 2. Si5368 Typical Application Circuit (I2C Control Mode) Figure 3. Si5368 Typical Application Circuit (SPI Control Mode) Preliminary Rev. 0.3 5 S i5368 1. Functional Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for every input clock and output clock, so the Si5368 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The Si5368 input clock frequency and clock multiplication ratio are programmable through Optionally, the fifth clock an I2C or SPI interface. output can be configured as a 2 to 512 kHz SONET/SDH frame synchronization output that is phase aligned with one of the high-speed output clocks. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. This utility can be downloaded from www.silabs.com/timing. The Si5368 is based on Silicon Laboratories' 3rdgeneration DSPLL® technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5368 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5368 supports hitless switching between input clocks in compliance with GR-253-CORE and GR-1244CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (