SI571

Si 5 7 0 / S i 5 71 P R E L I M I N A R Y D A TA S H E E T A N Y - R A T E I 2C P R O G R A M M A B L E X O/VCXO Features Any-rate programmable output frequencies from 10 to 945 MHz and select frequencies to 1.4 GHz I2C serial interface 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available LVPECL, CMOS, LVDS, and CML outputs Industry-standard 5x7 mm package Pb-free/RoHS-compliant 1.8, 2.5, or 3.3 V supply Si5602 Applications SONET / SDH xDSL 10 GbE LAN / WAN Low-jitter clock generation Optical modules Clock and data recovery Ordering Information: See page 21. Description The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with ±100 ppm of f0 ±25 — — — — — — — ±375 10 100 10 ppm ms µs ms Notes: 1. See Section "7. Ordering Information" on page 21 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM = 1/2 x VDD. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO. 6 Rev. 0.3 S i570/Si571 Table 4. CLK± Output Levels and Symmetry Parameter LVPECL Output Option1 Symbol VO VOD VSE Test Condition mid-level swing (diff) swing (single-ended) mid-level swing (diff) Min VDD – 1.42 1.1 0.55 1.125 0.5 Typ — Max VDD – 1.25 1.9 0.95 1.275 0.9 Units V VPP VPP V VPP — — 1.20 0.7 LVDS Output Option2 VO VOD CML Output Option2 CMOS Output Option3 Rise/Fall time (20/80%) VO VOD VOH VOL mid-level swing (diff) IOH = 32 mA IOL = 32 mA — 0.70 0.8 x VDD VDD – 0.75 0.95 — — — 1 — — 1.20 VDD V VPP V — — — 45 0.4 350 — 55 tR, tF LVPECL/LVDS/CML CMOS with CL = 15 pF LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 ps ns % Symmetry (duty cycle) SYM Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF Table 5. CLK± Output Phase Jitter (Si570) Parameter Phase Jitter (RMS)* for FOUT > 500 MHz Phase Jitter (RMS)* for FOUT of 125 to 500 MHz Symbol Test Condition 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min — — — — Typ 0.25 0.26 0.36 0.34 Max 0.40 0.37 0.50 0.42 ps Units ps φJ φJ 12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz (OC-192) *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Rev. 0.3 7 S i570/Si571 Table 6. CLK± Output Phase Jitter (Si571) Parameter Phase Jitter (RMS)1,2,3 for FOUT > 500 MHz Symbol Test Condition Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min — — — — — — — — — — — — Typ 0.26 0.26 0.27 0.26 0.32 0.26 0.40 0.27 0.49 0.28 0.87 0.33 Max — — — — — — — — — — — — Units ps φJ Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. 8 Rev. 0.3 S i570/Si571 Table 6. CLK± Output Phase Jitter (Si571) (Continued) Parameter Phase Jitter for FOUT of 125 to 500 MHz (RMS)1,2,3 Symbol Test Condition Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min — — — — — — — — — — — — Typ 0.37 0.33 0.37 0.33 0.43 0.34 0.50 0.34 0.59 0.35 1.00 0.39 Max — — — — — — — — — — — — Units ps φJ Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information. 3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions. Table 7. CLK± Output Period Jitter Parameter Period Jitter* Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ 2 14 Max — — Units ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter from Phase Noise” for further information. Rev. 0.3 9 S i570/Si571 Table 8. Typical CLK± Output Phase Noise (Si570) Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 120.00 MHz LVDS –112 –122 –132 –137 –144 –150 n/a 156.25 MHz LVPECL –105 –122 –128 –135 –144 –147 n/a 622.08 MHz LVPECL –97 –107 –116 –121 –134 –146 –148 Units dBc/Hz Table 9. Typical CLK± Output Phase Noise (Si571) Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz –87 –114 –132 –142 –148 –150 n/a 491.52 MHz 45 ppm/V LVPECL –75 –100 –116 –124 –135 –146 –147 622.08 MHz 135 ppm/V LVPECL –65 –90 –109 –121 –134 –146 –147 Units dBc/Hz Table 10. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (lead-free profile) Soldering Temperature Time @ TPEAK (lead-free profile) Symbol VDD VI TS ESD TPEAK tP Rating –0.5 to +3.8 –0.5 to VDD + 0.3 –55 to +125 >2500 260 20–40 Units Volts Volts ºC Volts ºC seconds Notes: 1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. 10 Rev. 0.3 S i570/Si571 Table 11. Environmental Compliance The Si570/571 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/Test Method MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016 Table 12. Programming Constraints (VDD = 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition HS_DIV x N1 > = 6 HS_DIV x N1 = 5 N1 = 1 HS_DIV = 4 N1 = 1 Min 10 970 1.2125 — 4850 — Typ — — — 0.09 — — Max 945 1134 1.4175 — 5670 10 Unit MHz MHz GHz ppb MHz ms Output Frequency CKOF M and RFREQ Value LSB Resolution Internal Oscillator Frequency Unfreeze to NewFreq Delay MRES fOSC 114.285 MHz 3rd Overtone Crystal Rev. 0.3 11 S i570/Si571 3. Functional Description The Si570 XO and the Si571 VCXO are low-jitter, programmable oscillators ideally suited for applications requiring multiple frequencies. The Si57x can be programmed to generate any output clock rate between 10 and 1.4 GHz with