S i 8 2 2 0/21
0 . 5 A N D 2 . 5 A M P I S O D R I VE R S W I T H O P T O I N P U T
(2.5, 3.75, AND 5.0 KV RMS)
Features
Functional upgrade for HCPL-0302,
HCPL-3120, TLP350, and similar
opto-drivers
60 ns propagation delay max
(independent of input drive current)
14x tighter part-to-part matching
versus opto-drivers
2.5, 3.75, and 5.0 kVRMS isolation
Transient Immunity
30 kV/µs
Under-voltage lockout protection with
hysteresis
Resistant to temperature and aging
effects
Gate driver supply voltage
6.5 V to 24 V
Wide operating range
–40
to +125 °C
Pin Assignments:
See page 20
Narrow Body SOIC
NC
8 VDD
1
ANODE 2
7 VO
CATHODE
6 VO
3
NC 4
5 VSS
RoHS-compliant packages
Top View
SOIC-8
narrow body
SOIC-16 wide body
Wide Body SOIC
CATHODE
Applications
NC
IGBT/ MOSFET gate drives
Industrial control systems
Switch mode power supplies
UPS systems
Motor control drives
Inverters
UL 1577 recognized
Up
to 5000 Vrms for 1 minute
CSA component notice 5A
approval
ANODE
NC
NC
Safety Regulatory Approvals
NC
CATHODE
VDE certification conformity
IEC
EN
NC
1
2
3
4
5
6
7
8
60747-5-2 (VDE 0884 Part 2)
60950-1 (reinforced insulation)
16
15
14
13
12
11
10
9
VSS
VDD
NC
VO
NC
NC
NC
VSS
Top View
Patent pending
IEC
60950-1, 61010-1, 60601-1
(reinforced insulation)
Description
The Si8220/21 is a high-performance functional upgrade for opto-coupled
drivers, such as the HCPL-3120 and the HPCL-0302 providing 2.5 A of
peak output current. It utilizes Silicon Laboratories' proprietary silicon
isolation technology, which provides a choice of 2.5, 3.75, or 5.0 kVRMS
withstand voltages per UL1577. This technology enables higher
performance, reduced variation with temperature and age, tighter part-topart matching, and superior common-mode rejection compared to optoisolated drivers. While the input circuit mimics the characteristics of an
LED, less drive current is required, resulting in increased efficiency.
Propagation delay time is independent of input drive current, resulting in
consistently short propagation time, tighter unit-to-unit variation, and
greater input circuit design flexibility.
Rev. 1.2 4/13
Copyright © 2013 by Silicon Laboratories
Si8220/21
Si8220/21
Functional Block Diagram
NC
VDD
ANODE
RF
Transmitter
CATHODE
Semiconductor-Based
Isolation Barrier
ISOLATOR
LED
Emulator
VO
RF
Receiver
UV
Lockout
VO
VSS
NC
2
Si8220/21
Rev. 1.2
Si8220/21
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6.4. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5. Parametric Differences between Si8220/21 and
HCPL-0302 and HCPL-3120 Opto Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
13. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
15. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.2
3
Si8220/21
1. Electrical Specifications
Table 1. Electrical Characteristics 1
VDD = 12 V or 15 V, VSS = GND, TA = –40 to +125 °C; typical specs at 25 °C.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
VDD
(VDD – VSS)
6.5
—
24
V
DC Specifications
Power Supply Voltage
Input Current (ON)
IF(ON)
5.0
—
20
mA
Input Current Rising Edge
Hysteresis
IHYS
—
0.5
—
mA
Input Voltage (OFF)
Input Forward Voltage
Output Resistance High (Source)
Output Resistance Low (Sink)
Output High Current (Source)
Output Low Current (Sink)
High-Level Output Voltage
VF(OFF)
Measured at ANODE with
respect to CATHODE.
–0.6
—
1.6
V
VF
Measured at ANODE with
respect to CATHODE.
IF = 5 mA.
1.7
—
2.5
V
0.5 A devices
—
15
—
2.5 A devices
—
2.7
—
0.5 A devices
—
5.0
—
2.5 A devices
—
1.0
—
(0.5 A), IF = 0
(see Figure 2)
—
0.3
—
ROH
ROL
IOH
IOL
A
(2.5 A), IF = 0
(see Figure 2)
—
1.5
—
(0.5 A), IF = 10 mA,
(see Figure 1)
—
0.5
—
A
(2.5 A), IF = 10 mA,
(see Figure 1)
—
2.5
—
(0.5 A), I OUT = –50 mA
—
VDD–
0.5
—
V
VOH
VDD–
0.1
(2.5 A), I OUT = –50 mA
Low-Level Output Voltage
VOL
(0.5 A), I OUT = 50 mA
—
200
—
mV
(2.5 A), I OUT = 50 mA
50
High-Level Supply Current
Output open IF = 10 mA
—
1.2
—
mA
Low-Level Supply Current
Output open
VF = –0.6 to +1.6 V
—
1.4
—
mA
Notes:
1. VDD = 12 V for 5, 8, and 10 V UVLO devices; VDD = 15 V for 12.5 V UVLO devices.
2. See "9.Ordering Guide" on page 22 for more information.
4
Rev. 1.2
Si8220/21
Table 1. Electrical Characteristics (Continued)1
VDD = 12 V or 15 V, VSS = GND, TA = –40 to +125 °C; typical specs at 25 °C.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Input Reverse Voltage
BVR
IR = 10 mA.
Measured at ANODE with
respect to CATHODE.
0.5
—
—
V
Input Capacitance
CIN
—
10
—
pF
VDD Undervoltage Threshold2
VDDUV+
VDD rising
5 V Threshold
See Figure 9 on page 15.
5.20
5.80
6.30
V
8 V Threshold
See Figure 10 on page 15.
7.50
8.60
9.40
V
10 V Threshold
See Figure 11 on page 15.
9.60
11.1
12.2
V
12.5 V Threshold
See Figure 12 on page 15.
12.4
13.8
14.8
VDD Undervoltage Threshold2
VDDUV–
VDD falling
5 V Threshold
See Figure 9 on page 15.
4.90
5.52
6.0
V
8 V Threshold
See Figure 10 on page 15.
7.20
8.10
8.70
V
10 V Threshold
See Figure 11 on page 15.
9.40
10.1
10.9
V
12.5 V Threshold
See Figure 12 on page 15.
11.6
12.8
13.8
VDD Lockout Hysteresis
VDDHYS
UVLO voltage = 5 V
—
280
—
mV
VDD Lockout Hysteresis
VDDHYS
UVLO voltage = 8 V
—
600
—
mV
VDD Lockout Hysteresis
VDDHYS
UVLO voltage = 10 V or
12.5 V
—
1000
—
mV
Propagation Delay Time to High
Output Level
tPLH
CL = 200 pF
—
—
60
ns
Propagation Delay Time to Low
Output Level
tPHL
CL = 200 pF
—
—
40
ns
—
30
tR, tF
(0.5 A), CL = 200 pF
—
Output Rise and Fall Time
(2.5 A), CL = 200 pF
—
—
20
AC Specifications
ns
Device Startup Time
tSTART
Time from
VDD = VDD_UV+ to VO
—
—
40
µs
Common Mode
Transient Immunity
CMTI
Input ON or OFF
VCM = 1500 V (see Figure 3)
—
30
—
kV/µs
Notes:
1. VDD = 12 V for 5, 8, and 10 V UVLO devices; VDD = 15 V for 12.5 V UVLO devices.
2. See "9.Ordering Guide" on page 22 for more information.
Rev. 1.2
5
Si8220/21
2. Test Circuits
VDD = 15 V
VDD
IN
10
OUT
Si822x
SCHOTTKY
VSS
1 µF
8V
100 µF
+
_
INPUT
1 µF
CER
Measure
10 µF
EL
RSNS
0.1
50 ns
IF
GND
200 ns
INPUT WAVEFORM
Figure 1. IOL Sink Current Test Circuit
VDD = 15 V
VDD
IN
Si822x
10
OUT
SCHOTTKY
VSS
1 µF
INPUT
1 µF
CER
Measure
10 µF
EL
RSNS
0.1
50 ns
IF
GND
200 ns
INPUT WAVEFORM
Figure 2. IOH Source Current Test Circuit
6
Rev. 1.2
100 µF
5.5 V
+
_
Si8220/21
12 V
Supply
267
Input Signal
Switch
Si822x
ANODE
Isolated
Supply
VDD
VO
Oscilloscope
CATHODE
GND
Isolated
Ground
Input
High Voltage
Differential Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3. Common Mode Transient Immunity Test Circuit
Rev. 1.2
7
Si8220/21
3. Regulatory Information
Table 2. Regulatory Information*
CSA
The Si822x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si822x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working
voltage.
UL
The Si822x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "9.Ordering Guide" on page 22.
8
Rev. 1.2
Si8220/21
Table 3. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
WB
SOIC-16
NB
SOIC-8
Unit
Nominal Air Gap (Clearance)1
L(IO1)
8.0 min
4.9 min
mm
Nominal External Tracking (Creepage)1
L(IO2)
8.0 min
4.01 min
mm
0.014
0.014
mm
600
600
V
0.040
0.040
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
Resistance (Input-Output)2
RIO
Capacitance (Input-Output)2
CIO
Input Capacitance3
CI
IEC60112
12
10
f = 1 MHz
10
12
2.0
1.0
pF
4.0
4.0
pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "12.Package Outline:
16-Pin Wide Body SOIC" on page 25, "10.Package Outline: 8-Pin Narrow Body SOIC" on page 23. VDE certifies the
clearance and creepage limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB
SOIC-8 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB
SOIC-16 package.
2. To determine resistance and capacitance, the Si822x is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Rev. 1.2
9
Si8220/21
Table 4. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Basic Isolation Group
Installation Classification
Test Conditions
Specification
NB SOIC8
WB SOIC 16
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-III
I-IV
Rated Mains Voltages < 400 VRMS
I-II
I-III
Rated Mains Voltages < 600 VRMS
I-II
I-III
Material Group
Table 5. IEC 60747-5-2 Insulation Characteristics for Si822xxC*
Characteristic
Parameter
Maximum Working Insulation
Voltage
Symbol
Test Condition
VIORM
Input to Output Test Voltage
VPR
Highest Allowable Overvoltage
(Transient Overvoltage,
tTR = 60 sec)
VTR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS,
VIO = 500 V
RS
WB
SOIC-16
NB SOIC-8
891
560
1671
1050
6000
4000
2
2
>109
>109
Unit
V peak
V peak
V peak
*Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The Si822x provides a climate classification of 40/125/21.
10
Rev. 1.2
Si8220/21
Table 6. IEC Safety Limiting Values1
Parameter
Symbol
Case Temperature
TS
Safety Input, Output, or
Supply Current
IS
Device Power Dissipation2
PD
Max
Test Condition
WB SOIC-16 NB SOIC-8
Unit
150
150
°C
50
40
mA
1.2
1.2
W
JA = 140 °C/W (NB SOIC-8),
100 °C (WB SOIC-16),
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 5 and 6.
2. The Si822x is tested with VO = 24 V, TJ = 150 ºC, CL = 200 pF, input a 2 MHz 50% duty cycle square wave.
Table 7. Thermal Characteristics
Parameter
JA
IC Junction-to-Air Thermal
Resistance
Safety-Limiting Current (mA)
Typ
Symbol
WB SOIC-16
NB SOIC-8
100
140
Unit
ºC/W
60
50
40
VDD = 24 V
30
20
10
0
0
50
100
150
Case Temperature (ºC)
200
Figure 4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.2
11
Safety-Limiting Current (mA)
Si8220/21
60
50
VDD = 24 V
40
30
20
10
0
0
50
100
150
Case Temperature (ºC)
200
Figure 5. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 8. Absolute Maximum Ratings1
Parameter
Storage Temperature2
Conditions
Min
Typ
Max
Units
TSTG
–65
—
+150
C
–40
—
+125
C
Operating Temperature
Output Supply Voltage
VDD
–0.6
—
30
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive
IO
—
—
10
mA
IF(AVG)
–100
—
30
mA
Lead Solder Temperature (10 s)
—
—
260
C
Maximum Isolation Voltage (1 s) NB SOIC-8
—
—
4250
VRMS
Maximum Isolation Voltage (1 s) WB SOIC-16
—
—
6500
VRMS
Input Current
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
12
Rev. 1.2
Si8220/21
4. Functional Description
4.1. Theory of Operation
The Si8220/21 is a functional upgrade for popular opto-isolated drivers, such as the Avago HPCL-3120, HPCL0302, Toshiba TLP350, and others. The operation of an Si8220/21 channel is analogous to that of an opto coupler,
except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and
requires no special considerations or initialization at start-up. A simplified block diagram for the Si8220/21 is shown
in Figure 6.
Transmitter
Receiver
RF
OSCILLATOR
VDD
A
LED
Emulator
MODULATOR
SemiconductorBased Isolation
Barrier
B
DEMODULATOR
0.5 to 2.5 A
peak
Gnd
Figure 6. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 7 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 7. Modulation Scheme
Rev. 1.2
13
Si8220/21
5. Technical Description
5.1. Device Behavior
Truth tables for the Si8220/21 are summarized in Table 9.
Table 9. Si8220/21 Truth Table Summary
Cathode
Anode
Diode Current (IF)
VDD
VO
Comments
X
X
X
< UVLO
L
Device turned off
Hi-Z
X
0
> UVLO
L
Logic low state
X
Hi-Z
0
> UVLO
L
Logic low state
GND
GND
0
> UVLO
L
Logic low state
VF
VF
0
> UVLO
L
Logic low state
GND1
VF
< IF(OFF
> UVLO
L
Logic low state
GND1
VF
> IF(OFF)
> UVLO
H
Logic high state
Note: “X” = don’t care. This truth table assumes VDD is powered. If VDD is below UVLO, see "5.3.Under
Voltage Lockout (UVLO)" on page 15 for more information.
5.2. Device Startup
Output VO is held low during power-up until VDD rises above the UVLO+ threshold for a minimum time period of
tSTART. Following this, the output is high when the current flowing from anode to cathode is > IF(ON). Device startup,
normal operation, and shutdown behavior is shown in Figure 8.
UVLO+
UVLO-
VDDHYS
VDD
IF(ON)
IHYS
IF
tSTART
tPHL
tPLH
tSTART
VO
Figure 8. Si8220/21 Operating Behavior (IF > IF(MIN) when VF > VF(MIN))
14
Rev. 1.2
Si8220/21
5.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 9
through 12, upon power up, the Si8220/21 is maintained in UVLO until VDD rises above VDDUV+. During power
down, the Si8220/21 enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+
– VDDHYS).
V DDUV+ (Typ)
3.5
Output Voltage (VO) 10.5
Output Voltage (VO) 10.5
V DDUV+ (Typ)
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.5
Supply Voltage (V DD - V SS) (V)
Figure 9. Si8220/21 UVLO Response (5 V)
9.0
10.0 10.5 11.0 11.5 12.0 12.5
Figure 11. Si8220/21 UVLO Response (10 V)
V DDUV+ (Typ)
Output Voltage (VO) 10.5
Output Voltage (VO) 10.5
V DDUV+ (Typ)
6.0
9.5
Supply Voltage (V DD - V SS) (V)
6.5
7.0
7.5
8.0
8.5
9.0
11.3
9.5 10.0
Figure 10. Si8220/21 UVLO Response (8 V)
11.8
12.3 12.8 13.3 13.8 14.3 14.8 15.3
Supply Voltage (V DD - V SS) (V)
Supply Voltage (V DD - V SS) (V)
Figure 12. Si8220/21 UVLO Response (12.5 V)
Rev. 1.2
15
Si8220/21
6. Applications
6.1. Power Supply Connections
VSS can be biased at, above, or below ground as long as the voltage on VDD with respect to VSS is a maximum of
24 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The optimum values
for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 10 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance.
6.2. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si8220/21 as close to the device it is driving as
possible. In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power
and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes
for power devices and small signal components provides the best overall noise performance.
6.3. Power Dissipation Considerations
Proper system design must assure that the Si8220/21 operates within safe thermal limits across the entire load
range. The Si8220/21 total power dissipation is the sum of the power dissipated by bias supply current, internal
switching losses, and power delivered to the load, as shown in Equation 1.
2
2
P D = V F I F Duty Cycle + V DD I QOUT + C int V DD F + C L V DD F
where:
P D is the total Si8220 device power dissipation (W)
I F is the diode current (20 mA max)
V F is the diode anode voltage (2.8 V max)
I QOUT is the driver maximum bias curent (5 mA)
C int is the internal parasitic capacitance (370 pF)
V DD is the driver-side supply voltage (24 V max)
F is the switching frequency (Hz)
Equation 1.
The maximum allowable power dissipation for the Si8220/21 is a function of the package thermal resistance,
ambient temperature, and maximum allowable junction temperature, as shown in Equation 2.
T jmax – T A
P Dmax -------------------------- ja
where:
P Dmax is the maximum allowable Si8220/21 power dissipation (W)
T jmax is the Si8220/21 maximum junction temperature (150 °C)
T A is the ambient temperature (°C)
ja is the Si8220/21 package junction-to-air thermal resistance (125 °C/W)
Equation 2.
Substituting values for PDmax Tjmax, TA, and ja into Equation 2 results in a maximum allowable total power
dissipation of 1.0 W. The maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 4 into Equation 1 and simplifying. The result is Equation 3, where VF = 2.8 V,
IF = 10 mA, and VDD = 18 V.
16
Rev. 1.2
Si8220/21
–3
– 10
1.35 10
C L max = ------------------------------ – 1.85 10
F
where:
C L max is the maximum load (pF) allowable at switching frequency F
Equation 3.
A graph of Equation 3 is shown in Figure 13. Each point along the load line in this graph represents the package
dissipation-limited value of CL for the corresponding switching frequency.
Load (pF)
10,000
1,000
100
0
500
1,000
1,500
2,000
2,500
Frequency (KHz)
Figure 13. Maximum Load vs. Switching Frequency
6.4. Input Circuit Design
Opto driver manufacturers typically recommend the circuits shown in Figures 14 and 15. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
OPTO DRIVER
Vdd
1 N/C
R1
2 ANODE
3 CATHODE
Control
Input
Open Drain or
Collector
4 N/C
Figure 14. Opto Driver Input Circuit
Rev. 1.2
17
Si8220/21
Vdd
OPTO DRIVER
1 N/C
2 ANODE
Control
Input
Q1
3 CATHODE
R1
4 N/C
Figure 15. High CMR Opto Driver Input Circuit
The optically-coupled driver circuit of Figure 14 turns the LED on when the control input is high. However, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 15 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing commonmode transient immunity. Some opto driver applications also recommend reverse-biasing the LED when the
control input is off to prevent coupled noise from energizing the LED.
The Si8220/21 can be used with the input circuits shown in Figures 14 and 15; however, some applications will
require increasing the value of R1 in order to limit IF to a maximum of 20 mA. The Si8220/21 propagation delay and
output drive do not change for values of IF between IF(MIN) and IF(MAX). New designs should consider the input
circuit configurations of Figure 16, which are more efficient than those of Figures 14 and 15. As shown, S1
represents any suitable switch, such as a BJT or MOSFET, analog transmission gate, processor I/O, etc. Also, note
that the Si8220/21 input can be driven from the I/O port of any MCU or FPGA capable of sourcing a minimum of
5 mA (see Figure 16C).
+5V
+5V
Si8220/21
Control
Input
1
N/C
2
ANODE
3
CATHODE
4
N/C
R1
Si8220/21
Si8220/21
1
N/C
2
ANODE
1
N/C
2
ANODE
S1
See Text
3
Control
Input
S1
R1
4
MCU I/O
Port pin
3 CATHODE
CATHODE
R1
N/C
4 N/C
See Text
A
B
Figure 16. Si8220/21 Other Input Circuit Configurations
18
Rev. 1.2
C
Si8220/21
6.5. Parametric Differences between Si8220/21 and
HCPL-0302 and HCPL-3120 Opto Drivers
The Si8220/21 is designed to directly replace HCPL-3120 and similar opto drivers. Parametric differences are
summarized in Table 10 below.
Table 10. Parametric Differences of Si8220 vs. HCPL-3120
Parameter
Si8220
HCPL-3120
Units
24
30
V
5 to 20
7 to 16
mA
–0.6 to +1.6
–0.3 to +0.8
V
0.5
–5
V
UVLO threshold (rising)
5.8 to 13.8
11.0 to 13.5
V
UVLO threshold (falling)
5.5 to 12.8
9.7 to 12.0
V
0.28 to 1
1.6
V
20
100
ns
Max supply voltage
ON state forward input current
OFF state input voltage
Max reverse input voltage
UVLO hysteresis
Rise/fall time into 10 in series with 10 nF
Table 11. Parametric Differences of Si8221 vs. HCPL-0302
Parameter
Si8221
HCPL-0302
Units
24
30
V
5 to 20
7 to 16
mA
–0.6 to +1.6
–0.3 to +0.8
V
0.5
–5
V
UVLO threshold (rising)
5.8 to 13.8
11.0 to 13.5
V
UVLO threshold (falling)
5.5 to 12.8
9.7 to 12.0
V
0.28 to 1
1.6
V
20
100
ns
Max supply voltage
ON state forward input current
OFF state input voltage
Max reverse input voltage
UVLO hysteresis
Rise/fall time into 10 in series with 10 nF
6.5.1. Supply Voltage and UVLO
The supply voltage of the Si8220/21 is limited to 24 V, and the UVLO voltage thresholds are scaled accordingly.
Opto replacement applications should limit their supply voltages to 24 V or less.
6.5.2. Input Diode Differences
The Si8220/21 input circuit requires less current and has twice the off-state noise margin compared to opto drivers.
However, high CMR opto driver designs that overdrive the LED (see Figure 15) may require increasing the value of
R1 to limit input current to 20 mA max. In addition, there is no benefit in driving the Si8220/21 input diode into
reverse bias when in the off state. Consequently, opto driver circuits using this technique should either leave the
negative bias circuitry unpopulated or modify the circuitry (e.g. add a clamp diode) to ensure that the anode pin of
the Si8220/21 is no more than –0.8 V with respect to the cathode when reverse-biased.
Rev. 1.2
19
Si8220/21
7. Pin Descriptions (Narrow-Body SOIC)
NC
ANODE
CATHODE
NC
Si8220/21
8
1
7
2
6
3
5
4
VDD
VO
VO
VSS
Top View
Figure 17. Pin Configuration
Table 12. Pin Descriptions (Narrow-Body SOIC)
Pin
Name
1
NC
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC
No connect.
5
VSS
External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6
VO
Output signal. Pins 6 and 7 are connected together internally.
7
VO
Output signal. Pins 6 and 7 are connected together internally.
8
VDD
Output-side power supply input referenced to VSS (24 V max).
*Note: No Connect. These pins are not internally connected.
20
Rev. 1.2
Si8220/21
8. Pin Descriptions (Wide-Body SOIC)
Si8220
CATHODE
NC
NC
ANODE
NC
NC
CATHODE
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
VDD
NC
VO
NC
NC
NC
VSS
Top View
Table 13. Pin Descriptions (Wide-Body SOIC)
Pin
1,7
Name
Description
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this
input.
2,3,5,6,8,
10,11,12,
14
NC*
No connect.
4
ANODE
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
9,16
VSS
External MOSFET source connection and ground reference for VDD. This terminal is
typically connected to ground but may be tied to a negative or positive voltage.
13
VO
Output signal.
15
VDD
Output-side power supply input referenced to VSS (24 V max).
*Note: No Connect. These pins are not internally connected.
Rev. 1.2
21
Si8220/21
9. Ordering Guide
Table 14. Si8220/21 Ordering Guide*
Ordering Options
New Ordering
Part Number
(OPN)
Input
Configuration
Si8220BB-A-IS
Peak Output
Current
(Cross Reference)
UVLO
Voltage
Insulation
Rating
Temp Range
Pkg Type
Opto input
2.5 A
(HCPL-3120)
8V
default
2.5 kVrms
–40 to +125 °C
SOIC-8
Si8220CB-A-IS
Opto input
2.5 A
(HCPL-3120)
10 V
2.5 kVrms
–40 to +125 °C
SOIC-8
Si8220DB-A-IS
Opto input
2.5 A
(HCPL-3120)
12.5 V
2.5 kVrms
–40 to +125 °C
SOIC-8
Si8220BD-A-IS
Opto input
2.5 A
(HCPL-3120)
8V
default
5.0 kVrms
–40 to +125 °C
WB SOIC-16
Si8220CD-A-IS
Opto input
2.5 A
(HCPL-3120)
10 V
5.0 kVrms
–40 to +125 °C
WB SOIC-16
Si8220DD-A-IS
Opto input
2.5 A
(HCPL-3120)
12.5 V
5.0 kVrms
–40 to +125 °C
WB SOIC-16
Si8221CC-A-IS
Opto input
0.5 A
(HCPL-0302)
10 V
3.75 kVrms
–40 to +125 °C
SOIC-8
Si8221DC-A-IS
Opto input
0.5 A
(HCPL-0302)
12.5 V
3.75 kVrms
–40 to +125 °C
SOIC-8
*Note: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL2A for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages.
“Si” and “SI” are used interchangeably.
22
Rev. 1.2
Si8220/21
10. Package Outline: 8-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si822x. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 18. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
0
8
Rev. 1.2
23
Si8220/21
11. Land Pattern: 8-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si822x in an 8-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 19. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 16. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
24
Rev. 1.2
Si8220/21
12. Package Outline: 16-Pin Wide Body SOIC
Figure 20 illustrates the package details for the Si822x Digital Isolator. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 20. 16-Pin Wide Body SOIC
Rev. 1.2
25
Si8220/21
Table 17. Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for
small body, lead-free components.
26
Rev. 1.2
Si8220/21
13. Land Pattern: 16-Pin Wide-Body SOIC
Figure 21 illustrates the recommended land pattern details for the Si822x in a 16-pin wide-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 21. 16-Pin SOIC Land Pattern
Table 18. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.2
27
Si8220/21
14. Top Marking: 16-Pin Wide Body SOIC
Si82CIUV
YYWWTTTTTT
e4
TW
Figure 22. 16-Pin Wide Body SOIC Top Marking
Table 19. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
Line 3 Marking:
28
Si82 = ISOdriver product series
C = Input configuration
2 = Opto input type
I = Peak output current
Base Part Number
0 = 2.5A; 1 = 0.5A
Ordering Options
See Ordering Guide for more U = UVLO level
information.
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
D = 5.0 kV
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
Circle = 1.5 mm Diameter
(Center Justified)
"e4" Pb-Free Symbol
Country of Origin
ISO Code Abbreviation
TW = Taiwan
Rev. 1.2
Si8220/21
15. Top Marking: 8-Pin Narrow Body SOIC
Si82CIUV
TTTTTT
e4 YYWW
Figure 23. 8-Pin Narrow Body SOIC Top Marking
Table 20. 8-Pin Narrow Body SOIC Top Marking Explanations
Line 1 Marking:
Base Part Number
Ordering Options
(See Ordering Guide for more
information)
Si82 = ISOdriver product series
C = Input configuration
2 = Opto input type
I = Peak output current
0 = 2.5 A; 1 = 0.5 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1 = kV; B = 2.5 = kV; C = 3.75 kV
D = 5.0 kV
Line 2 Marking:
TTTTTT
Manufacturing date code assigned by assembly contractor.
Line 3 Marking:
Circle = 1.1 mm Diameter
Left-Justified
"e4" Pb-Free Symbol
Rev. 1.2
29
Si8220/21
DOCUMENT CHANGE LIST
Revision 0.22 to Revision 1.0
Updated Tables 2, 3, 4, and 5.
Updated “9. Ordering Guide” .
Added Device Marking sections.
Revision 1.0 to Revision 1.1
Updated Table 5 on page 10.
Updated Table 8 on page 12.
Removed introductory text and Figure 17.
Changed all packages to MSL2A in
"9.Ordering Guide" on page 22.
Updated "12.Package Outline: 16-Pin Wide Body
SOIC" on page 25.
Revision 1.1 to Revision 1.2
30
Updated CMTI spec in Table 1 on page 4.
Updated Figure 1 on page 6.
Updated Figure 2 on page 6.
Added Figure 3 on page 7.
Updated Table 5 on page 10.
Added note to Table 14 on page 22.
Rev. 1.2
Si8220/21
NOTES:
Rev. 1.2
31
Si8220/21
CONTACT INFORMATION
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Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
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