Si823x 数据表
0.5 和 4.0 安培 ISOdriver（2.5 和 5 kVRMS）
Si823x 隔离驱动器系列将两个独立、隔离的驱动器集成到一个封装内。Si8230/1/3/4 是高侧/低侧驱
动器，而 Si8232/5/7/8 是双驱动器。可选峰值输出电流为 0.5 A (Si8230/1/2/7) 和 4.0 A
(Si8233/4/5/8) 的版本。所有驱动器的最大供电电压为 24 V。
Si823x 驱动器采用 Silicon Labs 自主研发的硅隔离技术，提供符合 UL1577 的 5 kVRMS 耐受电压以
及 45 ns 快速传送时间。驱动器输出可连接到相同或独立的地线进行接地，或者连接到正或负电压。
单个控制输入 (Si8230/2/3/5/7/8) 或 PWM 输入 (Si8231/4) 配置提供滞后大于 400 mV 的 TTL 级兼容
输入。高度的集成、低传送延时、较小的外形及其灵活性和成本效益性使 Si823x 系列非常适合
MOSFET/IGBT 门驱动器隔离应用。
可以为某些部件编号提供汽车级。这些产品制造过程中的所有步骤均遵循汽车专用流程，能够确保汽
车应用所需的稳健性和低缺陷率。
工业应用
• 供电系统
• 电机控制系统
• 直流到直流隔离供电
• 照明控制系统
• 等离子显示器
• 太阳能和工业变换器
安全法规认证
• UL 1577 认证
• 1 分钟内最大 5000 VRMS
• CSA component notice 5A 认证
• IEC 60950-1、62368-1、60601-1（强化绝
缘）
• VDE 认证合规
• VDE 0884-10
• EN60950-1（强化绝缘）
• CQC 认证
• GB4943.1
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汽车应用
• 车载充电器
• 电池管理系统
• 充电站
• 牵引逆变器
• 混合动力汽车
• 电池动力汽车
主要特点
• 两个完全隔离的驱动器集成在一个封装内
• 最高 5 kVRMS 输入到输出隔离
• 驱动器到驱动器差分电压峰值为 1500
VDC
• HS/LS 和双驱动器版本
• 最高 8 MHz 切换频率
• 0.5 A 峰值输出 (Si8230/1/2/7)
• 4.0 A 峰值输出 (Si8233/4/5/8)
• 高电磁抗扰度
• 符合 RoHS 的封装：
• SOIC-14/16 宽体
• SOIC-16 窄体
• LGA-14
• QFN-14（与 LGA-14 封装引脚兼容）
• AEC-Q100 认证
• 可提供汽车级 OPN
• 符合 AIAG 要求的 PPAP 文件支持
• IMDS 及 CAMDS 列表支持
Rev. 2.14
Si823x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si823x Ordering Guide 1, 2, 3
Legacy
Ordering Part
Number (OPN)
Inputs
Configuration
Peak
Current
UVLO
Voltage
Isolation
Rating
Temp Range
Package Type
Ordering
Part Number
(OPN)
2.5 kV Only
Wide Body (WB) Package Options
Si8230BB-D-IS
VIA, VIB
High Side/
Low Side
Si8231BB-D-IS
PWM
High Side/
Low Side
Si8232BB-D-IS
VIA,VIB
Dual Driver
Si8234CB-D-IS
PWM
High Side/
Low Side
Si8233BB-D-IS
VIA,VIB
High Side/
Low Side
Si8234BB-D-IS
PWM
High Side/
Low Side
Si8235BB-D-IS
VIA,VIB
Dual Driver
Si8235-B-IS
Si8230AB-D-IS
VIA, VIB
N/A
Si8231AB-D-IS
PWM
High Side/
Low Side
Si8232AB-D-IS
VIA,VIB
Dual Driver
Si8233AB-D-IS
VIA,VIB
Si8234AB-D-IS
PWM
High Side/
Low Side
Si8235AB-D-IS
VIA,VIB
Dual Driver
Si8230-A-IS
0.5 A
8V
Si8231-A-IS
Si8232-A-IS
10 V
2.5 kVrms
–40 to +125 °C
SOIC-16
Wide Body
Si8233-B-IS
4.0 A
8V
0.5 A
Si8234-B-IS
5V
N/A
2.5 kVrms
4.0 A
N/A
–40 to +125 °C
SOIC-16
Wide Body
5V
N/A
N/A
N/A
N/A
Narrow Body (NB) Package Options
Si8230BB-D-IS1
VIA,VIB
High Side/
Low Side
Si8231BB-D-IS1
PWM
High Side/
Low Side
Si8232BB-D-IS1
VIA,VIB
Dual Driver
Si8233BB-D-IS1
VIA,VIB
High Side/
Low Side
Si8234BB-D-IS1
PWM
High Side/
Low Side
Si8235BB-D-IS1
VIA,VIB
Dual Driver
Si8235BA-D-IS1
VIA,VIB
Dual Driver
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0.5 A
8V
2.5 kVrms
4.0 A
–40 to +125 °C
SOIC-16
Narrow Body
N/A
8V
1.0 kVrms
Rev. 2.14 | 2
Si823x Data Sheet
Ordering Guide
Legacy
Ordering Part
Number (OPN)
Inputs
Configuration
Si8230AB-D-IS1
VIA,VIB
Si8231AB-D-IS1
PWM
High Side/
Low Side
Si8232AB-D-IS1
VIA,VIB
Dual Driver
Si8233AB-D-IS1
VIA,VIB
Si8234AB-D-IS1
PWM
High Side/
Low Side
Si8235AB-D-IS1
VIA,VIB
Dual Driver
Peak
Current
UVLO
Voltage
Isolation
Rating
Temp Range
Package Type
Ordering
Part Number
(OPN)
2.5 kV Only
N/A
0.5 A
5V
N/A
2.5 kVrms
4.0 A
–40 to +125 °C
SOIC-16
Narrow Body
5V
N/A
N/A
N/A
N/A
LGA Package Options
Si8233CB-D-IM
Si8233BB-D-IM
VIA,VIB
High Side/
Low Side
Si8233AB-D-IM
Si8234BB-D-IM
Si8234AB-D-IM
Si8235BB-D-IM
Si8235AB-D-IM
VIA,VIB
N/A
8V
Si8233-B-IM
5V
4.0 A
PWM
10 V
Dual Driver
8V
N/A
2.5 kVrms
–40 to +125 °C
LGA-14 5x5
mm
Si8234-B-IM
5V
N/A
8V
Si8235-B-IM
5V
N/A
5V
N/A
8V
N/A
QFN Package Options
SI8233AB-D-IM1
SI8233BB-D-IM1
SI8234AB-D-IM1
SI8234BB-D-IM1
SI8235AB-D-IM1
SI8235BB-D-IM1
VIA,VIB
High Side/
Low Side
PWM
VIA,VIB
4.0 A
Dual Driver
5V
8V
2.5 kVrms
–40 to +125 °C
QFN-14
N/A
N/A
5V
N/A
8V
N/A
5 kV Ordering Options
Si8230BD-D-IS
VIA, VIB
High Side/
Low Side
Si8231BD-D-IS
PWM
High Side/
Low Side
Si8232BD-D-IS
VIA, VIB
Dual Driver
Si8233BD-D-IS
VIA, VIB
High Side/
Low Side
Si8234BD-D-IS
PWM
High Side/
Low Side
Si8235BD-D-IS
VIA, VIB
Dual Driver
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0.5 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-16
Wide Body
N/A
4.0 A
Rev. 2.14 | 3
Si823x Data Sheet
Ordering Guide
Legacy
Ordering Part
Number (OPN)
Inputs
Configuration
Si8230AD-D-IS
VIA, VIB
Si8231AD-D-IS
PWM
High Side/
Low Side
Si8232AD-D-IS
VIA, VIB
Dual Driver
Si8233AD-D-IS
VIA, VIB
Si8234AD-D-IS
PWM
High Side/
Low Side
Si8235AD-D-IS
VIA, VIB
Dual Driver
SI8230AD-D-IS3
VIA, VIB
SI8230BD-D-IS3
VIA, VIB
High Side/
Low Side
SI8233AD-D-IS3
VIA, VIB
SI8233BD-D-IS3
VIA, VIB
SI8235AD-D-IS3
VIA, VIB
SI8235BD-D-IS3
VIA, VIB
Peak
Current
UVLO
Voltage
Isolation
Rating
Temp Range
Package Type
Ordering
Part Number
(OPN)
2.5 kV Only
N/A
0.5 A
5V
N/A
SOIC-16
Wide Body
4.0 A
5.0 kVrms
–40 to +125 °C
8V
4.0 A
N/A
SOIC-14 Wide
Body with
increased
5V
creepage
8V
Dual Driver
N/A
N/A
5V
0.5 A
N/A
N/A
N/A
N/A
N/A
5V
N/A
8V
N/A
3 V VDDI Ordering Options
Si8237AB-D-IS1
VIA, VIB
Dual Driver
Si8237BB-D-IS1
VIA, VIB
Dual Driver
Si8238AB-D-IS1
VIA, VIB
Dual Driver
Si8238BB-D-IS1
VIA, VIB
Dual Driver
Si8237AD-D-IS
VIA, VIB
Dual Driver
Si8237BD-D-IS
VIA, VIB
Dual Driver
Si8238AD-D-IS
VIA, VIB
Dual Driver
5V
Si8238BD-D-IS
VIA, VIB
Dual Driver
8V
SI8238AD-D-IS3
VIA, VIB
Dual Driver
5V
SI8238BD-D-IS3
VIA, VIB
Dual Driver
0.5 A
4.0 A
0.5 A
4.0 A
5V
8V
5V
SOIC-16
Narrow Body
2.5 kVrms
8V
5V
8V
8V
–40 to +125 °C
SOIC-16
Wide Body
N/A
5.0 kVrms
SOIC-14 Wide
Body with
increased
creepage
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
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Rev. 2.14 | 4
Si823x Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass production steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part
Number (OPN)
Inputs
Configuration
Peak
Current
UVLO
Voltage
Isolation
Rating
VIA, VIB
High Side/Low Side
4.0 A
8V
2.5 kVrms
Temp Range
Package Type
–40 to +125 °C
Si8233BB-AS
SOIC-16 Wide
Body
Narrow Body (NB) Package Options
Si8230BB-AS1
VIA, VIB
High Side/Low Side
0.5 A
8V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
Si8233BB-AS1
VIA, VIB
High Side/Low Side
4.0 A
8V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
Si8235BB-AS1
VIA, VIB
High Side/Low Side
4.0 A
8V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
Si8233AB-AS1
VIA, VIB
High Side/Low Side
4.0 A
5V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
VIA, VIB
High Side/Low Side
4.0 A
8V
2.5 kVrms
–40 to +125 °C
LGA-14
LGA Package Option
Si8233BB-AM
5x5 mm
Si8234BB-AM
PWM
High Side/Low Side
4.0 A
8V
2.5 kVrms
–40 to +125 °C
LGA-14
5x5 mm
Si8235BB-AM
VIA, VIB
Dual Driver
4.0 A
8V
2.5 kVrms
–40 to +125 °C
LGA-14
5x5 mm
5 kV Ordering Options
Si8230BD-AS
VIA, VIB
High Side/Low Side
0.5 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-16 Wide
Body
Si8233BD-AS
VIA, VIB
High Side/Low Side
4.0 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-16 Wide
Body
Si8235BD-AS
VIA, VIB
Dual Driver
4.0 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-16 Wide
Body
Si8235BD-AS3
VIA, VIB
Dual Driver
4.0 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-14 Wide
Body with increased creepage
3 V VDDI Ordering Options
Si8237BB-AS1
VIA, VIB
Dual Driver
0.5 A
8V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
Si8238BB-AS1
VIA, VIB
Dual Driver
4.0 A
8V
2.5 kVrms
–40 to +125 °C
SOIC-16 Narrow
Body
Si8238BD-AS
VIA, VIB
Dual Driver
4.0 A
8V
5.0 kVrms
–40 to +125 °C
SOIC-16 Wide
Body
silabs.com | Building a more connected world.
Rev. 2.14 | 5
Si823x Data Sheet
Ordering Guide
Ordering Part
Number (OPN)
Inputs
Configuration
Peak
Current
UVLO
Voltage
Isolation
Rating
Temp Range
Package Type
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales representative for further information.
6. In Section 8. Top Markings, the Manufacturing Code represented by either “RTTTTT” or “TTTTTT” contains as its first character a
letter in the range N through Z to indicate Automotive-Grade.”
silabs.com | Building a more connected world.
Rev. 2.14 | 6
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Top Level Block Diagrams .
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2.2 Functional Description
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.11
2.3 Typical Operating Characteristics (0.5 Amp) .
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2.4 Typical Operating Characteristics (4.0 Amp) .
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.15
2.5 Family Overview and Logic Operation During Startup .
2.5.1 Products . . . . . . . . . . . . . .
2.5.2 Device Behavior . . . . . . . . . . . .
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.17
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2.6 Power Supply Connections .
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.19
2.7 Power Dissipation Considerations
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.19
2.8 Layout Considerations .
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.21
2.9 Undervoltage Lockout Operation .
2.9.1 Device Startup . . . . .
2.9.2 Undervoltage Lockout . . .
2.9.3 Undervoltage Lockout (UVLO)
2.9.4 Control Inputs . . . . . .
2.9.5 Disable Input . . . . . .
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.22
2.10 Programmable Dead Time and Overlap Protection
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.23
3. Electrical Specifications
3.1 Test Circuits .
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.28
4. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
4.1 High-Side/Low-Side Driver .
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.34
4.2 Dual Driver .
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.35
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5. Pin Descriptions
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6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
6.1 Package Outline: 16-Pin Wide Body SOIC.
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.42
6.2 Package Outline: 14-Pin Wide Body SOIC.
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6.3 Package Outline: 16-Pin Narrow Body SOIC .
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6.4 Package Outline: 14 LD LGA (5 x 5 mm) .
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.47
6.5 Package Outline: 14 LD QFN .
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7. Land Patterns
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7.1 Land Pattern: 16-Pin Wide Body SOIC .
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7.2 Land Pattern: 14-Pin Wide Body SOIC .
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7.3 Land Pattern: 16-Pin Narrow Body SOIC .
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7.4 Land Pattern: 14 LD LGA/QFN
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.52
silabs.com | Building a more connected world.
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Rev. 2.14 | 7
8. Top Markings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC) .
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8.2 Si823x Top Marking (16-Pin Narrow Body SOIC)
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8.3 Si823x Top Marking (14 LD LGA/QFN) .
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9. Revision History
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Rev. 2.14 | 8
Si823x Data Sheet
System Overview
2. System Overview
2.1 Top Level Block Diagrams
VDDI
VDDA
I S OL ATION
VIA
VOA
UVLO
GNDA
DT CONTROL &
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
UVLO
DISABLE
I S OL ATION
VDDI
VOB
UVLO
GNDB
VIB
GNDI
Si8230/3
Figure 2.1. Si8230/3 Two-Input High-Side/Low-Side Isolated Drivers
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Rev. 2.14 | 9
Si823x Data Sheet
System Overview
VDDI
VDDA
I S OL ATION
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
I S OL ATION
VDDI
UVLO
DISABLE
VOB
UVLO
GNDB
LPWM
GNDI
Si8231/4
Figure 2.2. Si8231/4 Single-Input High-Side/Low-Side Isolated Drivers
VDDI
I S OL ATION
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
DISABLE
VDDI
VDDB
I S OL ATION
UVLO
VOB
UVLO
GNDB
VIB
GNDI
Si8232/5/7/8
Figure 2.3. Si8232/5/7/8 Dual Isolated Drivers
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Rev. 2.14 | 10
Si823x Data Sheet
System Overview
2.2 Functional Description
The operation of an Si823x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of
light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A
simplified block diagram for a single Si823x channel is shown in the figure below.
Transmitter
Receiver
Driver
RF OSCILLATOR
VDD
A
Dead
time
control
MODULATOR
SemiconductorBased Isolation
Barrier
B
DEMODULATOR
0.5 to 4 A
peak
Gnd
Figure 2.4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.5. Modulation Scheme
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Si823x Data Sheet
System Overview
2.3 Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figure 2.6 Rise/Fall Time vs. Supply Voltage on page 12 through Figure
2.15 Output Source Current vs. Temperature on page 13 are for information purposes only. Refer to Table 3.1 Electrical Characteristics1 on page 25 for actual specification limits.
30
10
8
Propagation Delay (ns)
Rise/Fall Time (ns)
25
Tfall
6
4
Trise
H-L
20
L-H
15
2
25 °C
CL = 100 pF
25 °C
CL = 100 pF
0
10
9
12
15
18
VDDA Supply (V)
21
24
Figure 2.6. Rise/Fall Time vs. Supply Voltage
9
12
15
18
VDDA Supply (V)
21
24
Figure 2.7. Propagation Delay vs. Supply Voltage
50
40
45
35
Trise
40
Propagation Delay (ns)
Rise/Fall Time (ns)
30
25
Tfall
20
15
10
L- H
35
30
H-L
25
20
15
5
VDD=12 V, 25 °C
VDD=12 V, 25°C
10
0
0.0
0.5
1.0
Load (nF)
1.5
Figure 2.8. Rise/Fall Time vs. Load
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2.0
0.0
0.5
1.0
Load (nF)
1.5
2.0
Figure 2.9. Propagation Delay vs. Load
Rev. 2.14 | 12
Si823x Data Sheet
System Overview
30
5
4
Supply Current (mA)
Propagation Delay (ns)
25
L-H
20
H-L
3
VDDA = 15 V,
f = 250 kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
2
15
VDD=12 V, Load = 200 pF
10
-45
-20
5
30
55
Temperature (°C)
80
105
1
130
Figure 2.10. Propagation Delay vs. Temperature
3.5
6
105
130
1 MHz
5
500 kHz
2
30
55
80
Temperature (° C)
Duty Cycle = 50%
C L = 100 pF
1 Channel Switching
1 MHz
2.5
5
Figure 2.11. Supply Current vs. Temperature
VDDA Supply Current (mA)
VDDA Supply Current (mA)
-20
7
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
3
-45
100 kHz
1.5
50 kHz
1
4
500 kHz
3
100 kHz
2
50 kHz
1
0.5
0
0
9
14
19
9
24
14
19
24
VDDA Supply Voltage (V)
VDDA Supply Voltage (V)
Figure 2.12. Supply Current vs. Supply Voltage
Figure 2.13. Supply Current vs. Supply Voltage
500
425
400
450
Source Current (mA)
Source Current (mA)
375
400
350
350
325
300
300
VDD=12 V, Vout=VDD -5 V
275
Vout=VDD -5 V
250
250
9
14
19
Supply Voltage (V)
24
Figure 2.14. Output Source Current vs. Supply Voltage
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-45
-20
5
30
55
Temperature (°C)
80
105
130
Figure 2.15. Output Source Current vs. Temperature
Rev. 2.14 | 13
Si823x Data Sheet
System Overview
1125
900
1000
Sink Current (mA)
Sink Current (mA)
800
875
750
700
600
VDD=12 V, Vout=5 V
625
Vout=5 V
500
500
9
14
19
24
Supply Voltage (V)
Figure 2.16. Output Sink Current vs. Supply Voltage
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-45
-20
5
30
55
Temperature (°C)
80
105
130
Figure 2.17. Output Sink Current vs. Temperature
Rev. 2.14 | 14
Si823x Data Sheet
System Overview
2.4 Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figure 2.18 Rise/Fall Time vs. Supply Voltage on page 15 through Figure
2.27 Output Source Current vs. Temperature on page 16 are for information purposes only. Refer to Table 3.1 Electrical Characteristics1 on page 25 for actual specification limits.
10
30
25° C
CL = 100 pF
25°C
CL= 100 pF
Propagation Delay (ns)
Rise/Fall Time (ns)
8
Tfall
6
Trise
4
25
L- H
20
H -L
15
2
0
10
9
12
15
18
21
24
9
12
15
VDDA Supply (V)
Figure 2.18. Rise/Fall Time vs. Supply Voltage
21
24
Figure 2.19. Propagation Delay vs. Supply Voltage
50
40
VDD=12V,
25°C
VDD=12V
, 25 °C
H-L
40
Propagation Delay (ns)
30
Rise/Fall Time (ns)
18
VDDA Supply (V)
Trise
Tfall
20
10
L-H
30
20
0
10
0
2
4
6
8
Load (nF)
Figure 2.20. Rise/Fall Time vs. Load
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10
0
2
4
6
8
10
Load (nF)
Figure 2.21. Propagation Delay vs. Load
Rev. 2.14 | 15
Si823x Data Sheet
System Overview
30
10
VDDA = 15V,
f = 250kHz,CL= 0 pF
Duty Cycle = 50%
2 Channels Switching
VDD=12V,
Load = 200pF
Supply Current (mA)
Propagation Delay (ns)
8
25
H-L
L-H
20
15
6
4
2
0
10
-45
-45
-20
5
30
55
80
105
-20
5
Temperature ( ° C)
80
105
130
Figure 2.23. Supply Current vs. Temperature
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
14
12
VDDA Supply Current (mA)
VDDA Supply Current (mA)
55
Temperature ( °C)
Figure 2.22. Propagation Delay vs. Temperature
14
30
130
1MHz
10
8
500kHz
6
1MHz
12
10
8
500kHz
6
4
4
100kHz
100kHz
2
2
50 kHz
50 kHz
0
0
9
12
15
18
21
9
24
12
15
VDDA Supply Voltage (V)
18
21
24
VDDA Supply Voltage (V)
Figure 2.24. Supply Current vs. Supply Voltage
Figure 2.25. Supply Current vs. Supply Voltage
3.5
4
VDD=12V,
Vout=VDD - 5V
Vout=VDD -5V
3.75
3.25
Source Current (A)
Source Current (A)
3.5
3.25
3
2.75
3
2.75
2.5
2.5
2.25
2.25
2
9
12
15
18
21
24
Supply Voltage (V)
Figure 2.26. Output Source Current vs. Supply Voltage
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2
-45
-20
5
30
55
80
105
130
Temperature ( °C)
Figure 2.27. Output Source Current vs. Temperature
Rev. 2.14 | 16
Si823x Data Sheet
System Overview
7
9
VDD=12V,
Vout=5V
6.75
Vout=5V
6.5
8
Sink Current (A)
Sink Current (A)
6.25
7
6
6
5.75
5.5
5.25
5
4.75
5
4.5
4.25
4
9
12
15
18
21
24
4
-45
-20
5
30
55
80
105
130
Temperature (°C)
Supply Voltage (V)
Figure 2.28. Output Sink Current vs. Supply Voltage
Figure 2.29. Output Sink Current vs. Temperature
2.5 Family Overview and Logic Operation During Startup
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
2.5.1 Products
The table below shows the configuration and functional overview for each product in this family.
Table 2.1. Si823x Family Overview
Part Number
Configuration
Overlap Protection
Programmable
Dead Time
Inputs
Peak Output Current (A)
Si8230
High-Side/Low-Side
√
√
VIA, VIB
0.5
Si8231
High-Side/Low-Side
√
√
PWM
0.5
Dual Driver
—
—
VIA, VIB
0.5
Si8233
High-Side/Low-Side
√
√
VIA, VIB
4.0
Si8234
High-Side/Low-Side
√
√
PWM
4.0
Dual Driver
—
—
VIA, VIB
4.0
Si8232/7
Si8235/8
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Si823x Data Sheet
System Overview
2.5.2 Device Behavior
The table below consists of truth tables for the Si8230/3, Si8231/4, and Si8232/5/7/8 families.
Table 2.2. Si823x Family Truth Table1
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs
VDDI State
VIA
VIB
L
L
Powered
L
H
H
Disable
Output
Notes
VOA
VOB
L
L
L
Output transition occurs after internal dead time expires.
Powered
L
L
H
Output transition occurs after internal dead time expires.
L
Powered
L
H
L
Output transition occurs after internal dead time expires.
H
H
Powered
L
L
L
Invalid state. Output transition occurs after internal dead
time expires.
X2
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
X
Powered
H
L
L
Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
PWM Input
VDDI State
Disable
Output
Notes
VOA
VOB
H
Powered
L
H
L
Output transition occurs after internal dead time expires.
L
Powered
L
L
H
Output transition occurs after internal dead time expires.
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
Powered
H
L
L
Device is disabled.
Si8232/5/7/8 (Dual Driver) Truth Table
Inputs
VDDI State
VIA
VIB
L
L
Powered
L
H
H
Disable
Output
Notes
VOA
VOB
L
L
L
Output transition occurs immediately
(no internal dead time).
Powered
L
L
H
Output transition occurs immediately
(no internal dead time).
L
Powered
L
H
L
Output transition occurs immediately
(no internal dead time).
H
H
Powered
L
H
H
Output transition occurs immediately
(no internal dead time).
X2
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
X
Powered
H
L
L
Device is disabled.
Notes:
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see 2.9 Undervoltage
Lockout Operation for more information.
2. Note that an input can power the input die through an internal diode if its source has adequate current.
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Rev. 2.14 | 18
Si823x Data Sheet
System Overview
2.6 Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be
placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for these capacitors depend on load current
and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,
are recommended.
2.7 Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.The Si823x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. Equation 1 shows total Si823x power dissipation.
( )( )( )
( )( )( )
RP
RN
PD = (VDDI)(IDDI) + 2(IDD2)(VDD2) + f QG VDD2
+ f QG VDD2
+ 2fCintVDD22
RP + RG
RN + RG
where:
PD is the total Si823x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IDD2 is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (2.7 to 5.5 V)
VDD2 is the driver-side supply voltage (10 to 24 V)
f is the switching frequency (Hz)
QG is the gate charge of the FET being driven
RG is the external gate resistor
RP is the RDS(ON) of the driver pull-up switch: (Rp = 15 Ω for the 0.5 A driver; Rp = 2.7 Ω for the 4.0 A driver)
RN is the RDS(ON) of the driver pull-down switch: (Rn = 5 Ω for the 0.5 A driver and 1 Ω for the 4.0 A driver)
Equation 1
Power dissipation example for 0.5 A driver using Equation 1 with the following givens:
VDD1 = 5.0 V
VDD2 = 12 V
f = 350 kHz
RG = 22 Ω
QG = 25 nC
( )( 5 +522 ) + (350 × 103)(25 × 10-9)(12)( 1515+ 22 )
Pd = 0.015 + 0.060 + (350 × 103)(25 × 10-9) 12
+2 (350 × 103)(75 × 10−12)(144) = 145 mW
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Si823x Data Sheet
System Overview
From which the driver junction temperature is calculated using Equation 2, where:
Pd is the total Si823x device power dissipation (W)
θja is the thermal resistance from junction to air (105 °C/W in this example)
TA is the ambient temperature
T j = Pd × Θ ja × T A = (0.145)(105) + 20 = 35.2 ° C
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient temperature, and
maximum allowable junction temperature, as shown in Equation 2:
PDmax ≤
Tjmax − TA
Θja
where:
PDmax = Maximum Si823x power dissipation (W)
Tjmax = Si823x maximum junction temperature (150 °C)
TA = Ambient temperature (20 °C)
Θja = Si823x junction-to-air thermal resistance (105 °C/W)
Equation 2
Substituting values for PDmax Tjmax, TA, and θja into Equation 2 results in a maximum allowable total power dissipation of 1.29 W. Maximum allowable load is found by substituting this limit and the appropriate data sheet values from Table 3.1 Electrical Characteristics1
on page 25 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
QG(MAX) =
0.164
− 3.05 × 10−9
f
Equation 3
QG(MAX) =
0.634
− 5.81 × 10−9
f
Equation 4
Equation 3 and Equation 4 are graphed in the figure below, where the points along the load line represent the package dissipationlimited value of CL for the corresponding switching frequency.
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Rev. 2.14 | 20
Si823x Data Sheet
System Overview
2.8 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si823x as close to the device it is driving as possible. In addition, the VDD supply and ground
trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise performance.
2.9 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.30 Device Behavior during Normal Operation and
Shutdown on page 22, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Note that outputs
VOA and VOB default low when input side power supply (VDDI) is not present.
2.9.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
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Rev. 2.14 | 21
Si823x Data Sheet
System Overview
2.9.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB,
remain low when the input side of the Si823x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each
driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV–
and exits UVLO when VDDA rises above VDDAUV+.
UVLO+
UVLO-
VDDHYS
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
VIA
DISABLE
tSTART
tSD
tSTART
tSTART
tSD
tRESTART
tPHL
tPLH
VOA
Figure 2.30. Device Behavior during Normal Operation and Shutdown
2.9.3 Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Upon power up, the Si823x is maintained in
UVLO until VDD rises above VDDUV+. During power down, the Si823x enters UVLO when VDD falls below the UVLO threshold plus
hysteresis (i.e., VDD < VDDUV+ – VDDHYS).
2.9.4 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.9.5 Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation terminates within tSD after DISABLE =VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if
VDDI is below its UVLO level (i.e., VOA, VOB remain low).
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Rev. 2.14 | 22
Si823x Data Sheet
System Overview
2.10 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and VOB from being high
at the same time. These devices also include programmable dead time, which adds a user-programmable delay between transitions of
VOA and VOB. When enabled, dead time is present on all transitions, even after overlap recovery. The amount of dead time delay (DT)
is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be
tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
DT ≈ 10 × RDT
where:
DT = dead time (ns) and
RDT = dead time programing resistor (kΩ)
Equation 5
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection. Input/output timing
waveforms for the two-input drivers are shown in Figure 2.31 Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers on
page 23, and dead time waveforms are shown in Figure 2.32 Dead Time Waveforms for High-Side / Low-Side Two-input Drivers on
page 24.
Figure 2.31. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
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Rev. 2.14 | 23
Si823x Data Sheet
System Overview
OVERLAP
OVERLAP
VOB
VIA/
PWM
VIB
50%
VIB
VIA/
PWM
DT
DT
DT
DT
90%
VOA
VOA
10%
90%
DT
DT
VOB
10%
A. Typical Dead Time Operation
VOB
B. Dead Time Operation During Overlap
Figure 2.32. Dead Time Waveforms for High-Side / Low-Side Two-input Drivers
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Rev. 2.14 | 24
Si823x Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. Electrical Characteristics1
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V, TA = –40 to +125 °C, Typical specs at 25 °C, TJ = -40 to +150 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDDI
Si8230/1/2/3/4/5
4.5
—
5.5
V
Si8237/8
2.7
—
5.5
VDDA, VDDB
Voltage between VDDA and
GNDA, and VDDB and GNDB
(See 1. Ordering Guide)
6.5
—
24
V
IDDI(Q)
Si8230/2/3/5/7/8
—
2
3
mA
Si8231/4
—
3.5
5
mA
IDDA(Q), IDDB(Q)
Current per channel
—
—
3.0
mA
Input Supply Active Current
IDDI
Input freq = 500 kHz, no load
—
3.5
—
mA
Output Supply Active Current
IDDA
Current per channel with
—
6
—
mA
IDDB
Input freq = 500 kHz, no load
DC Specifications
Input-side Power Supply
Voltage
Driver Supply Voltage
Input Supply Quiescent
Current
Output Supply Quiescent
Current
Input Pin Leakage Current
IVIA, IVIB, IPWM
–10
—
+10
µA dc
Input Pin Leakage Current
(Si8230/1/2/3/4/5)
IDISABLE
–10
—
+10
µA dc
-1000
—
+1000
Input Pin Leakage Current
(Si8237/8)
Logic High Input Threshold
VIH
2.0
—
—
V
Logic Low Input Threshold
VIL
—
—
0.8
V
Input Hysteresis
VIHYST
Si8230/1/2/3/4/5/7/8
400
450
—
mV
Logic High Output Voltage
VOAH, VOBH
IOA, IOB = –1 mA
(VDDA /
VDDB)
— 0.04
—
—
V
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
—
—
0.04
V
IOA(SCL), IOB(SCL)
Si8230/1/2/7, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
—
0.5
—
A
Si8233/4/5/8, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
—
4.0
—
A
Si8230/1/2/7, Figure 3.2 IOH
Source Current Test Circuit on
page 28
—
0.25
—
A
Si8233/4/5/8, Figure 3.2 IOH
Source Current Test Circuit on
page 28
—
2.0
—
A
Output Short-Circuit Pulsed
Sink Current
Output Short-Circuit Pulsed
Source Current
IOA(SCH),
IOB(SCH)
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Rev. 2.14 | 25
Si823x Data Sheet
Electrical Specifications
Parameter
Output Sink Resistance
Output Source Resistance
Symbol
Test Condition
Min
Typ
Max
Unit
RON(SINK)
Si8230/1/2/7
—
5.0
—
Ω
Si8233/4/5/8
—
1.0
—
Ω
Si8230/1/2/7
—
15
—
Ω
Si8233/4/5/8
—
2.7
—
Ω
RON(SOURCE)
VDDI Undervoltage Threshold
VDDIUV+
VDDI rising (Si8230/1/2/3/4/5)
3.60
4.0
4.45
V
VDDI Undervoltage Threshold
VDDIUV–
VDDI falling
3.30
3.70
4.15
V
(Si8230/1/2/3/4/5)
VDDI Lockout Hysteresis
VDDIHYS
(Si8230/1/2/3/4/5)
—
250
—
mV
VDDI Undervoltage Threshold
VDDIUV+
VDDI rising (Si8237/8)
2.15
2.3
2.5
V
VDDI Undervoltage Threshold
VDDIUV–
VDDI falling (Si8237/8)
2.10
2.22
2.40
V
VDDI Lockout Hysteresis
VDDIHYS
(Si8237/8)
—
75
—
mV
VDDAUV+, VDDBUV+
VDDA, VDDB rising
5 V Threshold
5.20
5.80
6.30
V
8 V Threshold
7.50
8.60
9.40
V
10 V Threshold
9.60
11.1
12.2
V
12.5 V Threshold
12.4
13.8
14.8
V
5 V Threshold
4.90
5.52
6.0
V
8 V Threshold
7.20
8.10
8.70
V
10 V Threshold
9.40
10.1
10.9
V
12.5 V Threshold
11.6
12.8
13.8
V
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB Undervoltage
Threshold
VDDAUV–, VDDBUV–
VDDA, VDDB falling
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 5 V
—
280
—
mV
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 8 V
—
600
—
mV
VDDA, VDDB
Lockout Hysteresis
VDDAHYS,
VDDBHYS
UVLO voltage = 10 V or 12.5 V
—
1000
—
mV
—
10
—
ns
—
30
45
ns
—
—
5.60
ns
—
0.4
—
ns
AC Specifications
Minimum Pulse Width
Propagation Delay
tPHL, tPLH
Pulse Width Distortion
|tPLH - tPHL|
PWD
Minimum Overlap Time2
TDD
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CL = 200 pF
DT = VDDI, No-Connect
Rev. 2.14 | 26
Si823x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DT
Figure 2.32 Dead Time Waveforms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 100 k
730
900
1170
ns
Figure 2.32 Dead Time Waveforms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 6 k
55
70
75
ns
CL = 200 pF (Si8230/1/2/7)
—
—
20
ns
CL = 200 pF (Si8233/4/5/8)
—
—
12
ns
tSD
—
—
60
ns
tRESTART
—
—
60
ns
Programmed Dead Time3
Output Rise and Fall Time
tR,tF
Shutdown Time from
Disable True
Restart Time from
Disable False
Device Start-up Time
tSTART
Time from VDD_ = VDD_UV+ to
VOA, VOB = VIA, VIB
—
—
40
µs
Common Mode
CMTI
VIA, VIB, PWM = VDDI or 0 V
20
45
—
kV/µs
Transient Immunity
VCM = 1500 V
(see Figure 3.3 Common Mode
Transient Immunity Test Circuit
on page 29)
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 kΩ.
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Rev. 2.14 | 27
Si823x Data Sheet
Electrical Specifications
3.1 Test Circuits
Figures Figure 3.1 IOL Sink Current Test Circuit on page 28, Figure 3.2 IOH Source Current Test Circuit on page 28, and Figure
3.3 Common Mode Transient Immunity Test Circuit on page 29 depict sink current, source current, and common-mode transient immunity test circuits, respectively.
VDDA = VDDB = 15 V
VDDI
VDD
IN
INPUT
Si823x
10
OUT
SCHOTTKY
VSS
1 µF
1 µF
CER
Measure
100 µF
8V
+
_
10 µF
EL
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 3.1. IOL Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
VDD
IN
INPUT
Si823x
10
OUT
SCHOTTKY
VSS
1 µF
1 µF
CER
Measure
100 µF
5.5 V
+
_
10 µF
EL
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 3.2. IOH Source Current Test Circuit
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Rev. 2.14 | 28
Si823x Data Sheet
Electrical Specifications
12 V
Supply
Si823x
Input Signal
Switch
5V
Isolated
Supply
VDDI
VDDA
INPUT
VOA
DISABLE
DT
GNDA
VDDB
Oscilloscope
VOB
100k
GNDI
GNDB
Isolated
Ground
Input
High Voltage
Differential
Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3.3. Common Mode Transient Immunity Test Circuit
Table 3.2. Regulatory Information1
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si823x is certified according to VDE 0884-10 and EN 60950-1. For more details, see certificates 40018443, 40030763.
0884-10: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si823x is certified under GB4943.1-2011. For more details, see certificates CQC13001096106, CQC13001096108, and CQC
17001178087.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
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Rev. 2.14 | 29
Si823x Data Sheet
Electrical Specifications
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
Table 3.3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WBSOIC-14/16
5 kVRMS
WBSOIC-14/16
NBSOIC-16
2.5 kVRMS
14 LD LGA
/QFN
2.5 kVRMS
Nominal External Air
Gap
(Clearance)1
CLR
8.0
8.0/4.01
3.5
mm
Nominal External Tracking (Creepage)1
CPG
8.0
8.0/4.01
3.5
mm
Minimum Internal Gap
DTI
0.014
0.014
0.014
mm
600
600
600
V
(Internal Clearance)
Tracking Resistance
CTI or PTI
IEC60112
Erosion Depth
ED
0.019/0.122
0.019/0.122
0.021
mm
Resistance
(Input-Output)2
RIO
1012
1012
1012
Ω
Capacitance
(Input-Output)2
CIO
1.4
1.4
1.4
pF
4.0
4.0
4.0
pF
Input Capacitance3
CI
f = 1 ΜΗz
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in 6.1 Package Outline: 16-Pin
Wide Body SOIC, 6.2 Package Outline: 14-Pin Wide Body SOIC, 6.3 Package Outline: 16-Pin Narrow Body SOIC, 6.4 Package
Outline: 14 LD LGA (5 x 5 mm), 6.5 Package Outline: 14 LD QFN. VDE certifies the clearance and creepage limits as 4.7 mm
minimum for the NB SOIC and 8.5 mm minimum for the WB SOIC package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage of the WB SOIC package with designation
"IS3" as 8 mm minimum. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC and 7.6 mm minimum for the WB SOIC package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1–7, 14 LD LGA/QFN) are
shorted together to form the first terminal and pins 9–16 (8–14, 14 LD LGA/QFN) are shorted together to form the second terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
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Rev. 2.14 | 30
Si823x Data Sheet
Electrical Specifications
Table 3.4. IEC 60664-1 Ratings
Parameter
Test Condition
Specification
WB SOIC-14/16
NB SOIC-16
14 LD
LGA/QFN
Basic Isolation Group
Material Group
I
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-IV
I-III
I-III
Rated Mains Voltages < 400 VRMS
I-III
I-II
I-II
Rated Mains Voltages < 600 VRMS
I-III
I-II
I-II
Table 3.5. VDE 0884-10 Insulation Characteristics1
Characteristic
Parameter
Symbol
Maximum Working Insulation Voltage
VIORM
Test Condition
Input to Output Test Voltage
VPR
Method b1
(VIORM x 1.875 = VPR,
100%
Production Test, tm = 1
sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 s
Surge Voltage
VIOSM
Insulation Resistance at
TS, VIO = 500 V
RS
NB SOIC-16
14 LD LGA/QFN
Unit
891
560
V peak
1671
1050
V peak
6000
4000
V peak
3077
3077
V peak
2
2
>109
>109
Tested per IEC 60065 with
surge voltage of 1.2 µs/50
µs
Si823xxB/C/D tested with
4000 V
Pollution Degree (DIN VDE
0110, Table 1)
WB
SOIC-14/16
Ω
*Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of 40/125/21.
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Rev. 2.14 | 31
Si823x Data Sheet
Electrical Specifications
Table 3.6. VDE 0884-10 Safety Limiting Values1
Parameter
Symbol
Test
WB SOIC-14/16
NB SOIC-16
14 LD
LGA/QFN
Unit
150
150
150
°C
50
50
50
mA
1.2
1.2
1.2
W
Condition
Case
Temperature
TS
Safety Input Current
ΙS
θJA = 100 °C/W (WB SOIC-14/16),
105 °C/W (NB SOIC-16,
14 LD LGA/QFN)
VDDI = 5.5 V,
VDDA = VDDB = 24 V,
TJ = 150 °C, TA = 25 °C
Device Power Dissipation2
PD
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures Figure 3.4 WB SOIC, NB SOIC,
14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on
page 32.
2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave.
Table 3.7. Thermal Characteristics
Parameter
Symbol
WB
SOIC-14/16
NB
SOIC-16
14 LD LGA/QFN
Unit
θJA
100
105
105
°C/W
Safety-Limiting Current (mA)
IC Junction-to-Air
Thermal Resistance
60
50
VDDI = 5.5 V
VDDA, VDDB = 24 V
40
30
20
10
0
0
50
100
150
Case Temperature (ºC)
200
Figure 3.4. WB SOIC, NB SOIC, 14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per VDE 0884-10
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Rev. 2.14 | 32
Si823x Data Sheet
Electrical Specifications
Table 3.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
TSTG
–65
+150
°C
Ambient Temperature under Bias
TA
–40
+125
°C
Junction Temperature
TJ
—
+150
°C
Input-side Supply Voltage
VDDI
–0.6
6.0
V
Driver-side Supply Voltage
VDDA, VDDB
–0.6
30
V
Voltage on any Pin with respect to
Ground
VIO
–0.5
VDD + 0.5
V
Output voltage to GND, repeat
spike of –2 V for 200 ns, 200 kHz
VOA to GNDA,
VOB to GNDB
–2
VDDA/B + 0.5
V
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
IOPK
—
0.5
A
IOPK
—
4.0
A
Lead Solder Temperature (10 s)
—
260
°C
Maximum Isolation (Input to Output) (1 s)
WB SOIC
—
6500
VRMS
Maximum Isolation (Output to Output) (1 s)
WB SOIC
—
2500
VRMS
Maximum Isolation (Input to Output) (1 s)
NB SOIC
—
4500
VRMS
Maximum Isolation (Output to Output) (1 s)
NB SOIC
—
2500
VRMS
Maximum Isolation (Input to Output) (1 s)
14 LD LGA/QFN
—
3850
VRMS
Maximum Isolation (Output to Output) (1 s)
14 LD LGA/QFN
—
650
VRMS
Storage Temperature2
(0.5 Amp versions)
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
(4.0 Amp versions)
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
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Rev. 2.14 | 33
Si823x Data Sheet
Applications
4. Applications
The following examples illustrate typical circuit configurations using the Si823x.
4.1 High-Side/Low-Side Driver
The Figure A in the drawing below shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure B shows the Si8231/4
controlled by a single PWM signal.
VDD2
C1
1 µF
C2
0.1 µF
VDD2
D1
C3
1µF
VDDI
VDDI
VDDI
1500 V max
GNDI
C1
1 µF
VDDA
C2
0.1 µF
VDDI
1500 V max
GNDI
VDDA
CB
OUT1
VIA
OUT2
VIB
CONTROLLER
PWM
PWMOUT
GNDA
DT
RDT
CB
Q1
VOA
GNDA
DT
Si8230/3
CONTROLLER
RDT
Si8231/4
VDDB
C4
0.1 µF
DISABLE
C4
0.1 µF
C5
10 µF
I/O
DISABLE
GNDB
VDDB
VOB
Q1
VOA
VDDB
I/O
D1
C3
1µF
Q2
A
C5
10 µF
GNDB
VOB
Q2
B
Figure 4.1. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a
maximum drain voltage of 1500 V. The boot-strap start up time will depend on the CB cap chosen. See application note, “AN486: HighSide Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems”. VOB is connected as a conventional low-side driver, and,
in most cases, VDD2 is the same as VDDB. Note that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V (2.7 to 5.5
V for Si8237/8), while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective
grounds. It is recommended that bypass capacitors of 0.1 and 1 µF value be used on the Si823x input side and that they be located as
close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors, located as close to the chip as possible, be used on the Si823x output side to reduce high-frequency noise and maximize performance.
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Rev. 2.14 | 34
Si823x Data Sheet
Applications
4.2 Dual Driver
The figure below shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a common ground or to different grounds with as much as 1500 V dc between them.
VDDI
C1
1 µF
C2
0.1 µF
VDDI
Q1
VOA
GNDI
PH1
VIA
PH2
VIB
VDDA
VDDA
GNDA
C3
0.1 µF
C4
10 µF
Si8232/5/7/8
CONTROLLER
VDDB
VDDB
DISABLE
I/O
GNDB
C5
0.1 µF
VOB
C6
10 µF
Q2
Figure 4.2. Si8232/5/7/8 in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual
driver in a low-side high side/low side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can
operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes.
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Rev. 2.14 | 35
Si823x Data Sheet
Pin Descriptions
5. Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
VIA
1
16
VDDA
VIA
1
16
VDDA
VIB
2
15
VOA
VIB
2
15
VOA
VDDI
3
14
GNDA
VDDI
3
14
GNDA
GNDI
4
13
NC
GNDI
4
13
NC
DISABLE
5
12
NC
DISABLE
5
12
NC
DT
6
11
VDDB
DT
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8230
Si8233
GNDB
Si8230
Si8233
GNDB
Table 5.1. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin
Name
1
VIA
Non-inverting logic input terminal for Driver A.
2
VIB
Non-inverting logic input terminal for Driver B.
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4
GNDI
Input-side ground terminal.
5
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9
GNDB
Ground terminal for Driver B.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
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Description
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 2.14 | 36
Si823x Data Sheet
Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
PWM
1
16
VDDA
NC
2
15
VOA
VDDI
3
14
GNDI
4
DISABLE
5
DT
PWM
1
16
VDDA
NC
2
15
VOA
GNDA
VDDI
3
14
GNDA
13
NC
GNDI
4
13
NC
12
NC
DISABLE
5
12
NC
6
11
VDDB
DT
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8231
Si8234
GNDB
Si8231
Si8234
GNDB
Table 5.2. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin
Name
Description
1
PWM
PWM input.
2
NC
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
4
GNDI
Input-side ground terminal.
5
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
9
GNDB
Ground terminal for Driver B.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
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No connection.
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 2.14 | 37
Si823x Data Sheet
Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
VIA
1
16
VDDA
VIA
1
16
VDDA
VIB
2
15
VOA
VIB
2
15
VOA
VDDI
3
14
GNDA
VDDI
3
14
GNDA
GNDI
4
13
NC
GNDI
4
13
NC
DISABLE
5
12
NC
DISABLE
5
12
NC
NC
6
11
VDDB
NC
6
11
VDDB
NC
7
10
VOB
NC
7
10
VOB
VDDI
8
9
VDDI
8
9
Si8232
Si8235
Si8237
Si8238
GNDB
Si8232
Si8235
Si8237
Si8238
GNDB
Table 5.3. Si8232/5/7/8 Dual Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13 missing
Pin
Name
1
VIA
Non-inverting logic input terminal for Driver A.
2
VIB
Non-inverting logic input terminal for Driver B.
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
4
GNDI
Input-side ground terminal.
5
DISABLE
6
NC
No connection.
7
NC
No connection.
8
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
9
GNDB
Ground terminal for Driver B.
10
VOB
11
VDDB
12
NC
No connection.
13
NC
No connection.
14
GNDA
15
VOA
16
VDDA
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Description
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
Driver B output.
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output.
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 2.14 | 38
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
1
14
VDDA
VIA
2
13
VOA
VIB
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
DT
6
9
VOB
VDDI
7
8
GNDB
Si8233
Table 5.4. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin
Name
GNDI
1
Input-side ground terminal.
VIA
2
Non-inverting logic input terminal for Driver A.
VIB
3
Non-inverting logic input terminal for Driver B.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Description
Rev. 2.14 | 39
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
1
14
VDDA
PWM
2
13
VOA
NC
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
DT
6
9
VOB
VDDI
7
8
GNDB
Si8234
Table 5.5. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin
Name
GNDI
1
Input-side ground terminal.
PWM
2
PWM input.
NC
3
No connection.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection). If improved noise immunity is desired, a 10 nF capacitor may be
added in parallel to the dead time programming resistor (RDT).
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Description
Rev. 2.14 | 40
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
GNDI
1
14
VDDA
VIA
2
13
VOA
VIB
3
12
GNDA
VDDI
4
11
NC
DISABLE
5
10
VDDB
NC
6
9
VOB
VDDI
7
8
GNDB
Si8235
Table 5.6. Si8235 Dual Isolated Driver (14 LD LGA and QFN)
Pin
Name
GNDI
1
Input-side ground terminal.
VIA
2
Non-inverting logic input terminal for Driver A.
VIB
3
Non-inverting logic input terminal for Driver B.
VDDI
4
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid erroneous operation due to capacitive noise coupling.
NC
6
No connection.
VDDI
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB
8
Ground terminal for Driver B.
VOB
9
Driver B output (low-side driver).
VDDB
10
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
11
No connection.
GNDA
12
Ground terminal for Driver A.
VOA
13
Driver A output (high-side driver).
VDDA
14
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Description
Rev. 2.14 | 41
Si823x Data Sheet
Package Outlines
6. Package Outlines
6.1 Package Outline: 16-Pin Wide Body SOIC
Figure 6.1 16-Pin Wide Body SOIC on page 42 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table
6.1 Package Diagram Dimensions on page 42 lists the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
Table 6.1. Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
θ
0°
8°
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Rev. 2.14 | 42
Si823x Data Sheet
Package Outlines
Dimension
Min
Max
ααα
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 2.14 | 43
Si823x Data Sheet
Package Outlines
6.2 Package Outline: 14-Pin Wide Body SOIC
Figure 6.2 Si823x 14-pin WB SOIC Outline on page 44 illustrates the package details for the Si823x in a 14-Pin Wide Body SOIC.
Table 6.2 Package Diagram Dimensions on page 44 lists the values for the dimensions shown in the illustration.
Figure 6.2. Si823x 14-pin WB SOIC Outline
Table 6.2. Package Diagram Dimensions
Dimension
MIN
MAX
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
10.30 BSC
E
10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
Θ
0ͦ
8ͦ
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
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Rev. 2.14 | 44
Si823x Data Sheet
Package Outlines
Dimension
MIN
MAX
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 2.14 | 45
Si823x Data Sheet
Package Outlines
6.3 Package Outline: 16-Pin Narrow Body SOIC
Figure 6.3 16-pin Small Outline Integrated Circuit (SOIC) Package on page 46 illustrates the package details for the Si823x in a 16pin narrow-body SOIC. Table 6.3 Package Diagram Dimensions on page 46 lists the values for the dimensions shown in the illustration.
Figure 6.3. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 6.3. Package Diagram Dimensions
Dimension
Min
Max
Dimension
Min
Max
A
—
1.75
L
0.40
1.27
A1
0.10
0.25
L2
0.25 BSC
A2
1.25
—
h
0.25
0.50
b
0.31
0.51
θ
0°
8°
c
0.17
0.25
aaa
0.10
D
9.90 BSC
bbb
0.20
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.25
e
1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 2.14 | 46
Si823x Data Sheet
Package Outlines
6.4 Package Outline: 14 LD LGA (5 x 5 mm)
Figure 6.4 Si823x LGA Outline on page 47 illustrates the package details for the Si823x in an LGA outline. Table 6.4 Package Diagram Dimensions on page 47 lists the values for the dimensions shown in the illustration.
Figure 6.4. Si823x LGA Outline
Table 6.4. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.84
0.94
b
0.25
0.30
0.35
D
5.00 BSC
D1
4.15 BSC
e
0.65 BSC
E
5.00 BSC
E1
3.90 BSC
L
0.70
0.75
0.80
L1
0.05
0.10
0.15
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.15
eee
—
—
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 2.14 | 47
Si823x Data Sheet
Package Outlines
6.5 Package Outline: 14 LD QFN
Figure 6.5 Si823x 14-pin LD QFN Outline on page 48 illustrates the package details for the Si823x in an QFN outline. Table
6.5 Package Diagram Dimensions on page 48 lists the values for the dimensions shown in the illustration.
Figure 6.5. Si823x 14-pin LD QFN Outline
Table 6.5. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.85
0.90
A1
0
0.025
0.05
b
0.25
0.30
0.35
D
5.00 BSC
e
0.65 BSC
E
5.00 BSC
E1
3.60 BSC
L
0.50
0.60
0.70
L13
—
0.10 BSC
—
ccc
—
—
0.08
ddd
—
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. L1 shall not be less than 0.01 mm.
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Rev. 2.14 | 48
Si823x Data Sheet
Land Patterns
7. Land Patterns
7.1 Land Pattern: 16-Pin Wide Body SOIC
Figure 7.1 16-Pin SOIC Land Pattern on page 49 illustrates the recommended land pattern details for the Si823x in a 16-pin widebody SOIC. Table 7.1 16-Pin Wide Body SOIC Land Pattern Dimensions on page 49 lists the values for the dimensions shown in the
illustration.
Figure 7.1. 16-Pin SOIC Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.14 | 49
Si823x Data Sheet
Land Patterns
7.2 Land Pattern: 14-Pin Wide Body SOIC
Figure 7.2 14-Pin WB SOIC Land Pattern on page 50 illustrates the recommended land pattern details for the Si823x in a 14-pin Wide
Body SOIC. Table 7.2 14-Pin WB SOIC Land Pattern Dimensions on page 50 lists the values for the dimensions shown in the
illustration.
Figure 7.2. 14-Pin WB SOIC Land Pattern
Table 7.2. 14-Pin WB SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
Pad Column Spacing
9.70
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.60
C1
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.14 | 50
Si823x Data Sheet
Land Patterns
7.3 Land Pattern: 16-Pin Narrow Body SOIC
Figure 7.3 16-Pin Narrow Body SOIC PCB Land Pattern on page 51 illustrates the recommended land pattern details for the Si823x in
a 16-pin narrow-body SOIC. Table 7.3 16-Pin Narrow Body SOIC Land Pattern Dimensions on page 51 lists the values for the dimensions shown in the illustration.
Figure 7.3. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 7.3. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.14 | 51
Si823x Data Sheet
Land Patterns
7.4 Land Pattern: 14 LD LGA/QFN
Figure 7.4 14-Pin LGA/QFN Land Pattern on page 52 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA/
QFN. Table 7.4 14-Pin LGA/QFN Land Pattern Dimensions on page 52 lists the values for the dimensions shown in the illustration.
Figure 7.4. 14-Pin LGA/QFN Land Pattern
Table 7.4. 14-Pin LGA/QFN Land Pattern Dimensions
Dimension
(mm)
C1
4.20
E
0.65
X1
0.80
Y1
0.40
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 2.14 | 52
Si823x Data Sheet
Top Markings
8. Top Markings
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC)
Table 8.1. Top Marking Explanation (14/16-Pin Wide Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking: YY = Year
WW = Workweek
TTTTTT = Mfg Code
Line 3 Marking: Circle = 1.5 mm Diameter
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
Manufacturing Code from Assembly Purchase Order form.
“e4” Pb-Free Symbol
(Center Justified)
Country of Origin
TW = Taiwan (as shown), TH = Thailand
ISO Code Abbreviation
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Rev. 2.14 | 53
Si823x Data Sheet
Top Markings
8.2 Si823x Top Marking (16-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: YY = Year
WW = Workweek
TTTTTT = Mfg Code
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Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
Manufacturing Code from Assembly Purchase Order form.
Rev. 2.14 | 54
Si823x Data Sheet
Top Markings
8.3 Si823x Top Marking (14 LD LGA/QFN)
Line 1 Marking: Base Part Number
Ordering Options
See Ordering Guide for more information.
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2 = 0.5 A
3, 4, 5 = 4.0 A
Line 2 Marking: Ordering options
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
I = –40 to +125 °C ambient temperature range
M = LGA package type
M1 = QFN package type
Line 3 Marking: TTTTTT
Manufacturing Code from Assembly
Line 4 Marking: Circle = 1.5 mm diameter
Pin 1 identifier
YYWW
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Manufacturing date code
Rev. 2.14 | 55
Si823x Data Sheet
Revision History
9. Revision History
Revision 2.14
June, 2019
• Added automotive grade OPN, Si8230BD-AS, to Table 1.2 Ordering Guide for Automotive Grade OPNs1, 2, 4, 5 on page 5.
Revision 2.13
September, 2018
• Added automotive grade OPNs in Table 1.2 Ordering Guide for Automotive Grade OPNs1, 2, 4, 5 on page 5.
• Modified power equations in 2.7 Power Dissipation Considerations.
• Corrected typo for IDISABLE in Table 3.1 Electrical Characteristics1 on page 25.
• Reformatted Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
• Added Absolute Max rating of –2V/200 ns on output pins in Table 3.8 Absolute Maximum Ratings1 on page 33.
• Updated 7.2 Land Pattern: 14-Pin Wide Body SOIC.
Revision 2.12
May 2018
• Updated the Ordering Guide for Automotive-Grade OPN options.
Revision 2.1.1
January 2018
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 2.1
October 2017
• Added IS3 and IM1 packaging options
• Added IEC 62368-1 references throughout
• Changed max propagation delay spec from 60 ns to 45 ns based on new test limits
• Removed references to IEC 61010
• Removed references to IEC 60747, replaced with references to VDE 0884-10
Revision 2.0
August 7, 2017
Revision 1.9
July 7, 2017
• Updated 1. Ordering Guide to designate tape and reel packaging option.
Revision 1.8
May 17, 2016
• Converted document from Framemaker to DITA.
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Rev. 2.14 | 56
Si823x Data Sheet
Revision History
Revision 1.7
• Updated 3.1 Test Circuits
• Added CQC certificate numbers.
• Updated Table 3.3 Insulation and Safety-Related Specifications on page 30
• Updated Erosion Depth.
• Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31
• Updated VPR for WBSOIC-16.
• Updated Table 3.8 Absolute Maximum Ratings1 on page 33
• Removed Io and added Peak Output Current specifications.
• Updated Equation 1.
• Updated Figure 4.1 Si823x in Half-Bridge Application on page 34.
• Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
• Updated Ordering Guide Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2
Revision 1.6
• Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
• Added Revision D Ordering Part Numbers.
• Removed all Ordering Part Numbers of previous revisions.
Revision 1.5
• Updated Table 3.1 Electrical Characteristics1 on page 25, input and output supply current.
•
•
•
•
Added references to AEC-Q100 qualified throughout.
Changed all 60747-5-2 references to 60747-5-5.
Added references to CQC throughout.
Updated pin descriptions throughout.
• Corrected dead time default to 400 ps from 1 ns.
• Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
• Removed moisture sensitivity level table notes.
Revision 1.4
• Updated 1. Ordering Guide.
• Updated "3 V VDDI Ordering Options".
Revision 1.3
• Added Si8237/8 throughout.
• Updated Table 3.1 Electrical Characteristics1 on page 25.
•
•
•
•
•
•
•
Updated Figure 3.1 IOL Sink Current Test Circuit on page 28.
UpdatedFigure 3.2 IOH Source Current Test Circuit on page 28.
Added Figure 3.3 Common Mode Transient Immunity Test Circuit on page 29.
Updated Si823x Family Truth Table to include notes 1 and 2.
Updated 2.10 Programmable Dead Time and Overlap Protection.
Removed references to Figures 26A and 26B.
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2.
• Added Si8235-BA-C-IS1 ordering part number.
• Added table note.
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Rev. 2.14 | 57
Si823x Data Sheet
Revision History
Revision 1.2
• Updated 1. Ordering Guide.
• Updated moisture sensitivity level (MSL) for all package types.
• Updated Table 3.8 Absolute Maximum Ratings1 on page 33.
•
•
•
•
•
•
•
• Added junction temperature spec.
Updated 3.1 Test Circuits with new notes.
Updated Figures Figure 2.16 Output Sink Current vs. Supply Voltage on page 14, Figure 2.14 Output Source Current vs. Supply
Voltage on page 13, Figure 2.17 Output Sink Current vs. Temperature on page 14, and Figure 2.15 Output Source Current vs. Temperature on page 13 to reflect correct y-axis scaling.
Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
Updated .
Updated 6.1 Package Outline: 16-Pin Wide Body SOIC.
Updated Table 6.1 Package Diagram Dimensions on page 42.
Change references to 1.5 kVRMS rated devices to 1.0 kVRMS throughout.
• Updated 2.7 Power Dissipation Considerations.
Revision 1.1
• Updated .
• Updated CMTI specification.
• Updated Table 3.1 Electrical Characteristics1 on page 25.
• Updated CMTI specification.
• Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
• Updated 4.2 Dual Driver.
• Updated 1. Ordering Guide.
• Replaced pin descriptions on page 1 with chip graphics.
Revision 1.0
• Updated Tables 3.1 Test Circuits, Table 3.3 Insulation and Safety-Related Specifications on page 30, Table 3.4 IEC 60664-1 Ratings on page 31, and Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
• Updated 1. Ordering Guide.
• Added 5 V UVLO ordering options
• Added Device Marking sections.
Revision 0.3
• Moved Sections 2, 3, and 4 to after Section 5.
• Updated Tables Table 5.4 Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN) on page 39, Table 5.5 Si8234 PWM Input
HS/LS Isolated Driver (14 LD LGA and QFN) on page 40.
• Removed Si8230, Si8231, and Si8232 from pinout and from title.
• Updated and added Ordering Guide footnotes.
• Updated UVLO specifications in Table 3.1 Electrical Characteristics1 on page 25.
• Added PWD and Output Supply Active Current specifications in Table 3.1 Electrical Characteristics1 on page 25.
• Updated and added typical operating condition graphs in 2.3 Typical Operating Characteristics (0.5 Amp) and 2.4 Typical Operating
Characteristics (4.0 Amp).
Revision 0.2
• Updated all specs to reflect latest silicon revision.
• Updated Table 3.1 Electrical Characteristics1 on page 25 to include new UVLO options.
• Updated Table 3.8 Absolute Maximum Ratings1 on page 33 to reflect new maximum package isolation ratings
• Added Figures 34, 35, and 36.
• Updated Ordering Guide to reflect new package offerings.
• Added "Undervoltage Lockout (UVLO)" section to describe UVLO operation.
Revision 0.11
• Initial release.
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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
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