Si825x-DK
Si825 X D EVELOPMENT K IT U SER ’ S G U I D E
1. Kit Contents
The Si825x Development Kit contains the following items:
35 W Si8250 Isolated Half-bridge Target Board
USB to SMBus™ Bridge Board
USB Debug Adapter
USB Cable
Two 9 V, 1.5 A Universal Power Supplies
Silicon Laboratories IDE and Product Information CD-ROM. CD content includes the following:
Silicon
Laboratories Integrated Development Environment (IDE)
8051 Development Tools (macro assembler, linker, evaluation ‘C’ compiler)
Source code examples and register definition files
Si825x Kernel
Application Builder tool suite (waveform editor, compensator, system and MCU wizards)
Keil
PMBus
TM
Monitor Software
Kernel flowcharts and Si825x data sheet
Documentation:
Si825x Development Kit User’s Guide (this document)
Note: The full version of the Kernel when compiled is approximately 14 kB. This exceeds the 4 kB limit of the compiler that is
shipped with the kit’s software development tools. To avoid a compiler issue, either buy the full Keil compiler toolset or
compile the limited version of the Kernel.
2. Hardware Overview
The Si8250 Target Board implements a digitally-controlled, isolated half-bridge current doubler at a PWM
frequency of 400 kHz. The target board (Figure 1) contains system power stages and digital control circuits with
debug connectors for both the secondary-side controller (Si8250) and the primary-side MCU (C8051F300). The
user can directly access the Si8250 using PMBus by connecting a PC to the target board using the included USB
to SMBus Bridge Board.
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Si825x-DK
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Power & Output
Filter Stage
VOUT
VIN
Si8250
C8051F300
PMBus
(J7)
C2 Connector
(J20)
+9V Power
Connector
(J6)
+9V Power
Connector
(J5)
Si8441
Isolation
C2 Connector
(J10)
Figure 1. Si8250 Target Board
3. Target Board Stand-Alone Operation
The Si8250 Target Board comes preloaded with SMPS algorithms installed. This dc-dc converter is designed to
provide 1.0 V output with up to 35 A of output current.
To operate the target board as a stand-alone power supply:
1. Connect the two 9 V, 1.5 A universal power supplies (supplied with the kit) to J5 and J6 as shown in Figure 2.
This supply provides bias for the Si8250 and driver ICs.
2. Connect a third external supply (not provided in kit) to the VIN terminals as shown. This supply needs to provide
a voltage between 36–75 V with at least 2 A of current.
3. Connect an electronic load simulator or other load to the VOUT terminals as shown in Figure 2.
4. Turn the VIN supply on. The target board will start and run.
–
–
Power Supply
(36–75 V, 2 A)
+
Electronic
Load
Simulator
+
Power
Supply
Adaptor
(9 V, 1.5 A)
J6
J5
Figure 2. Board Power Configuration
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Supply
Adaptor
(9 V, 1.5 A)
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4. Development/Debug Initial Hardware Setup
This section describes use of the Si8250 Target Board with the Silicon Laboratories integrated development
environment (IDE) and Application Builder tools. To configure the hardware for connection to the IDE:
1. Disconnect the external supply if connected to VIN and disconnect the load simulator if connected to VOUT.
2. Connect one of the 9 V, 1.5 A universal power supplies (supplied with the kit) to J6. Connect the other 9 V, 1.5 A
universal power supply to J5 as shown in Figure 3.These supplies provide bias for the Si825x, driver ICs, and
the C8051F300.
3. Connect the USB Debug Adaptor’s ribbon cable to the Si8250 Target Board at J10 as shown in Figure 3.
4. Connect the USB cable to the USB Debug Adapter’s USB input plug.
5. Connect the USB cable from the USB Debug Adapter to a USB port on the PC.
Figure 3. Overall View of the Debug Connection
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5. Development/Debug Operation: Software Setup
The Si825x Development Kit comes with Application Builder software (detailed in Section "8. Si825x Application
Builder” on page 11), a configurable real-time software Kernel, and a software Kernel compiled specifically for the
Si8250 Target Board.
The Kernel is royalty-free application software for the Si825x family of digital power controllers that greatly reduces
application program development time, effort, and engineering risk. The Application Builder is used to customize
the Kernel and create C-code source level application software for the Si825x end application. The Application
Builder directly modifies the source code in the Kernel, which is then compiled and downloaded to the Si825x. For
more information on the Kernel, see application note “AN271: Si8250 Real-Time Kernel Overview”.
The half-bridge directory (SiLabs\Power\Si8250_Dev_Kit\Firmware) contains the Kernel configured for the Si8250
Target Board.
Kernel software can be loaded/reloaded to the target board using the Silicon Laboratories IDE. Note that hardware
must be set up as detailed in Section "4. Development/Debug Initial Hardware Setup” on page 3. Follow the
instructions below to configure and download the half-bridge application software for the Si8250 Target Board.
Note: A thorough understanding of the IDE is required before one can use the development/Debug Mode of the kit. The IDE is
detailed in Section "7. Silicon Laboratories Integrated Development Environment".
1. The included CD-ROM contains the Silicon Laboratories Integrated Development Environment (IDE),
Application Builder examples, the PMBus Monitor, Keil software 8051 tools, and additional documentation.
Insert the CD-ROM into your PC’s CD-ROM drive. An installer will automatically launch allowing you to install
the software or read documentation by clicking buttons on the installation panel. If the installer does not
automatically start when you insert the CD-ROM, run autorun.exe found in the root directory of the CD-ROM.
Refer to the ReleaseNotes.txt file on the CD-ROM for the latest information regarding known problems and
restrictions. See Section "7. Silicon Laboratories Integrated Development Environment” on page 8 for further
information on the development tools.
2. Open the IDE by selecting Silicon LaboratoriesSilicon Laboratories IDE from the PC programs menu.
3. Next, the example project included with the kit needs to be opened. Select ProjectOpen Project... from the
IDE menus. In the Project Workspace window, browse to the
“SiLabs\Power\Si8250_Dev_Kit\Firmware\Half_bridge\source” directory and select the *.wsp project file. Press
Open to close the window and open the project.
Note: This example will only work with the full version of the Keil compiler. If the demonstration compiler is used, use the
files in “SiLabs\Power\Si8250_Dev_Kit\Firmware\Half_bridge_basic\source”. This code will compile to less than
4 kB of code.
4. The Si8250 Target Board has several connection requirements that need to be specified before connecting to
the board. Select OptionsConnection Options... from the IDE menu. In the Connection Options window,
select USB Debug Adapter in the Serial Adapter section. Next, select C2 in the Debug Interface section. The
Si825x family of devices use the Silicon Laboratories 2-wire (C2) debug interface. Click OK to close the window.
5. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
6. Build the project by clicking on the Build/Make Project button in the toolbar or by selecting ProjectBuild/
Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the files that have
been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild All button
in the toolbar or select ProjectRebuild All from the menu.
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7. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful, select Enable automatic connect/download
after build in the ProjectTarget Build Configuration dialog. If errors occur during the build process, the IDE will
not attempt the download.
8. Run the example by pressing the Go button in the IDE toolbar.
9. At this point, power can be reapplied to the drivetrain on the Si8250 Target Board. Connect a third external
supply (not provided in kit) to the VIN terminals as shown in Figure 2. This supply needs to provide a voltage of
between 36–75 V with at least 2 A of current.
10.Connect an electronic load simulator to the VOUT terminals as shown in Figure 2.
11. Turn the VIN supply on. The isolated half-bridge supply will start and run.
12.Save the project when finished with the debug session to preserve the current target build configuration, editor
settings, and location of all open debug views. To save the project, select ProjectSave Project from the
menu.
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6. PMBus Operation
PMBus is a connectivity solution designed for connecting power supplies to a single management bus. The Realtime Kernel provided with the Si8250 design kit includes optional support for PMBus. In addition, the Si825x design
kit also comes with a PMBus monitor application and USB to SMBus Bridge Board to manage the power supply
through PMBus.
1. The PMBus Monitor software is installed during the initial software setup. (See Section "5. Development/Debug
Operation: Software Setup” on page 4.)
2. Connect the board as shown in Section "3. Target Board Stand-Alone Operation” on page 2. Note that the
PMBus monitor may also be operated with the USB Debug Adaptor. If this is desired, connect the target board
as shown in Section "4. Development/Debug Initial Hardware Setup” on page 3.
3. Drivers must be installed to allow the PMBus Monitor to communicate with the USB to SMBus Bridge Board.
The driver files are located by default in the "Silabs\Power\Si825x AppBuilder\PMBus Monitor\USB-SMBus
Bridge Board Drivers" directory. Run the PreInstaller.exe application. This program will copy the driver files to
the PC's "Program Files" directory and then will register the driver files so the board will be recognized when it
is connected. Windows Logo testing warnings may appear. Press the "Continue Anyway" button.
4. Connect the USB to SMBus Bridge Board to an available USB slot on your PC with a USB cable.
5. Windows will open a "Found New Hardware Wizard" window. Press "Next" after selecting the
(Recommended) option. Windows Logo testing warnings may appear. Press the "Continue Anyway" button.
Press "Finish" to finish installing the USB-SMBus Bridge Board.
6. Connect the Si8250 Target Board to the USB to SMBus Bridge Board as shown in Figure 4.
Figure 4. PMBus to USB Adapter Connection
7. Open the Application Builder by selecting Silicon LaboratoriesSi825xApplication Builder from the PC
programs menu.
8. Run the PMBus Monitor application by selecting OptionsLaunch PMBus Monitor Tool from the Application
Builder. The window shown in Figure 5 will appear. The PMBus Monitor can be used to control and configure
the target board. The target can be enabled/disabled through the monitor. The PMBus Monitor allows
parameters, such as fault thresholds, to be changed. It also reports operating conditions and problems.
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Figure 5. View of the PMBus Monitor
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7. Silicon Laboratories Integrated Development Environment
The Silicon Laboratories IDE combines an editor, project manager, code development tools, and a debugger into a
single, intuitive environment for code development and in-system debugging. No additional target RAM, program
memory, or communications channels are required. The use of third-party compilers and assemblers is also
supported. This development kit includes the Keil Software A51 macro assembler, BL51 linker, and evaluation
version C51 ‘C’ compiler. These tools can be used from within the Silicon Laboratories IDE. Figure 6 illustrates the
IDE.
Figure 6. IDE
7.1. System Requirements
The Silicon Laboratories IDE requirements:
Pentium-class host PC running Microsoft Windows 95 or later or Microsoft Windows NT or later.
One available USB port.
64 MB RAM and 40 MB free HD space recommended.
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7.2. Assembler and Linker
A full-version Keil A51 macro assembler and BL51 banking linker are included with the development kit and are
installed during IDE installation. The complete assembler and linker reference manual can be found online under
the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (A51.pdf).
7.3. Evaluation C51 ‘C’ Compiler
An evaluation version of the Keil C51 ‘C’ compiler is included with the development kit and is installed during IDE
installation. The evaluation version of the C51 compiler is the same as the full professional version except that
code size is limited to 4 kB, and the floating point library is not included. The C51 compiler reference manual can
be found under the Help menu in the IDE or in the “SiLabs\MCU\hlp” directory (C51.pdf).
7.4. Using the Keil Software 8051 Tools with the Silicon Laboratories IDE
To perform source-level debugging with the IDE, you must configure the Keil 8051 tools to generate an absolute
object file in the OMF-51 format with object extensions and debug records enabled. You may build the OMF-51
absolute object file by calling the Keil 8051 tools at the command line (e.g. batch file or make file) or by using the
project manager built into the IDE. The default configuration when using the Silicon Laboratories IDE project
manager enables object extension and debug record generation. Refer to application note “AN104: Integrating Keil
8051 Tools Into the Silicon Labs IDE” for additional information on using the Keil 8051 tools with the Silicon
Laboratories IDE.
To build an absolute object file using the Silicon Laboratories IDE project manager, you must first create a project.
A project consists of a set of files, IDE configuration, debug views, and a target build configuration (list of files and
tool configurations used as input to the assembler, compiler, and linker when building an output object file).
The following sections illustrate the steps necessary to manually create a project with one or more source files,
build a program, and download the program to the target in preparation for debugging. (The IDE will automatically
create a single-file project using the currently open and active source file if you select Build/Make Project before a
project is defined.)
7.4.1. Creating a New Project
1. Select ProjectNew Project to open a new project and reset all configuration settings to default.
2. Select FileNew File to open an editor window. Create your source file(s) and save the file(s) with a
recognized extension, such as *.c, *.h, or *.asm, to enable color syntax highlighting.
3. Right-click on “New Project” in the Project Window. Select Add files to project. Select files in the file browser
and click Open. Continue adding files until all project files have been added.
4. For each of the files in the Project Window that you want assembled, compiled, and linked into the target build,
right-click on the file name and select Add file to build. Each file will be assembled or compiled as appropriate
(based on file extension) and linked into the build of the absolute object file.
Note: If a project contains a large number of files, the “Group” feature of the IDE can be used to organize. Right-click on
“New Project” in the Project Window. Select Add Groups to project. Add predefined groups or add customized
groups. Right-click on the group name and choose Add file to group. Select files to be added. Continue adding files
until all project files have been added.
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7.4.2. Building and Downloading the Program for Debugging
1. Once all source files have been added to the target build, build the project by clicking on the Build/Make
Project button in the toolbar or selecting ProjectBuild/Make Project from the menu.
Note: After the project has been built the first time, the Build/Make Project command will only build the files that have
been changed since the previous build. To rebuild all files and project dependencies, click on the Rebuild All button
in the toolbar or select Project->Rebuild All from the menu.
2. Before connecting to the target device, several connection options may need to be set. Open the Connection
Options window by selecting OptionsConnection Options... in the IDE menu. First, select the adapter that
was included with the kit in the “Serial Adapter” section. Next, the correct “Debug Interface” must be selected.
Si825x family devices use the Silicon Laboratories 2-wire (C2) debug interface. Once all the selections are
made, click the OK button to close the window.
3. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
4. Download the project to the target by clicking the Download Code button in the toolbar.
Note: To enable automatic downloading if the program build is successful, select Enable automatic connect/download
after build in the ProjectTarget Build Configuration dialog. If errors occur during the build process, the IDE will
not attempt the download.
5. Save the project when finished with the debug session to preserve the current target build configuration, editor
settings, and the location of all open debug views. To save the project, select ProjectSave Project As... from
the menu. Create a new name for the project, and click on Save.
7.5. Si825x Debug Mode
The IDE contained in the Si8250 Development Kit has an Online Debug feature, which optionally enables the user
to inspect or update special function registers (SFRs) in the Si8250 while it is operating. For example, filter
coefficients can be optimized by simply typing in new coefficient values while the supply is connected to a network
analyzer and running. The IDE can also be operated in Standard mode where SFR inspect and update is allowed
only when the Si8250 is not running. As shown in Figure 7, the IDE can be set for Online Debug Mode or Standard
Debug mode by clicking on the circled mode switch.
Figure 7. Si825x IDE Debug Modes
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8. Si825x Application Builder
In addition to the IDE, the Si825x family is also supported with an intuitive toolset that leverages traditional power
supply control design methods minimizing the digital supply design learning curve. The toolset consists of a realtime firmware Kernel (C-language source code), and the Application Builder (see Figure 8). The Application
Builder includes device peripheral configuration options with the Peripheral Configuration Wizard. Additionally,
the Application Builder tools are used to modify the Kernel. Three key development tools within the Application
Builder are the DPWM Timing Diagram Editor, the System Parameter Programmer, and the Compensation
Editor. These tools are detailed in the following sections. The flow diagrams for the Kernel are included on the CD.
Figure 8. Si825x Application Builder
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8.1. DPWM Timing Diagram Editor
The DPWM Timing Diagram Editor permits designers to generate DPWM initialization code by simply drawing
the timing for their end system. The wizard accommodates up to six output phases and can be used to establish
positive or negative dead-times, relative edges, absolute edges, and other timing required by the end system.
Refer to the Si825x data sheet for a description of the different edges.
This example illustrates how to use the DPWM Timing Diagram Editor to create and simulate the timing for a halfbridge as well as generate the initialization code in the Kernel.
1. To open the DPWM Timing Diagram Editor window, open the Application Builder and select System
ConfigurationDPWM Timing Diagram Editor from the menu.
2. To create an absolute edge on Phase 1, hold the mouse above the Phase 1 zero timing line (default) at time tick
10. Then, either double click with the left mouse button or right-click at that point and select Absolute Edge. An
absolute edge at time tick 10 will be created (see Figure 9).
3. To finish the timing for Phase 1, specify hardware modulation using (Cu0). This event edge will be modulated
relative to its absolute edge at time tick 10. To create this edge, hold the mouse above the Phase 1 timing line to
the right of time tick 10 at time tick 60. Either double-click or right-click at that point and select Event (Cu0)
Edge. Next, select the edge to reference by clicking on edge 1 in Phase 1. A relative falling (Cu0) edge will be
created at time tick 60 since U(n) defaults to 50 (see Figure 9).
Figure 9. DPWM Timing Diagram Editor—Phase 1
1. Now, create the timing for Phase 2. For Phase 2, the goal is to create a relative rising edge relative to the falling
edge of Phase 1 and an absolute falling edge on Phase2 at time tick 505. To create the relative rising edge,
hold the mouse above the Phase 2 zero timing line (default) at time tick 100. Then, either double-click with the
left mouse button or right-click at that point and select Relative Edge. Next, select the edge to reference by
clicking on Phase 1’s falling edge. A relative edge at approximately time tick 90 will be created (see Figure 10).
2. To finish the timing for Phase 2, create an absolute falling at time tick 505. To create this edge, hold the mouse
above the Phase 2 timing line at time tick 505. Then, either double-click with the left mouse button or right-click
at that point and select Absolute Edge. An absolute edge at time tick 505 will be created (see Figure 10).
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Figure 10. DPWM Timing Diagram Editor—Phase 2
3. Click the Simulate button to display the Simulate Window (see Figure 11). Use the arrows to increase and
decrease the value of U(n). Notice that Phase 1’s edge should modulate with its absolute edge starting at 10
ticks. Phase 2 should also modulate. However, its rising edge starts relative to Phase 1’s falling edge.
Figure 11. DPWM Timing Diagram Editor—Timing Simulator
4. Now that the desired timing for the two-phase system has been created, click on OK. The Application Builder
will automatically extract the correct DPWM timing initialization data for the Kernel. These coefficients can be
saved to a new project file if desired for later use. Click on FileSave Project to save this project. To generate
an IDE project, select FileBuild IDE Project... and select the directory for project generation.
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8.2. Compensation Editor
The Compensation Editor is a loop simulation and coefficient generation tool for frequency compensating the
system. To open the Compensation Editor window, open the Application Builder and select System
ConfigurationCompensation Editor from the menu. The Compensation Editor for a buck regulator is shown in
Figure 12. As shown, this tool provides fields for the user to enter power stage parameters, such as the output filter
component and parasitic values; controller parameters, such as PWM frequency and pole/zero locations; and
Si8250-specific data, such as ADC sample frequency. The simulator comes prepopulated with default values for
the Si8250 Target Board. These model parameters can be changed as desired. To view the gain and phase plots
with the default parameters, click on the View Graphs button, and their plots will be generated a short time later.
Moreover, clicking on the View Graphs button, the user can view different responses of the buck regulator. Sample
graphs are shown in Figure 12.
Table 1 shows two frequency responses: one for steady-state operation and one for operation during a transient.
The Si8250 automatically extends loop bandwidth by writing faster coefficients to the loop compensation filter (DSP
filter engine). This nonlinear control response improves system transient response, reducing both the magnitude
and duration of the output transient.
Table 1. Si8250 Target Board Frequency Response
Loop Gain Bandwidth
Phase Margin
Steady-State Response
Transient Response
40 kHz
82 degrees
64 kHz
10 degrees
Figure 12. Compensation Editor, Input/Output Windows
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8.3. System Parameter Programmer
The System Setting Programmer allows the designer to input all system settings (UVLO, OV, OCP, etc.) and then
converts these parameters to HEX and populates the resulting initialization code in the Kernel. To open the
System Settings window, open the Application Builder and select System ConfigurationSystem Settings
from the menu (see Figure 13).
.
Figure 13. System Parameters Window
8.4. Peripheral Configuration Wizard
The Peripheral Configuration Wizard can be used to automatically generate initialization code for the Si8250’s onchip peripherals (ADC2, comparator, UART, SMBusTM, etc.). The peripheral windows can be accessed by clicking
on the Peripherals menu in the Application Builder. Figure 14 illustrates the Port I/O window. For more details on
using this wizard, consult the “Help” file by clicking on HelpHelp....
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Figure 14. Peripheral Configuration Wizard - Port I/O Window
9. Restoring Factory Defaults
The Si825x Development Kit includes hex files created for the isolated half-bridge application. Downloading these
hex files to the Si8250 Target Board will restore the board to its factory defaults.
9.1. Restoring the Si8250
To download the factory default Si8250 hex file (secondary side) to the target board, perform the following steps:
1. Open the IDE by selecting Silicon LaboratoriesSilicon Laboratories IDE from the PC programs menu.
2. The Si8250 Target Board has several connection requirements that need to be specified before connecting to
the board. Select OptionsConnection Options... from the IDE menu. In the Connection Options window,
select USB Debug Adapter in the Serial Adapter section. Next, select C2 in the Debug Interface section. The
Si825x family of devices use the Silicon Laboratories 2-wire (C2) debug interface. Press OK to close the window.
3. Connect the USB Debug Adaptor’s ribbon cable to the Si8250 Target Board at J10 as shown in Figure 3.
4. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
5. Select DebugDownload Object File... from the IDE menus to open the download window.
6. Press the Browse button to open the Download Filename... window.
7. In the List files of type: drop down box, select the Intel-Hex option.
8. Browse to the “SiLabs\Power\Si8250_Dev_Kit\Firmware\Half_bridge\hex” directory and select the *.hex file.
Press OK to close the window.
9. Press the Download button to download the file.
10.Click the Disconnect button in the toolbar, or select DebugDisconnect from the menu to disconnect from
the device.
11. Power cycle the device to run the downloaded program.
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9.2. Restoring the C8051F300
To download the factory default C8051F300 hex file (primary side) to the target board, perform the following steps:
1. Open the IDE by selecting Silicon LaboratoriesSilicon Laboratories IDE from the PC programs menu.
2. The Si8250 Target Board has several connection requirements that need to be specified before connecting to
the board. Select OptionsConnection Options... from the IDE menu. In the Connection Options window,
select USB Debug Adapter in the Serial Adapter section. Next, select C2 in the Debug Interface section. The
Si825x family of devices use the Silicon Laboratories 2-wire (C2) debug interface. Press OK to close the window.
3. Remove jumper JP3.
4. Connect the USB Debug Adaptor’s ribbon cable to the Si8250 Target Board at J20.
5. Click the Connect button in the toolbar or select DebugConnect from the menu to connect to the device.
6. Select DebugDownload Object File... from the IDE menus to open the download window.
7. Press the Browse button to open the Download Filename... window.
8. In the List files of type: drop down box, select the Intel-Hex option.
9. Browse to the “SiLabs\Power\Si8250_Dev_Kit\Firmware\half_bridge_iso\hex” directory and select the *.hex file.
Press OK to close the window.
10.Press the Download button to download the file.
11. Replace jumper JP3.
12.Click the Disconnect button in the toolbar, or select DebugDisconnect from the menu to disconnect from
the device.
13.Press switch S3, ‘F300 RST button, and the downloaded firmware will begin to execute.
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10. Si8250 Target Board
The Si8250 Target Board has a Si8250-IQ installed. Refer to Figure 15 for the locations of the various I/O
connectors and major components.
J1, J2
J3, J4
J5
J6
J7
J8
J10
J20
JP1
JP3
VIN, Primary power connection 36–75 V, 2 A
VOUT, Supply output connection for load simulator
Secondary side power connector (9 V, 1.5 A power supply adaptor)
Primary side power connector (9 V, 1.5 A power supply adaptor)
PMBus adapter
I/O header
Si8250 Debug Interface
C8051F300 Debug Interface
Si8250 ENABLE Polarity Select
C8051F300 Reset Capacitor
J2
J4
L3
J3
T1
J1
L4
U1
U2
JP3
Si8250
C8051
F300
J7
LD7
DEBUG
LD3 F300RST Si-8250-RST P1.5
S3
S2
P1.4
S5
JP1
S4
J10
LD4
J6
LD2
LD5
J5
DEBUG
Figure 15. Si8250 Target Board
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Pin 1
J8
J20
LD6
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10.1. System Clock Sources
The Si8250-IQ device installed on the target board features a calibrated programmable internal oscillator that is
enabled as the system clock source on reset. After reset, the device operates at a frequency of 80 kHz by default
using the internal low-frequency oscillator but may be configured by software to operate at other frequencies. Refer
to the Si825x family data sheet for more information on configuring the system clock source.
10.2. Switches and LEDs
Four switches are provided on the target board. Switch S2 is connected to the RESET pin of the Si8250. Switch S3
is connected to the RESET pin of the C8051F300. Pressing S2 or S3 puts the corresponding device into its
hardware-reset state. Switches S4 and S5 are connected to two of the Si8250’s general-purpose I/O (GPIO) pins,
P1.4 and P1.5. Pressing S4 or S5 generates a logic low signal on the port pin. See Table 2 for descriptions of each
switch.
Six LEDs are also provided on the target board. The red LED is used to indicate communications between the
C8051F300 and the Si8250 devices on the target board. The green LED is used to indicate that power is being
regulated by the Si8250. The yellow LEDs are used to indicate power connections to the target board. See Table 2
for a description of each LED.
Table 2. Target Board Switch and LED Descriptions
Label
Reference
Description
F300RST
S3
C8051F300 Reset Switch
Si-8250-RST
S2
Si8250 Reset Switch
P1.5
S5
Si8250 GPIO port pin P1.5 Switch
P1.4
S4
Si8250 GPIO port pin P1.4 Switch
none
LD7
Si8250/C8051F300 Communications Red LED
none
LD6
Power Regulation in process Green LED
V3V3ISO
LD3
3.3 V to C8051F300 from J6 Yellow LED
V3V3
LD4
3.3 V to Si8250 from J5 Yellow LED
V2V5
LD2
2.5 V to Si8250 from J5 Yellow LED
V5VO
LD5
5 V to Si8250 from J5 Yellow LED
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10.3. VIN (J1, J2)
The user-provided power supply should be connected to connectors J1 and J2 where J2 is the reference. The
power source must be from 36–75 V with at least 2 A maximum output.
Table 3. J7 Pin Descriptions
Jumper #
Description
J1
36–75 V, 2 A
J2
GND
10.4. VOUT (J3, J4)
Connectors J3 and J4 are the dc output from the half-bridge. A load should be connected, preferably an electronic
load.
Table 4. J7 Pin Descriptions
Jumper #
Description
J3
1 V (Nominal), 35 A max
J4
Isolated GND
10.5. PMBus Connector (J7)
The J7 connector is the PMBus interface connector for the Si8250 Target Board. Table 5 shows the J7 pin
definitions.
Table 5. J7 Pin Descriptions
20
Pin #
Description
1
SCL
2
DGND
3
SDA
4
DGND
5
SMBA
6
DGND
Rev. 0.31
Si825x-DK
10.6. I/O Connector (J8)
The J8 connector provides access to signals that are not used in the isolated half-bridge converter. These pins can
be used for other purposes, such as debugging or prototyping. Table 6 shows the J8 pin definitions
Table 6. J8 Pin Descriptions
Pin #
Description
1
P0.3
2
P1.3
3
PH5
4
PH6
5
P1.0
6
P1.1
7
GND
8
GND
Rev. 0.31
21
Si825x-DK
10.7. Si8250 DEBUG Interface (J10)
The Si8250 DEBUG connector (J10) provides access to the DEBUG (C2) pins of the Si8250 device on the target
board. It is used to connect the USB Debug Adapter to the target board for in-circuit debugging and programming.
Table 7 shows the J10 Si8250 DEBUG pin definitions.
Table 7. J10 Si8250 DEBUG Connector Pin Descriptions
Pin #
Description
1
+2.5 V
2, 3, 9
DGND
4
C2D
7
RST/C2CK
5, 6, 8, 10
Not Connected
10.8. C8051F300 DEBUG Interface (J20)
The C8051F300 DEBUG connector (J20) provides access to the DEBUG (C2) pins of the C8051F300 device on
the target board. It is used to connect the USB Debug Adapter to the target board for in-circuit debugging and
programming. Table 8 shows the J20 C8051F300 DEBUG pin definitions.
Table 8. J20 C8051F300 DEBUG Connector Pin Descriptions
Pin #
Description
1
+2.5 V
2, 3, 9
DGND
4
C2D
7
RST/C2CK
5, 6, 8, 10
Not Connected
10.9. Si8250 Enable Polarity (JP1)
The JP1 jumper selects the polarity of the reset line for the Si8250. When installed, the reset signal is active high.
Otherwise, it is active low.
10.10. C8051F300 Programmer (JP3)
The JP3 jumper allows the option to connect an onboard capacitor to the reset signal of the C8051F300. Remove
this jumper when programming the C8051F300.
10.11. Voltage and Current Sense Test Points
The Si8250 Target Board has several test points for VREF, VINSENSE, IIN, VSENSE, all PHn, IPK, and more.
These test points correspond to the respective pins on the Si8250-IQ integrated circuit as well as other useful
inspection points. See Section “12. Schematic, Layout, and Bill of Materials” on page 24.
22
Rev. 0.31
Si825x-DK
11. USB Debug Adapter
The USB Debug Adapter provides the interface between the PC’s USB port and the Si825x’s in-system debug/
programming circuitry. The attached 10-pin DEBUG ribbon cable connects the adapter to the target board and the
target device’s debug interface signals. (The USB Debug Adapter supports both Silicon Laboratories JTAG and C2
debug interfaces.) Power is provided to the adapter from the USB connection to the PC. The USB Debug Adapter
is capable of providing power to a circuit board via pin 10 of the DEBUG connector. The Si8250 Target Board is not
designed to be powered from this source. Table 9 shows the pin definitions for the DEBUG ribbon cable connector.
Note: The USB Debug Adapter requires a target system clock of 32 kHz or greater.
With the default settings, the USB Debug Adapter can supply up to 100 mA to a target system.
Table 9. USB Debug Adapter DEBUG Connector Pin Descriptions
Pin #
Description
1,8
Not Connected
2,3,9
GND (Ground)
4
TCK (C2D)
5
TMS
6
TDO
7
TDI (C2CK)
10
USB Power
DEBUG
Ribbon Cable
USB DEBUG ADAPTER
Run
Stop
Power
USB Connector
Figure 16. USB Debug Adapter
Rev. 0.31
23
150
NC7
NC6
OUT
0.1uF
1
3
2
GND_ISO
DNP
C136
1
C137
RXD
TXD
C2CK
C2D
Isolated
GND
C91
22uF25V
7
6
8
10
3
+
F3_C2CK
F3_C2D
3
1
8
JP3
U33
LT1761ES5-3.3
SHDN
IN
R1
1
CR 1
2
TP1
T2-1
PA0368_050
4R7
BAS16D
2
3
HB
HO
HS
LO
VCC
HI
LI
GND
U3
LM5101M
TP2 G2
G2
1
V3V3ISO
BYP
OUT
4
5
C133
RN2D
5
R17
0
C17
DNP
1uF25V
C131
47uF6V3V
+ C130
V3V3ISO
R62
DNP
F3_PD7
5.6V
TV8
F3RXD
F3TXD
24
RN2C
V3V3ISO
R67
511
9
15
10
14
13
12
11
16
GND2
GND2
E N2
OUT1
OUT2
OUT3
IN4
VDD2
3
U35
Si8441
V3V3ISO
TG4
TG3
V5V0
V2V5
8
2
8
7
3
4
5
6
1
R25
200
LD2
YELLOW
GND1
GND1
EN1
IN1
I N2
IN3
OUT4
6
5
7
A1
INB
INA
NC1
R68
511
V5V0
TP55
RXD
R50
1.21K
+
3
1
F2PH3
TP53
F2PH3
3
3
3
C51
1uF25V
10uF25V
V5V0
TP50
F2TXD
F2RXD
F2PH1
F2PH2
IPK
3
3
0.01uF
0.1uF0508
C52
C53
3.3V
TV2
0.1uF
0
3
C5
4
2
-VOUT
+VOUT
R6
3
L3
4
2
C50
F2PH4
TP54
F2PH4
V5V0
3
1
L4
IRLR8113
Q3
-VOUT
TP23
TP56
TXD
F2PH2
TP52
IPK
TP32
LD5
YELLOW
DGND
TP24
F2TXD
F2RXD
LD4
YELLOW
DGND
TP20
F2PH1
F2PH2
F2PH1
TP51
R15
39R2
DNP
R14
V3V3
V3V3
K1
K2
7R5
C15
0.01uF
F2PH4
F2PH3
VS3
G3
G3 1
G4
D5
BAS70DW-04
1
2
3
4
R13
A2
TP3
1uF25V
GND
UCC27324D
NC8
OUTA
VCC
OUTB
U4
C6
2R2
R3
TP4
G4 1
2R2
R4
BAS16D
2
3
Q4
IRLR8113
BAS16D
2
3
VS4
1
CR4
CR3
1
C32
0.1uF0508
V3V3
R12
10K
VDD1
3
T2-2
PA0368_050
2 2
2.5mA LED current
LD3
YELLOW
*
S
TP28
VS3
C132
0.1uF0508
DNP
C16
PH 1
TP16
V3V3ISO
PH1
PH2
0
R16
C42
1uF25V
T1-2
T1_PLN
VS4
TP29
4
5
BYP
OUT
.1uF
SHDN
IN
3
1
0.01uF
V2V5
TP25
0.01uF
V3V3
TP34
C55
5
4
5
4
R37
R32
C35
R31
R30
1K
DNP
30.1 K
1K
3
DNP
BYP
OUT
BYP
OUT
SHDN
3
1
3
1
Digital GND
SHDN
IN
U25
LT1761ES5-2.5
VSENSE
C90
22uF25V
3
Vo=(V1-V2)*(R31/R30)
Digital GND
U34
LT1761ES5-3.3
1000pF X7R
IN
1K
R35
C39
4
-
1K
1K
R34
3
+
R36
V2
V1
+
R5
0.001
Optional: Place
on Back of PCB
IOUT_FLT
Vo=(V1-V2)*(R31/R30)
TP41
VSEN
TP40
IOUT
U7
LMV721
4
150
DNP
1K
C34
1
3
-
NOTE: 20A high current
path, use plane/pour
C12
C11
C10
U6
LMV721
+
30.1 K
150
V2V5A
Digital GND
C25
C33
U50
LT1761ES5-5
1uF25V
C72
V2V5
1uF25V
C31
V3V3
R55
.1uF
V2V5A
1
C30
DNP
R33
C54
C29
R54
.1uF
C28
C9
C8
C7
plane
MULTIPLE VIAS ON ALL SUPPLY CAPS
LOW ESR MLCeramic 1812 Package
IOUT
+VOUT
TP26
Figure 17. Si8250 Target Board Schematic (Page 1)
0.01uF
V3V3ISO
TP33
0
PH2
TP17
C41
0.1uF100V
R40
V9V0ISO
Q2
FDS3572
Q1
FDS3572
Note: Orient J20 with Pin 1
to upper,left
4 24
AC2
K2
A1
A2
2
4
6
8
10
K1
AC1
1
3
5
7
9
J20
F300_DEBUG
1
5
6
7
VP1
TP9
VP1
G1
G1
LAYOUT: Place 0.500 apart
GND_ISO
GND_ISO
TP5
TP10
2
3
4
8
0.1uF100V
C4
4R7
BAS16D
2
3
GD2
TP22
R2
TG21
CR2
TP8
VP2
VP2
GD1
TP21
RN2A
24
TG1
V3V3ISO
D2
BAS70DW-04
C140 0.1uF0508
1
24
4R7
F3_RST_B
RN2B
R20
4 R7
4
PGND
TP7
T1-1
T1-6-1
R19
PGND
TP27
R61
1K
C134
0.1uF0508
PGND
2.2uF
C3
0.01uF
C18
VP3
VP3
TP38
2.2uF
C2
VIN
0.1uF0508
U2
C8051F300
V9V0ISO
D3
2
Optional
RST
V3V3ISO
15V_uni
VREF
P0.2
P0.3
P0.6
AIN1
C139
1K
R27
R26
33K
MAX803
C135
1uF25V
R64
2
VCC
U5
1K
R24
R23
33K
100K
VREF TP15
1uF25V
2
3
3
100K
R63
4
5
9
C138
C60
V3V3ISO
1
4
1K
UVLO
S3
F300RST
+
1uH
L1
C1 120uF
R60
V3V3ISO
DCBAL
SCVIN
IIN
7
6
5
TP12
TP13
TP14
VINSC
IIN
DCBAL
UVLO TP11
.1uF
C59
1
R59
VCC
GND
U8 MAX4080
2
4
1
0.010
8
RS-
RS+
R11
1200pF
RED
4
100uF_Cer
1
J6
9V_ISO
BLACK
GND
1
3
VDD
GND
11
*
P
7
2
1
1
2
2
3
3
VIN
TP6
RF ISO
100uF_Cer
NOTE: 75V/1A high power
path, use 0.025" min
trace.
A
C
0
R38
0
R 10
15V_uni
D4
V9V0
DNP
R39
TP18
VOA
TP19
VOB
RED
J4
J3
VOUT PGND
1
NOTE: At 25W, max avg current is .3A @ 75V
Allowing for a peak of 1A gives 10mV across R11
A MAX4080 with 60x gain will output 600mV
A
C
AC1
AC2
100uF_Cer
J1
VIN
GND
2
A
C
6
3
2
1
A
C
100uF_Cer
5
2
5
2
2
100uF_Cer
GND
2
1
100uF_Cer
2
GND
2
GND
Rev. 0.31
2
1
NOTE: Min spacing between pair
24
1
3
2
0
J5
R52
1
BLACK
2
J2
PGND
J9
9V
VOUT
Si825x-DK
12. Schematic, Layout, and Bill of Materials
2
2
IPK
F2PH1
F2PH2
F2PH3
F2PH4
R77
V2V5
R76
V2V5
V2V5
V2V5
LD6
A
LD7
A
C
C
S5
1K
S4
1K
P1.5
P1.4
GREEN
RED
GNDA
TP30
2 F2TXD
2 F2RXD
2
2
2
2
IOUT_FLT
VSENSE
2
GNDA
TP35
TP31
VREF1V2
1
4
1
4
DNP
R9
DNP
R8
2
3
2
3
TP43
C74
0.1uF0508
C75
0.1uF0508
P05
P15
R72
R75
R74
R73
.1uF
4.7uF16V
4.7K
4.7K
200
200
VREF1V2
C37
14
11
C21
1uF25V
V2V5A
10uF25V
C27
Analog GND
P1.5
P1.4
P0.6
P1.6
P0.4
P0.5
PH1
PH2
PH3
PH4
P1.2
VSENSE
IPK
+
V2V5
DGND
40Z800mA
C22
0.1uF0508
P0.0
P0.1
P0.2
P0.7
C23
1uF25V
V2V5
1
3
5
7
9
V2V5
2
4
6
8
10
8
C58
.1uF
DNP
1K
R46
R58
DNP
1K
R45
R57
1K
R44
25
7
C57
.1uF
1K
1K
RN6A 24
1
A1
A2
R43
R41
8
D6
RN6B 24
7
2
RN6C 24
6
3
A1
A2
26
PS_EN
SDA
SCL
SMBA
RN6D 24
4
D7
5
1K
C56
.1uF
24
RN1D
24
RN1C
Note: Orient J10 with Pin 1 to bottom,left
D1
BAS70DW-04
J10
SI-8250_DEBUG
S2
SI-8250_RST
1
R42
24
RN1B
RN1A
24
F2_RST_B
8
1
2
C70
1uF25V
DNP
F2_C2CK
F2_C2D
C71
0.1uF0508
R56
10
21
24
23
22
17
1
16
C24
0.1uF0508
P1.1 / AIN1
P1.0 / AIN0
PH6
PH5
P1.3 / AIN3
P0.3 / XCLK
Digital GND
V2V5
U1
SI-8250
10uF25V
C20
RST / C2CK
P1.7 / C2D
+
1K
R71
V2V5
R70
1K
Figure 18. Si8250 Target Board Schematic (Page 2)
P15
TP37
P14
TP36
18
15
20
19
32
31
30
27
9
3
2
6
0
VREF
R21
Analog GND
GNDA
C26
1uF25V
Place C36,C26 at U1
C36
.1uF
C38
U9
LM4051BIM3-12
Is=5mA
TP42
R7
249
V2V5
AC1
A1
FB1
K1
A2
V2V5A
7
2
6
3
4
5
V2V5A
13
28
VDD
VDD
GND
GND
K2
AC2
4
AC2
AC1
AC2
AC1
5
VDDA
GNDA
4
Rev. 0.31
29
12
K1
K2
K1
K2
V2V5
BAS70DW-04
RN7D 24
4
8
RN7A 24
1
V2V5
BAS70DW-04
RN7B 24
7
2
RN7C 24
6
3
5
C77
1uF25V
99K
R78
EXT_EN
PMBus
J7
1
2
3
4
5
6
7
8
J8
SI8250-EXT
V2V5
2
4
6
1
2
3
JP1
LO
OPEN HI
J8 Silk:
P03
P13
PH5
PH6
P10
P11
GND
GND
1
3
5
Si825x-DK
25
Si825x-DK
13. Bill of Materials
Table 10. Si825x-DK Bill of Materials
Item
Qty
Reference
Footprint
Part
MFG
MFG-PN
Dist
1
1
C55
C0603
1000 pF X7R
Panasonic
ECJ-1VB1H102K
Digi-Key
2
1
C60
C0603
1200 pF
Panasonic
ECJ-1VB1H122K
Digi-Key
3
12
C5,C22,C24,C32,C52,C71,
C74,C75,C132,C134,C137,
C139
C0508
0.1 uF0508
Panasonic
ECY-29RE104KV
Digi-Key
4
5
C15,C25,C33,C53,C133
C0603
0.01 uF
Panasonic
ECJ-1VB1C103K
Digi-Key
5
9
C28,C29,C36,C37,C54,
C56,C57,C58,C59
C0603
.1 uF
Panasonic
ECJ-1VB1E104K
Digi-Key
6
2
C41,C4
C0805
0.1 uF100 V
TDK
C2012X7R2A104K
7
14
C6,C18,C21,C23,C26,
C31,C42,C51,C70,C72,
C73,C77,C131,C135,C138
C1206
1 uF25 V
Panasonic
ECJ-3YB1E105K
Digi-Key
8
6
C7,C8,C9,C10,C11,C12
C1812
100 uF_Cer
TDK
C4532X5R0J107M
Digi-Key
9
2
C3,C2
C1812
2.2 uF
Murata
GRM43ER72A225KA01L
Digi-Key
10
3
C20,C27,C50
C7343D
10 uF25 V
Kemet
T491D106M025A5
Digi-key
11
2
C90,C91
C7343D
22 uF25 V
Panasonic
ECS-T1ED226R
Digi-Key
12
1
C38
C1206
4.7 uF16 V
TDK
C3216X7R1C475K
Digi-Key
13
1
C130
C7343D
47uF6V3V
Panasonic
EEF-HL0J470R
Digi-Key
14
1
C1
M16x15
120 uF
United Chemicon
SXE100VB121M16X15LL
15
4(dnp)
C16,C17,C30,C35
C0603
DNP
16
3(dnp)
C34,C39,C136
C0603
DNP
17
4
CR1,CR2,CR3,CR4
SOT23-3
BAS16D
Diodes Inc
BAS16-7-F
Digi-Key
18
5
D1,D2,D5,D6,D7
SOT363-6
BAS70DW-04
Diodes Inc
BAS70DW-04
Digi-Key
19
2
D4,D3
SMA
15 V_uni
Diodes Inc
SMAJ15A-13
Digi-Key
20
1
FB1
FB0805
40Z800 mA
Steward
LI0805H400R-00
Digi-Key
21
4
HOL1,HOL2,HOL3,HOL4
MH_170_NP
MH
22
2
J1.J3
BJ
VIN
Johnson Components 111-0702-001
23
2
J2,J4
BJ
PGND
Johnson Components 111-0703-001
24
2
J5,J6
PWR_J
9V
25
1
JP1
BERG1X2
26
1
J8
27
1
28
Switchcraft
RAPC722
Digi-Key
JUMPER1x2
Molex
22-28-4023
Digi-Key
BERG1X8
SI8250-EXT
Molex
22-28-4083
Digi-Key
J7
HEADER_3X2RA
Pmbus
Sullens
PTC03DBAN
Digi-Key
2
J10,J20
HEADER_5X2
10-89-1101
Digi-Key
29
4
LD2,LD3,LD4,LD5
D1206
YELLOW
CML
CMD15-21VYD/TR8
Digi-Key
30
1
LD6
D1206
GREEN
CML
CMD15-21VGD/TR8
Digi-Key
31
1
LD7
D1206
RED
CML
CMD15-21VRD/TR8
Digi-Key
32
1
L1
DO1605
1 uH
CoilCraft
DO1605T-102MX
Coilcraft
33
2
L3,L4
L2525-2
Ferroxcube
E18/4/R-3F35-A160-P
26
SI-8250_DEBUG Molex
Rev. 0.31
Si825x-DK
Table 10. Si825x-DK Bill of Materials (Continued)
Item
Qty
Reference
Footprint
Part
34
2
Q1,Q2
DPAK
SUD15N15-95
35
2
Q4,Q3
DPAK
36
3
R54,R55,R59
R60603
150
37
21
R15,R24,R27,R30,R32,
R34,R35,R36,R37,R41,
R42,R43,R44,R45,R46,
R60,R61,R70,R71,R76,
R77
R0603
38
1
R12
39
5
40
MFG
Vishay
SUD40N03-18P Vishay
MFG-PN
Dist
SUD15N15-95
SUD40N03-18P
Mouser
Panasonic
ERJ-3EKF150V
Digi-Key
1K
Panasonic
ERJ-3EKF1001V
Digi-Key
R0603
10 K
Panasonic
ERJ-3EKF1002V
Digi-Key
R23,R26,R63,R64,R78
R0603
100 K
Panasonic
ERJ-3EKF1003V
Digi-Key
2
R31,R33
R0603
30.1 K
Panasonic
ERJ-3EKF3012V
Digi-Key
41
1
R50
R0603
1.21K
Panasonic
ERJ-3EKF1211V
Digi-Key
42
3
R25,R72,R73
R0603
200
Panasonic
ERJ-3EKF2000V
Digi-Key
43
1
R7
R0603
249
Panasonic
ERJ-3EKF2490V
Digi-Key
44
2
R74,R75
R0603
4.7 K
Panasonic
ERJ-3EKF4751V
Digi-Key
45
2
R68,R67
R0603
511
Panasonic
ERJ-3EKF5110V
Digi-Key
46
7
R6,R16,R17,R21,R38,
R40,R52
R0603
0
Panasonic
ERJ-3GEY0R00V
Digi-Key
47
8
R1,R2,R3,R4,R13,R14,
R19,R20
R0805
4R7
Panasonic
ERJ-3RQJ4R7V
Digi-Key
48
1
R11
R2512
0.01
Panasonic
ERJ-M1WSF10MU
Digi-Key
49
1
R5
R2512
0.001
Panasonic
ERJ-M1WTJ1M0U
Digi-Key
50
4
RN1,RN2,RN6,RN7
RPEXB28V
24
Panasonic
EXB-28V240JX
Digi-Key
51
7(dnp)
R8,R9,R39,R56,R57,
R58,R62
R0603
DNP
52
4
S2,S3,S4,S5
SWPAD04
SI-8250_RST
Panasonic
EVQ-PAD04M
Digi-Key
53
4
TP25,TP33,TP34,TP50
TP040
V2V5
Keystone
5000
Digi-Key
54
6
TP5,TP10,TP20,TP24,
TP30,TP35
TP040
GND_ISO
Keystone
5001
Digi-Key
55
25
TP1,TP2,TP3,TP4,TP6,
TP7,TP8,TP9,TP11,TP12,
TP13,TP14,TP15,TP16,
TP17,TP21,TP22,TP23,
TP27,TP31,TP32,TP51,
TP52,TP53,TP54
TP040
G1
Keystone
5002
Digi-Key
56
1
TV2
D0603
3.3 V
AVX
VC060303A100DP
Mouser
57
1
TV8
D0603
5.6 V
AVX
VC060305A150RP
Mouser
58
1
T1
T1_PCB
T1-6-1
Ferroxcube
E22/6/16/R-3F3
59
1
T2
PA0282
PA0368_050
Pulse
PA0368.050
60
1
U5
SC70-3
MAX803
Maxim
MAX803TEXR
61
1
U8
UMAX-8
MAX4080
Maxim
MAX4080SAUA
62
1
U9
SOT23-3
63
1
U3
SO-8
LM4051BIM3-12 National
LM5101AM
Rev. 0.31
National
LM4051BIM3-12
Digi-Key
LM5101AM
Digi-Key
27
Si825x-DK
Table 10. Si825x-DK Bill of Materials (Continued)
Item
Qty
Reference
Footprint
Part
64
2
U6,U7
SOT23-5
LMV721
65
1
U25
SOT23-5
66
2
U33,U34
SOT23-5
67
1
U50
SOT23-5
LT1761ES5-5
68
1
U35
SO-16_WIDE
69
1
U1
70
1
71
1
28
MFG
Dist
LMV721M5
Digi-Key
LT1761ES5-2.5 LTC
LT1761ES5-2.5
Arrow
LT1761ES5-3.3 LTC
LT1761ES5-3.3
Arrow
LTC
LT1761ES5-5
Arrow
Si8441
SiLabs
Si8441BB-C-IS
SiLabs
LQFP32
Si8250
SiLabs
Si8250-IQ
SiLabs
U2
MLP11
C8051F300
SiLabs
C8051F300
SiLabs
U4
SO-8
UCC27324D
TI
UCC27324D
Digi-Key
Rev. 0.31
National
MFG-PN
Si825x-DK
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Updated “Contact Information” on page 30.
Updated
disclaimer.
Revision 0.3 to Revision 0.31
Updated Table 10 to reflect new Si84xx isolation
nomenclature.
Rev. 0.31
29
Si825x-DK
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: MCUinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
The sale of this product contains no licenses to Power-One’s intellectual property. Contact Power-One, Inc. for appropriate licenses.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
30
Rev. 0.31
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