Si827x Data Sheet
4 Amp ISOdriver with High Transient (dV/dt) Immunity
KEY FEATURES
The Si827x isolators are ideal for driving power switches used in a wide variety of
power supply, inverter, and motor control applications. The Si827x isolated gate drivers
utilize Skyworks' proprietary silicon isolation technology, supporting up to 2.5 kVRMS
withstand voltage per UL1577 and VDE0884. This technology enables industry leading
common-mode transient immunity (CMTI), tight timing specifications, reduced variation
with temperature and age, better part-to-part matching, and extremely high reliability.
It also offers unique features such as separate pull-up/down outputs, driver shutdown
on UVLO fault, and precise dead-time programmability. The Si827x series offers longer
service life and dramatically higher reliability compared to opto-coupled gate drivers.
The Si827x drivers utilize Skyworks' proprietary silicon isolation technology, which provides up to 2.5 kVRMS withstand voltage per UL1577 and fast 60 ns propagation times.
Driver outputs can be grounded to the same or separate grounds or connected to a positive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis are
available in individual control input (Si8271/2/3/5) or PWM input (Si8274) configurations.
High integration, low propagation delay, small installed size, flexibility, and cost-effectiveness make the Si827x family ideal for a wide range of isolated MOSFET/IGBT and SiC
or GaN FET gate drive applications.
Automotive Grade products are built using automotive-specific flows at all steps in
the manufacturing process to ensure the robustness and low defectivity required for
automotive applications.
Industrial Applications
• Switch-mode Power Supplies
• Solar Power Inverters
• Motor control and drives
• Uninterruptible Power Supplies
• High-Power Class D Amplifiers
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 2500 VRMS for 1 minute
Automotive Applications
• On-board chargers
• Battery management systems
• Charging stations
• Traction inverters
• Hybrid Electric Vehicles
• Battery Electric Vehicles
• Single, dual, or high-side/low-side drivers
• Single PWM or dual digital inputs
• High dV/dt immunity:
• 200 kV/µs CMTI
• 400 kV/µs Latch-up
• Separate pull-up/down outputs for slew
rate control
• Wide supply range:
• Input supply: 2.5–5.5 V
• Driver supply: 4.2–30 V
• Very low jitter of 200 ps p-p
• 60 ns propagation delay (max)
• Dedicated enable pin
• Skyworks’ high performance isolation
technology:
• Industry leading noise immunity
• High speed, low latency and skew
• Best reliability available
• Compact packages:
• 8-pin SOIC
• 16-pin SOIC
• DFN-14 (pin to pin compatible with
LGA-14 packages)
• Wide temperature range:
• –40 to 125 °C
• AEC-Q100 Qualified
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• IMDS and CAMDS listing support
• CSA approval
• IEC 60950-1 (reinforced insulation)
• VDE certification conformity
• VDE 0884 Part 10
• CQC certification approval
• GB4943.1-2011
1
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.06 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 23, 2021
1
Si827x Data Sheet • Ordering Guide
1. Ordering Guide
Industrial and Automotive Grade OPNs
Industrial-grade devices (part numbers having an “-I” in their suffix) are built using well-controlled, high-quality manufacturing flows to
ensure robustness and reliability. Qualifications are compliant with JEDEC, and defect reduction methodologies are used throughout
definition, design, evaluation, qualification, and mass production steps.
Automotive-grade devices (part numbers having an “-A” in their suffix) are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part Approval
Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material Data System
(CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is employed throughout definition,
de-sign, evaluation, qualification, and mass production steps.
Table 1.1. Si827x Ordering Guide1, 2, 3
Ordering
Part Number
Automotive
OPN4, 5
Inputs
Driver
Configuration6
Output
UVLO
(V)
DeadIntegrated Time
Low
Deglitcher Range Jitter
(ns)
Package
Isolation
Rating
2.5 kVRMS Isolation Options
Si8271AB-IS
Si8271AB-AS
VI
Single
5
N
N/A
Y
SOIC-8 NB
2.5 kVRMS
Si8271BB-IS
Si8271BB-AS
VI
Single
8
N
N/A
Y
SOIC-8 NB
2.5 kVRMS
Si8271ABD-IS
Si8271ABD-AS
VI
Single
5
Y
N/A
N
SOIC-8 NB
2.5 kVRMS
Si8271BBD-IS
Si8271BBD-AS
VI
Single
8
Y
N/A
N
SOIC-8 NB
2.5 kVRMS
Si8271DB-IS
Si8271DB-AS
VI
Single
12
N
N/A
Y
SOIC-8 NB
2.5 kVRMS
Si8271DBD-IS
Si8271DBD-AS
VI
Single
12
Y
N/A
N
SOIC-8 NB
2.5 kVRMS
Si8271GB-IS
Si8271GB-AS
VI
Single
3
N
N/A
Y
SOIC-8 NB
2.5 kVRMS
Si8271GBD-IS
Si8271GBD-AS
VI
Single
3
Y
N/A
N
SOIC-8 NB
2.5 kVRMS
Si8273AB-IS1
Si8273AB-AS1
VIA/VIB
HS/LS
5
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8273ABD-IS1
Si8273ABD-AS1
VIA/VIB
HS/LS
5
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8273BB-IS1
Si8273BB-AS1
VIA/VIB
HS/LS
8
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8273BBD-IS1
Si8273BBD-AS1
VIA/VIB
HS/LS
8
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8273DB-IS1
Si8273DB-AS1
VIA/VIB
HS/LS
12
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8273DBD-IS1
Si8273DBD-AS1
VIA/VIB
HS/LS
12
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8273GB-IS1
Si8273GB-AS1
VIA/VIB
HS/LS
3
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8273GBD-IS1
Si8273GBD-AS1
VIA/VIB
HS/LS
3
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8274AB1-IS1
Si8274AB1-AS1
PWM
HS/LS
5
N
10-200
Y
SOIC-16 NB 2.5 kVRMS
Si8274AB4D-IS1
Si8274AB4D-AS1
PWM
HS/LS
5
Y
20-700
N
SOIC-16 NB 2.5 kVRMS
Si8274BB1-IS1
Si8274BB1-AS1
PWM
HS/LS
8
N
10-200
Y
SOIC-16 NB 2.5 kVRMS
Si8274BB4D-IS1
Si8274BB4D-AS1
PWM
HS/LS
8
Y
20-700
N
SOIC-16 NB 2.5 kVRMS
Si8274DB1-IS1
Si8274DB1-AS1
PWM
HS/LS
12
N
10-200
Y
SOIC-16 NB 2.5 kVRMS
Si8274DB4D-IS1
Si8274DB4D-AS1
PWM
HS/LS
12
Y
20-700
N
SOIC-16 NB 2.5 kVRMS
Si8274GB1-IS1
Si8274GB1-AS1
PWM
HS/LS
3
N
10-200
Y
SOIC-16 NB 2.5 kVRMS
2
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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2
Si827x Data Sheet • Ordering Guide
Ordering
Part Number
Automotive
OPN4, 5
Si8274GB4D-IS1 Si8274GB4D-AS1
DeadIntegrated Time
Low
Deglitcher Range Jitter
(ns)
Inputs
Driver
Configuration6
Output
UVLO
(V)
PWM
HS/LS
3
Y
20-700
N
SOIC-16 NB 2.5 kVRMS
Package
Isolation
Rating
Si8275AB-IS1
Si8275AB-AS1
VIA/VIB
Dual
5
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8275ABD-IS1
Si8275ABD-AS1
VIA/VIB
Dual
5
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8275BB-IS1
Si8275BB-AS1
VIA/VIB
Dual
8
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8275BBD-IS1
Si8275BBD-AS1
VIA/VIB
Dual
8
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8275DB-IS1
Si8275DB-AS1
VIA/VIB
Dual
12
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8275DBD-IS1
Si8275DBD-AS1
VIA/VIB
Dual
12
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8275GB-IS1
Si8275GB-AS1
VIA/VIB
Dual
3
N
N/A
Y
SOIC-16 NB 2.5 kVRMS
Si8275GBD-IS1
Si8275GBD-AS1
VIA/VIB
Dual
3
Y
N/A
N
SOIC-16 NB 2.5 kVRMS
Si8273AB-IM1
Si8273AB-AM1
VIA/VIB
HS/LS
5
N
N/A
Y
DFN-14
2.5 kVRMS
Si8273ABD-IM1
Si8273ABD-AM1
VIA/VIB
HS/LS
5
Y
N/A
N
DFN-14
2.5 kVRMS
Si8273GB-IM1
Si8273GB-AM1
VIA/VIB
HS/LS
3
N
N/A
Y
DFN-14
2.5 kVRMS
Si8274AB1-IM1
Si8274AB1-AM1
PWM
HS/LS
5
N
10-200
Y
DFN-14
2.5 kVRMS
PWM
HS/LS
5
Y
20-700
N
DFN-14
2.5 kVRMS
PWM
HS/LS
3
N
10-200
Y
DFN-14
2.5 kVRMS
PWM
HS/LS
3
Y
20-700
N
DFN-14
2.5 kVRMS
Si8274AB4D-IM1 Si8274AB4D-AM1
Si8274GB1-IM1
Si8274GB1-AM1
Si8274GB4D-IM1 Si8274GB4D-AM1
Si8275AB-IM1
Si8275AB-AM1
VIA/VIB
Dual
5
N
N/A
Y
DFN-14
2.5 kVRMS
Si8275ABD-IM1
Si8275ABD-AM1
VIA/VIB
Dual
5
Y
N/A
N
DFN-14
2.5 kVRMS
Si8275BB-IM1
Si8275BB-AM1
VIA/VIB
Dual
8
N
N/A
Y
DFN-14
2.5 kVRMS
Si8275BBD-IM1
Si8275BBD-AM1
VIA/VIB
Dual
8
Y
N/A
N
DFN-14
2.5 kVRMS
Si8275DB-IM1
Si8275DB-AM1
VIA/VIB
Dual
12
N
N/A
Y
DFN-14
2.5 kVRMS
Si8275DBD-IM1
Si8275DBD-AM1
VIA/VIB
Dual
12
Y
N/A
N
DFN-14
2.5 kVRMS
Si8275GB-IM1
Si8275GB-AM1
VIA/VIB
Dual
3
N
N/A
Y
DFN-14
2.5 kVRMS
Si8275GBD-IM1
Si8275GBD-AM1
VIA/VIB
Dual
3
Y
N/A
N
DFN-14
2.5 kVRMS
1 kVRMS Isolation Options
Si8271GA-IS
Si8271GA-AS
VI
Single
3
N
N/A
Y
SOIC-8 NB
1 kVRMS
Si8271GAD-IS
Si8271GAD-AS
VI
Single
3
Y
N/A
N
SOIC-8 NB
1 kVRMS
Si8273GA-IM1
Si8273GA-AM1
VIA/VIB
HS/LS
3
N
N/A
Y
DFN-14
1 kVRMS
Si8273GAD-IM1
Si8273GAD-AM1
VIA/VIB
HS/LS
3
Y
N/A
N
DFN-14
1 kVRMS
Si8274GA1-IM1
Si8274GA1-AM1
PWM
HS/LS
3
N
10-200
Y
DFN-14
1 kVRMS
PWM
HS/LS
3
Y
10-200
N
DFN-14
1 kVRMS
Si8274GA1D-IM1 Si8274GA1D-AM1
3
Si8275GA-IM1
Si8275GA-AM1
VIA/VIB
Dual
3
N
N/A
Y
DFN-14
1 kVRMS
Si8275GAD-IM1
Si8275GAD-AM1
VIA/VIB
Dual
3
Y
N/A
N
DFN-14
1 kVRMS
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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3
Si827x Data Sheet • Ordering Guide
DeadIntegrated Time
Low
Deglitcher Range Jitter
(ns)
Inputs
Driver
Configuration6
Output
UVLO
(V)
Si8275DA-AM1
VIA/VIB
Dual
12
N
N/A
Si8275DAD-AM1
VIA/VIB
Dual
12
Y
N/A
Ordering
Part Number
Automotive
OPN4, 5
Si8275DA-IM1
Si8275DAD-IM1
Package
Isolation
Rating
Y
DFN-14
1 kVRMS
N
DFN-14
1 kVRMS
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the Ordering Part Number indicates tape and reel option.
4. Automotive-Grade devices (with an “-A” suffix) are identical in construction materials and electrical parameters to their IndustrialGrade (with an “-I” suffix) version counterpart. Automotive-Grade products are produced utilizing full automotive process flows
and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on
shipping labels.
5. In Top Markings, the Manufacturing Code represented by “TTTTTT” contains, as its first character, a letter in the range N through
Z to indicate Automotive-Grade.
6. All HS/LS drivers have built-in overlap protection while the single and dual drivers do not.
4
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4
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Typical Operating Characteristics .
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.10
2.2 Family Overview and Logic Operation During Startup .
2.2.1 Products . . . . . . . . . . . . . .
2.2.2 Device Behavior . . . . . . . . . . . .
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.11
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2.3 Power Supply Connections .
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.13
2.4 Power Dissipation Considerations
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.13
2.5 Layout Considerations .
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.15
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2.7 Overlap Protection and Programmable Dead Time .
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.17
2.8 Deglitch Feature
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.18
3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
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2.6 Undervoltage Lockout Operation
2.6.1 Device Startup . . . .
2.6.2 Undervoltage Lockout . .
2.6.3 Control Inputs . . . . .
2.6.4 Enable Input . . . . .
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3.1 High-Side/Low-Side Driver .
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.19
3.2 Dual Driver .
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.20
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
21
4.1 Test Circuits .
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.24
4.2 Regulatory Information (Pending).
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.25
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
5.1 Si8271 Pin Descriptions .
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.31
5.2 Si8273/75 Pin Descriptions .
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.32
5.3 Si8274 Pin Descriptions .
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.33
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
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6.1 Package Outline: 16-Pin Narrow-Body SOIC .
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.34
6.2 Package Outline: 8-Pin Narrow Body SOIC .
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6.3 Package Outline: 14-Pin DFN .
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.38
7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1 Land Pattern: 16-Pin Narrow Body SOIC .
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.39
7.2 Land Pattern: 8-Pin Narrow Body SOIC
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.40
7.3 Land Pattern: 14-Pin DFN .
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.41
8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.1 Si827x Top Marking (16-Pin Narrow Body SOIC)
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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.06 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 23, 2021
.42
5
8.2 Si8271 Top Marking (8-Pin Narrow Body SOIC) .
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.43
8.3 Si827x Top Marking (14-Pin DFN)
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.44
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.06 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 23, 2021
6
Si827x Data Sheet • System Overview
2. System Overview
VDD
VI
VDDI
ISOLATION
VDDI
VDDI
UVLO
VO+
UVLO
VO-
EN
GNDA
GNDI
Si8271
Figure 2.1. Si8271 Block Diagram
VDDI
VDDA
ISOLATION
VIA
VOA
UVLO
GNDA
OVERLAP
PROTECTION
VDDI
VDDI
VDDB
UVLO
EN
ISOLATION
VDDI
VOB
UVLO
GNDB
VIB
GNDI
Si8273
Figure 2.2. Si8273 Block Diagram
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Si827x Data Sheet • System Overview
VDDI
VDDA
ISOLATION
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
ISOLATION
VDDI
UVLO
EN
VOB
UVLO
GNDB
LPWM
GNDI
Si8274
Figure 2.3. Si8274 Block Diagram
VDDI
ISOLATION
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
EN
VDDI
VDDB
ISOLATION
UVLO
VOB
UVLO
GNDB
VIB
GNDI
Si8275
Figure 2.4. Si8275 Block Diagram
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Si827x Data Sheet • System Overview
The operation of an Si827x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of
light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A
simplified block diagram for a single Si827x channel is shown in the figure below.
Transmitter
Receiver
Driver
RF
OSCILLATOR
A
Deadtime
control
MODULATOR
VDD
SemiconductorBased Isolation
Barrier
B
DEMODULATOR
4 A peak
Gnd
Figure 2.5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See Figure 2.6 Modulation Scheme on page 9 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.6. Modulation Scheme
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Si827x Data Sheet • System Overview
2.1 Typical Operating Characteristics
The typical performance characteristics depicted in the figures below are for information purposes only. Refer to Table 4.1 Electrical
Characteristics on page 21 for actual specification limits.
10
Figure 2.7. Rise/Fall Time vs. Supply Voltage
Figure 2.8. Propagation Delay vs. Supply Voltage
Figure 2.9. Supply Current vs. Supply Voltage
Figure 2.10. Supply Current vs. Supply Voltage
Figure 2.11. Supply Current vs. Temperature
Figure 2.12. Rise/Fall Time vs. Load
Figure 2.13. Propagation Delay vs. Load
Figure 2.14. Propagation Delay vs. Temperature
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Si827x Data Sheet • System Overview
Figure 2.15. Output Sink Current vs. Temperature
Figure 2.16. Output Source Current vs. Temperature
2.2 Family Overview and Logic Operation During Startup
The Si827x family of isolated drivers consists of single, high-side/low-side, and dual driver configurations.
2.2.1 Products
The table below shows the configuration and functional overview for each product in this family.
Table 2.1. Si827x Family Overview
Part Number
Configuration
Overlap
Programmable
Protection
Dead Time
Inputs
Peak Output
Current (A)
Si8271
Single Driver
—
—
VI
4.0
Si8273
High-Side/Low-Side
Y
—
VIA, VIB
4.0
Si8274
PWM
Y
Y
PWM
4.0
Si8275
Dual Driver
—
—
VIA, VIB
4.0
2.2.2 Device Behavior
The following table consists of truth tables for the Si8273, Si8274, and Si8275 families.
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Si827x Data Sheet • System Overview
Table 2.2. Si827x Family Truth Table1
Si8271 (Single Driver) Truth Table
Inputs
VDDI State
Enable
VI
Output
Notes
VO+
VO–
L
Powered
H
Hi–Z
L
H
Powered
H
H
Hi–Z
X2
Unpowered
X
Hi–Z
L
X
Powered
L
Hi–Z
L
Si8273 (High-Side/Low-Side) Truth Table
Inputs
VDDI State
VIA
VIB
L
L
Powered
L
H
H
Enable
Output
Notes
VOA
VOB
H
L
L
Powered
H
L
H
L
Powered
H
H
L
H
H
Powered
H
L
L
Invalid state.
X2
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
X
Powered
L
L
L
Device is disabled.
Si8274 (PWM Input High-Side/Low-Side) Truth Table
PWM Input
VDDI State
Enable
Output
Notes
VOA
VOB
H
Powered
H
H
L
L
Powered
H
L
H
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
Powered
L
L
L
Device is disabled.
Si8275 (Dual Driver) Truth Table
Inputs
VDDI State
VIA
VIB
L
L
Powered
L
H
H
Enable
Output
Notes
VOA
VOB
H
L
L
Powered
H
L
H
L
Powered
H
H
L
H
H
Powered
H
H
H
X2
X2
Unpowered
X
L
L
Output returns to input state within 7 µs of VDDI power restoration.
X
X
Powered
L
L
L
Device is disabled.
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see 2.6.2 Undervoltage Lockout
for more information.
2. An input can power the input die through an internal diode if its source has adequate current.
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Si827x Data Sheet • System Overview
2.3 Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be
placed as close to the VDD and GND pins of the Si827x as possible. The optimum values for these capacitors depend on load current
and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,
are recommended.
2.4 Power Dissipation Considerations
Proper system design must assure that the Si827x operates within safe thermal limits across the entire load range.The Si827x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. The equation below shows total Si827x power dissipation.
RP
RN
PD = VDDI IDDI + 2 IDDx VDDx + f QG VDDx R + R + f QG VDDx R + R + 2 f CINTVDDx2
P
G
N
G
where:
PD is the total Si827x device power dissipation (W)
IDDI is the input-side maximum bias current (10 mA)
IDDx is the driver die maximum bias current (4 mA)
CINT is the internal parasitic capacitance (370 pF)
VDDI is the input-side VDD supply voltage (2.5 to 5.5 V)
VDDx is the driver-side supply voltage (4.2 to 30 V)
f is the switching frequency (Hz)
QG is the gate charge of the external FET
RG is the external gate resistor
RP is the RDS(ON) of the driver pull-up switch (2.7 Ω)
RN is the RDS(ON) of the driver pull-down switch (1 Ω)
Equation 1
For example, the total power dissipation for an application can be found using Equation 1 and the following application-specific values:
VDDI = 5.0 V
VDDx = 12 V
f = 350 kHz
RG = 22 Ω
QG = 25 nC
With these application-specific values, Equation 1 yields PD = 199 mW .
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Si827x Data Sheet • System Overview
The driver junction temperature is calculated using Equation 2, shown below.
T J = PD × θJ A + T A
where:
PD is the total Si827x device power dissipation (W), as determined by Equation 1.
θJA is the thermal resistance from junction to air (°C/W)
TA is the ambient temperature (°C)
Equation 2
Continuing the example above, the driver junction temperature can be determined using the result of Equation 1 and Equation 2 with
the following application-specific values:
θJA = 66 ˚C/W
TA = 20 ˚C
With these application-specific values, Equation 2 yields TJ = 33.1 ˚C.
The maximum power dissipation allowable for the Si827x, for any given application, is a function of the package thermal resistance,
ambient temperature, and maximum allowable junction temperature, as shown in Equation 3 below.
PD(MAX) ≤
T J(MAX) − T A
θJ A
where:
PD(MAX) is the maximum Si827x power dissipation (W)
TJ(MAX) is the maximum Si827x junction temperature (150 °C)
TA is the ambient temperature (°C)
θJA is the Si827x junction-to-air thermal resistance (°C/W)
Equation 3
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Si827x Data Sheet • System Overview
Continuing our example from the previous page and using the results of Equation 1 and Equation 2 as inputs to Equation 3, along with
the example values of TA and θJA previously given, yields a maximum allowable power dissipation of 1.97 W.
Maximum allowable gate charge as a function of switching frequency is found by substituting the maximum allowable power dissipation
limit and the appropriate data sheet values from Table 4.1 Electrical Characteristics on page 21 into Equation 1 and simplifying. For
our example, the result is Equation 4, which assumes VDDI = 5 V and VDDA = VDDB = 12 V, and can be easily charted to visualize
design constraints as is demonstrated by Figure 2.17 below.
QG MAX =
0.995
− 1.06 × 10−7
f
Equation 4
Maximum Gate Charge (µC)
20
15
10
5
0
100
200
300
400
500
600
Switching Frequency (kHz)
700
Figure 2.17. Maximum Gate Charge vs. Switching Frequency
2.5 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si827x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si827x as close to the device it is driving as possible. In addition, the VDD supply and
ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground
plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise
performance.
2.6 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in the Figure 2.18 on page 16, where UVLO+ and UVLOare the positive-going and negative-going thresholds respectively.
It's important to note that the driver outputs (VO) will default to a low output state when the input side power supply (VDDI) is not
present, but the output side power supply (VDDx) is present.
2.6.1 Device Startup
Driver outputs (VO) are held low during power-up until the device power supplies are above the UVLO threshold for time period tSTART.
Following this, the outputs follow the state of device inputs (VI).
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Si827x Data Sheet • System Overview
2.6.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when the device
power supplies are below their specified operating circuits range. The input (control) side, and each driver on the output side, have their
own undervoltage lockout monitors.
The Si827x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver output (VO) remains
low when the input side of the Si827x is in UVLO and VDDx is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above
VDDAUV+.
The UVLO circuit unconditionally drives VO low when VDDx is below the lockout threshold. Upon power up, the Si827x is maintained in
UVLO until VDDx rises above VDDxUV+. During power down, the Si827x enters UVLO when VDDx falls below VDDxUV–. Please refer
to spec tables for UVLO values.
UVLO+
UVLO-
VDDIHYS
VDDI
UVLO+
UVLO-
VDDxHYS
VDDA
VIA
ENABLE
tSTART
tSD
tSTART
tSTART
tSD
tRESTART
tPHL
tPLH
VOA
Figure 2.18. Device Behavior during Normal Operation and Shutdown
2.6.3 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si8274), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.6.4 Enable Input
When brought low, the ENABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device
operation terminates within tSD after ENABLE = VIL and resumes within tRESTART after ENABLE = VIH. The ENABLE input has no effect
if VDDI is below its UVLO level (i.e., VOA, VOB remain low).
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Si827x Data Sheet • System Overview
2.7 Overlap Protection and Programmable Dead Time
Overlap protection prevents the two driver outputs from both going high at the same time. Programmable dead time control sets the
amount of time between one output going low and the other output going high.
All drivers configured as high-side/low-side pairs with separate inputs (Si8273x) have overlap protection. See Figure 2.19 on page 17
and Table 2.3 on page 17. Drivers controlled with a single input (Si8274x) have inherit overlap protection by virtue of one driver being
active high and the other being active low with respect to the PWM input.
VIA
VIB
VOA
VOB
A
B
C
D
E
F
G
H
I
Figure 2.19. Input and Output Waveforms for Si8273x Drivers
Table 2.3. Description of Input and Output Waveforms for Si8273x Drivers
Reference
Description
A
Normal operation: VIA high, VIB low.
B
Normal operation: VIB high, VIA low.
C
Contention: VIA = VIB = high.
D
Recovery from contention: VIA transitions low.
E
Normal operation: VIA = VIB = low.
F
Normal operation: VIA high, VIB low.
G
Contention: VIA = VIB = high.
H
Recovery from contention: VIB transitions low.
I
Normal operation: VIB transitions high.
All high-side/low-side drivers with a single PWM input (Si8274x) include programmable dead time, which adds a user-programmable
delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions. The amount of dead time delay (DT)
is programmed by a single resistor (RDT) connected from the DT input to ground per the equation below. Note that the dead time pin
should be connected to GNDI through a resistor between the values of 6 kΩ and 100 kΩ. A filter capacitor of 100 pF in parallel with
RDT is recommended. See Figure 2.20 on page 18 below.
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Si827x Data Sheet • System Overview
DT = 2.02 × RDT + 7.77 (for 10−200 ns range)
DT = 6.06 × RDT + 3.84 (for 20−700 ns range)
where:
DT is the dead time (ns)
RDT is the dead time programming resistor (kΩ)
Equation 4
VOB
PWM
LPWM
(internal)
50%
DT
90%
VOA
10%
90%
DT
VOB
10%
Typical Dead Time Operation
Figure 2.20. Dead-Time Waveforms for Si8274x Drivers
2.8 Deglitch Feature
A deglitch feature is provided on some options, as defined in the 1. Ordering Guide. The internal deglitch circuit provides an internal
time delay of 15 ns typical, during which any noise is ignored and will not pass through the IC. For these product options, the
propagation delay will be extended by 15 ns, as specified in the spec table.
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Si827x Data Sheet • Applications
3. Applications
The following examples illustrate typical circuit configurations using the Si827x.
3.1 High-Side/Low-Side Driver
In the figure below, side A shows the Si8273 controlled using the VIA and VIB input signals, and side B shows the Si8274 controlled by
a single PWM signal.
VDD
VDDI
VDDI
C1
1 µF
D1
C1
1 µF
1500 V max
C2
0.1 µF
VDDA
1500 V max
VDDA
GNDI
CB
OUT1
VIA
OUT2
VIB
CB
Q1
VOA
PWMOUT
PWM
GNDA
Si8273
CONTROLLER
GNDA
DT
VDD
CONTROLLER
Si8274
RDT
C4
0.1 µF
C5
10 µF
I/O
GNDB
VOB
VDD
VDDB
C4
0.1 µF
ENABLE
Q1
VOA
VDDB
I/O
D1
C3
1 µF
VDDI
C2
0.1 µF
GNDI
VDD
VDDI
C3
1 µF
ENABLE
Q2
A
C5
10 µF
GNDB
VOB
Q2
B
Figure 3.1. Si827x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a
maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si827x requires
VDDI in the range of 2.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 4.2 and 30 V with respect to their
respective grounds. The boot-strap start up time will depend on the CB capacitor chosen. VDD is usually the same as VDDB. Also, note
that the bypass capacitors on the Si827x should be located as close to the chip as possible. Moreover, it is recommended that bypass
capacitors be used (as shown in the figures above for input and driver side) to reduce high frequency noise and maximize performance.
The outputs VOA and VOB can be used interchangeably as high side or low side drivers.
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Si827x Data Sheet • Applications
3.2 Dual Driver
The figure below shows the Si827x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a
common ground or to different grounds with as much as 1500 V dc between them.
VDDI
VDDI
C1
1 µF
C2
0.1 µF
Q1
VOA
GNDI
VDDA
OUT1
VIA
OUT2
VIB
VDDA
C3
0.1 µF
C4
10 µF
GNDA
CONTROLLER
Si8275
VDDB
VDDB
I/O
C5
0.1 µF
ENABLE
C6
10 µF
GNDB
VOB
Q2
Figure 3.2. Si827x in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual driver
in a high-side/low-side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can operate as a
dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes.
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Si827x Data Sheet • Electrical Specifications
4. Electrical Specifications
Table 4.1. Electrical Characteristics
VDDI = 2.5 to 5.5 V; VDDx - GNDx = 4.2 to 30 V; TA = -40 to +125 ˚C
Typical specifications at VDDI = 5 V; VDDx - GNDx = 15 V; TA = 25 ˚C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Supply Voltage
VDDI
VDDI – GNDI
2.5
—
5.5
V
Driver Supply Voltage
VDDx1
VDDx – GNDx
4.2
—
30
V
—
7.9
10.0
mA
—
8.0
10.0
mA
—
2.5
4.0
mA
—
10.0
11.0
mA
DC Parameters
Input Supply Quiescent Current
IDDQ
Input Supply Active Current
IDDI
Output Supply Quiescent Current
Output Supply Active Current
f = 500 kHz
IDDxQ2
IDDx2
f = 500 kHz (no load)
Gate Driver
High Output Transistor RDS (ON)
ROH
—
2.7
—
Ω
Low Output Transistor RDS (ΟΝ)
ROL
—
1.0
—
Ω
—
1.8
—
A
—
4.0
—
A
High Level Peak Output Current
IOH
VDDx = 15 V,
See Figure 4.2
on page 24 for
Si827xG,
VDDx = 4.2 V,
tPW_IOH < 250 ns
VDDx = 15 V,
Low Level Peak Output Current
IOL
See Figure 4.1
on page 24 for
Si827xG,
VDDx = 4.2 V,
tPW_IOL < 250 ns
UVLO
VDDI UVLO Threshold +
VDDIUV+
1.85
2.2
2.45
V
VDDI UVLO Threshold –
VDDIUV–
1.75
2.1
2.35
V
VDDI Hysteresis
VDDIHYS
—
100
—
mV
2.7
3.5
4.0
V
4.9
5.5
6.3
V
7.2
8.3
9.5
V
11
12.2
13.5
V
UVLO Threshold + (Driver Side)
3 V Threshold
5 V Threshold
8 V Threshold
12 V Threshold
VDDxUV+1
UVLO Threshold - (Driver Side)
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Si827x Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
3 V Threshold
5 V Threshold
8 V Threshold
VDDxUV-1
12 V Threshold
Min
Typ
Max
Units
2.5
3.0
3.8
V
4.6
5.2
5.9
V
6.7
7.8
8.9
V
9.6
10.8
12.1
V
—
500
—
mV
—
300
—
mV
—
500
—
mV
—
1400
—
mV
UVLO Lockout Hysteresis
3 V Threshold
5 V Threshold
8 V Threshold
VDDxHYS
12 V Threshold
Digital
Logic High Input Threshold
VIH
2.0
—
—
V
Logic Low Input Threshold
VIL
—
—
0.8
V
VHYST
350
400
—
mV
Input Hysteresis
Logic High Output Voltage
VOH
IO = –1 mA
VDDx –
0.04
—
—
V
Logic Low Output Voltage
VOL
IO = 1 mA
—
—
0.04
V
tPLH, tPHL
CL = 200 pF
20
30
60
ns
tPLH, tPHL
CL = 200 pF
30
45
75
ns
tPHL
CL = 200 pF
20
30
60
ns
tPHL
CL = 200 pF
30
45
75
ns
tPLH
CL = 200 pF
30
45
75
ns
tPLH
CL = 200 pF
65
85
105
ns
PWD
|tPLH – tPHL|
—
3.6
8
ns
PWD
|tPLH – tPHL|
—
14
19
ns
PWD
|tPLH – tPHL|
—
38
47
ns
—
200
—
ps
AC Switching Parameters
Propagation Delay
Si8271/3/5 with low jitter
Propagation Delay
Si8271/3/5 with deglitch option
Propagation Delay
Si8274 with low jitter
Propagation Delay
Si8274 with deglitch option
Propagation Delay
Si8274 with low jitter
Propagation Delay
Si8274 with deglitch option
Pulse Width Distortion
Si8271/3/5 all options
Pulse Width Distortion
Si8274 with low jitter
Pulse Width Distortion
Si8274 with deglitch option
Peak to Peak Jitter
Si827x with low jitter
22
tJIT(PK)
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Si827x Data Sheet • Electrical Specifications
Parameter
Programmed dead time (DT) for
products with 10–200 ns DT range
Programmed dead time (DT) for
products with 20–700 ns DT range
Symbol
DT
DT
Test Condition
Min
Typ
Max
RDT = 6 kΩ
10
20
30
RDT = 15 kΩ
26
38
50
RDT = 100 kΩ
150
210
260
RDT = 6 kΩ
23
40
57
RDT = 15 kΩ
60
95
130
RDT = 100 kΩ
450
610
770
Units
ns
ns
Rise time
tR
CL = 200 pF
4
10.5
16
ns
Fall time
tF
CL = 200 pF
5.5
13.3
18
ns
tSD
—
—
60
ns
tRESTART
—
—
60
ns
tSTART
—
16
30
µs
200
350
400
kV/µs
150
300
400
kV/µs
Shutdown Time from
Enable False
Restart Time from
Enable True
Device Startup Time
Common Mode Transient
Immunity
CMTI
See Figure 4.3 on
page 25.
Si827x with deglitch option
VCM = 1500 V
Common Mode Transient
Immunity
See Figure 4.3 on
page 25.
Si827x with low jitter option
CMTI
VCM = 1500 V
Notes:
1. The symbols VDD, VDDA and VDDB all refer to the driver supply voltage, but reflect the different pin names used for the supply
on different product options. Specifications that apply to the driver supply voltage are also referred to as VDDx in this data sheet.
2. The symbols IDD, IDDA and IDDB all refer to the driver supply current, but reflect the different pin names used for the supply on
different product options. Specifications that apply to the driver supply current are also referred to as IDDx in this data sheet.
23
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Si827x Data Sheet • Electrical Specifications
4.1 Test Circuits
The figures below depict sink current, source current, and common-mode transient immunity test circuits.
VDDI
VDDx
Schottky
Input
IN
Gate Driver
1 µF
GND
Measure
10 Ω
OUT
100 µF
8V
15 V
5.5 V
15 V
50 ns
VDDI
1 µF
CER
GND
R SNS
0.1 Ω
10 µF
EL
200 ns
Input Waveform
Figure 4.1. IOL Sink Current Test Circuit
VDDI
VDDx
Schottky
Input
IN
Gate Driver
1 µF
GND
Measure
10 Ω
OUT
100 µF
50 ns
VDDI
GND
1 µF
CER
10 µF
EL
R SNS
0.1 Ω
200 ns
Input Waveform
Figure 4.2. IOH Source Current Test Circuit
24
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Si827x Data Sheet • Electrical Specifications
Supply
Gate Driver
VDDI
INPUT
5V
Isolated
Supply
Input Signal
Switch
VOA
GNDA
EN
100 kΩ
12 V
VDDA
VDDB
DT
Oscilloscope
VOB
GNDI
GNDB
Isolated
Ground
Input
High Voltage
Differential Probe
Output
VCM Surge
Output
High Voltage
Surge Generator
Figure 4.3. Common Mode Transient Immunity Test Circuit
4.2 Regulatory Information (Pending)
Table 4.2. Regulatory Information1,2
CSA
The Si827x is certified under CSA. For more details, see Master Contract Number 232873.
60950-1: Up to 125 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si827x is certified according to VDE 0884-10. For more details, see Certificate 40018443.
VDE 0884-10: Up to 630 Vpeak for basic insulation working voltage.
UL
The Si827x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic protection.
CQC
The Si827x is certified under GB4943.1-2011. For more details, see Certificates CQC 16001160284 and CQC 17001177887.
Rated up to 250 VRMS basic insulation working voltage.
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
2. For more information, see 1. Ordering Guide.
25
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Si827x Data Sheet • Electrical Specifications
Table 4.3. Insulation and Safety-Related Specifications
Parameter
Nominal External Air Gap
Symbol
Test Condition
Value
Unit
SOIC-8
NB SOIC-16
DFN-14
CLR
4.7
4.7
3.5
mm
CPG
3.9
3.9
3.5
mm
DTI
0.008
0.008
0.008
mm
600
600
600
V
(Clearance)
Nominal External Tracking
(Creepage)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
PTI or CTI
IEC60112
Erosion Depth
ED
0.019
0.019
0.021
mm
Resistance
RIO
1012
1012
1012
Ω
0.5
0.5
0.5
pF
3.0
3.0
3.0
pF
(Input-Output)1
Capacitance
CIO
f = 1 MHz
(Input-Output)1
Input Capacitance2
CI
Notes:
1. To determine resistance and capacitance, the Si827x is converted into a 2-terminal device. All pins on side 1 are shorted to
create terminal 1, and all pins on side 2 are shorted to create terminal 2. The parameters are then measured between these two
terminals.
2. Measured from input pin to ground.
Table 4.4. IEC 60664-1 Ratings
Parameter
Basic Isolation Group
Installation Classification
26
Test Condition
Specification
SOIC-8
NB SOIC-16
DFN-14
Material Group
I
I
I
Rated Mains Voltages < 150 VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages < 300 VRMS
I-III
I-III
I-III
Rated Mains Voltages < 400 VRMS
I-II
I-II
I-II
Rated Mains Voltages < 600 VRMS
I-II
I-II
I-II
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Si827x Data Sheet • Electrical Specifications
Table 4.5. VDE 0884 Insulation Characteristics1
Parameter
Symbol
Maximum Working Insulation Voltage
Input to Output Test Voltage
Test Condition
Characteristic
Unit
630
V peak
VIORM
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1181
V peak
Transient Overvoltage
VIOTM
t = 60 sec
4000
V peak
Surge Voltage
VIOSM
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
3077
Vpeak
Tested with 4000 V
Pollution Degree
2
(DIN VDE 0110, Table 1)
Insulation Resistance at
RS
Ω
>109
TS, VIO = 500 V
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si827x provides a climate classification of 40/125/21.
Table 4.6. IEC Safety Limiting Values1
Parameter
Symbol
Safety
Temperature
TS
Safety Input Current
ΙS
Test Condition
115 °C/W (SOIC-8),
θJA =
SOIC-8
NB
SOIC-16
DFN-14
Unit
150
150
150
°C
36
63
38
mA
1.1
1.2
1.2
W
66 °C/W (NB SOIC-16),
110˚ C/W (DFN-14),
Device Power Dissipation
PD
VDDI =
5.5 V
VDDx =
30 V
TJ =
150 °C
TA =
25 °C
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in the two figures below.
27
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Si827x Data Sheet • Electrical Specifications
Table 4.7. Thermal Characteristics
Parameter
Symbol
SOIC-8
NB
DFN-14
Unit
110
°C/W
SOIC-16
IC Junction-to-Air
Thermal Resistance
θJA
115
66
Safety Limiting Current (mA)
40
VDDx = 30 V
30
20
10
0
0
25
50
75
100
125
Ambient Temperature (˚C)
150
Figure 4.4. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values per VDE
Safety Limiting Current (mA)
80
VDDx = 30 V
60
40
20
0
0
25
50
75
100
125
Ambient Temperature (˚C)
150
Figure 4.5. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values per VDE
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Si827x Data Sheet • Electrical Specifications
Safety Limiting Current (mA)
40
VDDx = 30 V
30
20
10
0
0
25
50
75
100
125
Ambient Temperature (˚C)
150
Figure 4.6. DFN-14 Thermal Derating Curve, Dependence of Safety Limiting Values per VDE
29
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Si827x Data Sheet • Electrical Specifications
Table 4.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Units
TSTG
–65
+150
°C
Operating Temperature
TA
–40
+125
°C
Junction Temperature
TJ
—
+150
°C
Input-side supply voltage
VDDI
–0.6
6.0
V
Driver-side supply voltage
VDD, VDDA, VDDB
–0.6
36
V
Voltage on any input pin with respect to ground
VI, VIA, VIB, EN, DT
–0.5
VDD + 0.5
V
VO+, VO-, VOA, VOB
–0.5
VO+, VO-, VOA, VOB
–1.2
VDD + 0.5
V
—
4.0
A
Lead Solder Temperature (10 s)
—
260
°C
HBM Rating ESD
—
3.5
kV
CDM
—
2000
V
Maximum Isolation Voltage (Input to Output) (1 sec)
—
3000
VRMS
—
3000
VRMS
—
1500
VRMS
—
650
VRMS
—
400
kV/μs
Storage Temperature
Voltage on any input pin with respect to ground2
Transient for 200 ns
Peak Output Current (tPW = 10 µs, duty cycle = 0.2%)
IOPK
NB SOIC-16 and SOIC-8
Maximum Isolation Voltage (Input to Output) (1 sec)
DFN-14
Maximum Isolation Voltage (Output to Output) (1 sec)
NB SOIC-16
Maximum Isolation Voltage (Output to Output) (1 sec)
DFN-14
Latch-up Immunity
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions specified in the operational sections of this data sheet.
2. Transient voltage pulse repeatable at 200 kHz.
30
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Si827x Data Sheet • Pin Descriptions
5. Pin Descriptions
5.1 Si8271 Pin Descriptions
VI
1
8
VDD
VDDI
2
7
VO+
GNDI
3
6
VO-
EN
4
5
GND
Si8271
Figure 5.1. Pin Assignments Si8271
Table 5.1. Si8271 Pin Descriptions
31
Pin
Name
Description
1
VI
2
VDDI
Input side power supply
3
GNDI
Input side ground
4
EN
5
GND
Driver side ground
6
VO–
Gate drive pull low
7
VO+
Gate drive pull high
8
VDD
Driver side power supply
Digital driver control signal
Enable
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Si827x Data Sheet • Pin Descriptions
5.2 Si8273/75 Pin Descriptions
VIA
1
16
VDDA
VIB
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
EN
5
NC
Si8273
Si8275
12
NC
6
11
VDDB
NC
7
10
VOB
VDDI
8
9
1
VIA 2
VIB 3
GNDI 4
EN 5
NC
NC
VDDI
Si8273
Si8275
6
7
14
13
12
11
VDDA
VOA
GNDA
NC
10 VDDB
9 VOB
8 GNDB
GNDB
Figure 5.2. Pin Assignments Si8273/5
Table 5.2. Si8273/5 Pin Descriptions
32
NB SOIC-16 Pin #
DFN-14 Pin #
Name
Description
1
2
VIA
Digital driver control signal for “A” driver
2
3
VIB
Digital driver control signal for “B” driver
3,8
7
VDDI
Input side power supply
4
4
GNDI
Input side ground
5
5
EN
Enable
6, 7, 12, 13
1, 6, 11
NC
No Connect
9
8
GNDB
10
9
VOB
11
10
VDDB
Driver side power supply for “B” driver
14
12
GNDA
Driver side power supply for “A” driver
15
13
VOA
16
14
VDDA
Driver side power supply for “B” driver
Gate drive output for “B” driver
Gate drive output for “A” driver
Driver side power supply for “A” driver
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Si827x Data Sheet • Pin Descriptions
5.3 Si8274 Pin Descriptions
PWM
1
16
VDDA
NC
2
15
VOA
VDDI
3
14
GNDA
GNDI
4
13
NC
EN
5
12
NC
NC 1
PWM 2
NC 3
GNDI 4
EN 5
DT
6
11
VDDB
VDDI
NC
7
10
VOB
VDDI
8
9
Si8274
DT
Si8274
6
7
14
13
12
11
VDDA
VOA
GNDA
NC
10 VDDB
9 VOB
8 GNDB
GNDB
Figure 5.3. Pin Assignments Si8274
Table 5.3. Si8274 Pin Descriptions
33
NB SOIC-16 Pin #
DFN-14 Pin #
Name
Description
1
2
PWM
2, 7, 12, 13
1, 3, 11
NC
3, 8
7
VDDI
Input side power supply
4
4
GNDI
Input side ground
5
5
EN
Enable
6
6
DT
Dead-time control
9
8
GNDB
10
9
VOB
11
10
VDDB
Driver side power supply for “B” driver
14
12
GNDA
Driver side power supply for “A” driver
15
13
VOA
16
14
VDDA
Pulse width modulated driver control signal
No Connect
Driver side power supply for “B” driver
Gate drive output for “B” driver
Gate drive output for “A” driver
Driver side power supply for “A” driver
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Si827x Data Sheet • Package Outlines
6. Package Outlines
6.1 Package Outline: 16-Pin Narrow-Body SOIC
The figure below illustrates the package details for the Si827x in a 16-pin narrow-body SOIC (SO-16). The table below lists the values
for the dimensions shown in the illustration.
Figure 6.1. 16-pin Small Outline Integrated Circuit (SOIC) Package
34
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Si827x Data Sheet • Package Outlines
Table 6.1. Package Diagram Dimensions
Dimension
Min
Max
Dimension
Min
Max
A
—
1.75
L
0.40
1.27
A1
0.10
0.25
L2
A2
1.25
—
h
0.25
0.50
b
0.31
0.51
θ
0°
8°
c
0.17
0.25
aaa
0.10
0.25 BSC
D
9.90 BSC
bbb
0.20
E
6.00 BSC
ccc
0.10
E1
3.90 BSC
ddd
0.25
e
1.27 BSC
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si827x Data Sheet • Package Outlines
6.2 Package Outline: 8-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si827x in an 8-pin narrow-body SOIC package. The table below lists the values
for the dimensions shown in the illustration.
α
Figure 6.2. 8-Pin Narrow Body SOIC Package
36
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Si827x Data Sheet • Package Outlines
Table 6.2. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
37
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
∝
0°
8°
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Si827x Data Sheet • Package Outlines
6.3 Package Outline: 14-Pin DFN
The figure below illustrates the package details for the Si827x in an DFN outline. The table below lists the values for the dimensions
shown in the illustration.
Figure 6.3. Si827x 14-pin DFN Outline
Table 6.3. Package Diagram Dimensions
Dimension
MIN
NOM
MAX
A
0.74
0.85
0.90
A1
0
—
0.05
b
0.25
0.30
0.35
D
4.90
5.00
5.10
e
E
0.65 BSC
4.90
E1
5.00
5.10
3.60 REF
L
0.50
0.60
0.70
L1
0.05
0.10
0.15
ccc
—
—
0.08
ddd
—
—
0.10
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Si827x Data Sheet • Land Patterns
7. Land Patterns
7.1 Land Pattern: 16-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si827x in a 16-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 7.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si827x Data Sheet • Land Patterns
7.2 Land Pattern: 8-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si827x in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.2. 8-Pin Narrow Body SOIC Land Pattern
Table 7.2. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si827x Data Sheet • Land Patterns
7.3 Land Pattern: 14-Pin DFN
The figure below illustrates the recommended land pattern details for the Si827x in a 14-pin DFN. The table below lists the values for
the dimensions shown in the illustration.
Figure 7.3. 14-Pin DFN Land Pattern
Table 7.3. 14-Pin DFN Land Pattern Dimensions
Dimension
(mm)
C1
4.20
E
0.65
X1
0.80
Y1
0.40
Notes:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si827x Data Sheet • Top Markings
8. Top Markings
8.1 Si827x Top Marking (16-Pin Narrow Body SOIC)
Table 8.1. Top Marking Explanation (16-Pin Narrow Body SOIC)
Si827 = ISOdriver product series
Y = Configuration
3 = High-side/Low-side (HS/LS)
4 = PWM HS/LS
5 = Dual driver
U = UVLO level
G=3V
Base Part Number
Ordering Options
Line 1 Marking:1
A=5V
B=8V
D = 12 V
See 1. Ordering Guide for
more information.
V = Isolation rating
B = 2.5 kV
W = Dead-time setting range
none = not included
1= 10-200 ns
4 = 20-700 ns
X = Integrated deglitch circuit
none = not included
D = integrated
YY = Year
WW = Workweek
Line 2 Marking:
TTTTTT = Mfg Code
Assigned by the Assembly House. Corresponds to the year and workweek
of the mold date.
Manufacturing Code from Assembly Purchase Order form.
The Manufacturing Code represented by “TTTTTT” contains, as its first
character, a letter in the range N through Z to indicate Automotive-Grade.
Note:
1. Characters W and/or X are optional and may be missing from the marking line. When missing, the remaining characters are
right-justified on the marking line.
42
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42
Si827x Data Sheet • Top Markings
8.2 Si8271 Top Marking (8-Pin Narrow Body SOIC)
Table 8.2. Top Marking Explanation (Narrow Body SOIC)
Si827 = ISOdriver product series
Y = Configuration
1 = Single driver
U = UVLO level
G=3V
Line 1 Marking:
Customer Part Number
A=5V
B=8V
D = 12 V
V = Isolation rating
A = 1 kVRMS
B = 2.5 kVRMS
W = Dead-time setting range
none = not included
1= 10-200 ns
WX = Ordering options
Line 2 Marking:1
4 = 20-700 ns
X = Integrated deglitch circuit
none = not included
D = integrated
YY = Year
WW = Work week
Line 3 Marking:
TTTTTT = Mfg code
Assigned by the Assembly House. Corresponds to the year and workweek
of the mold date.
Manufacturing Code from Assembly Purchase Order form.
The Manufacturing Code represented by “TTTTTT” contains, as its first
character, a letter in the range N through Z to indicate Automotive-Grade.
Note:
1. Characters W and/or X are optional and may be missing from the marking line. When missing, the remaining characters are
right-justified on the marking line.
43
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Si827x Data Sheet • Top Markings
8.3 Si827x Top Marking (14-Pin DFN)
Table 8.3. Top Marking Explanation (14-Pin DFN)
Si827 = ISOdriver product series
Base Part Number
Line 1 Marking:
Ordering Options
See 1. Ordering Guide for
more information.
Y = configuration
3 = High-side/Low-side (HS/LS)
4 = PWM HS/LS
5 = Dual driver
U = UVLO level
G=3V
A=5V
B=8V
D = 12 V
V = Isolation rating
A = 1 kVRMS
Line 2 Marking:1
Ordering Options
B = 2.5 kVRMS
W = Dead-time setting range
none = not included
1= 10-200 ns
4 = 20-700 ns
X = Integrated deglitch circuit
none = not included
D = integrated
Line 3 Marking:
Line 4 Marking:
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order form.
The Manufacturing Code represented by “TTTTTT” contains, as its first
character, a letter in the range N through Z to indicate Automotive-Grade.
Circle = 1.5 mm diameter
Pin 1 identifier.
YYWW
Manufacturing date code.
Note:
1. Characters W and/or X are optional and may be missing from the marking line. When missing, the remaining characters are
right-justified on the marking line.
44
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Si827x Data Sheet • Revision History
9. Revision History
Revision 1.06
April, 2021
• Added automotive-grade ordering part numbers to 1. Ordering Guide.
Revision 1.05
September, 2020
• Added Si8271GB-AS to 1. Ordering Guide.
Revision 1.04
May, 2020
• Adjusted industrial ordering guide to group by isolation rating.
• Added 8 new OPNs rated at 1 kVRMS to the Table 1.1 on page 2.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added Si8273GB-IM1 to Table 1.1 on page 2.
Added footnotes section to Table 1.1 on page 2 and appropriate footnotes.
Removed duplicate Si8273BB-IS1 line in the Table 1.1 on page 2.
The QFN package was renamed to DFN throughout the document and pin count naming was unified with SOIC packages.
Updated and unified style and naming conventions throughout the document.
Edited CQC basic working voltage rating from 600 V to 250 V and removed the reinforced working voltage rating in Table 4.2 on
page 25.
Edited Table 4.8 on page 30 and clarified negative transient tolerance specification.
Edited the Top Marking Explanation tables in 8. Top Markings and added a footnote clarifying how optional characters are represented.
Removed "component notice 5A" from CSA certification descriptions in Table 4.2 on page 25.
Added "-2011" to CQC certification descriptions in Table 4.2 on page 25.
Corrected Dead-Time Adjustable Range on Si8274DB1-AS1 to 10-100 ns in Table 1.1 on page 2.
Updated diagrams in 2. System Overview to improve readability.
Updated application diagrams in 3. Applications to improve readability and to follow updated naming conventions.
Corrected IC Junction-to-Air Thermal Resistance (ØJA) specifications for all packages in Table 4.7 on page 28.
• Clarified Figure 4.1 on page 24, Figure 4.2 on page 24, and Figure 4.3 on page 25.
• Updated thermal derating curves, power dissipation example, and safety input current specifications and test conditions for all
packages based on new ØJA specifications.
• Added a new thermal derating curve for the DFN-14 package (Figure 4.6 on page 29) based on the new ØJA specification.
•
•
•
•
•
•
Clarified, reorganized, and updated the 2.4 Power Dissipation Considerations section.
Figure 6.3 on page 38 and Table 6.3 on page 38 were edited and clarified.
Footnote 3 was removed from Table 6.3 on page 38.
Removed the single driver option from Line 1 Marking row in Table 8.3 on page 44
Reorganized and clarified 2.7 Overlap Protection and Programmable Dead Time
Clarified conditions for typical specifications in Table 4.1 Electrical Characteristics on page 21
Revision 1.03
October, 2019
• Added Si8275BB-AS1 and Si8275GB-AS1 to Ordering Guide for Automotive Grade OPNs.
Revision 1.02
June, 2019
• Updated Table 1.1 Si827x Ordering Guide1, 2, 3 on page 2.
Revision 1.01
April, 2019
• Added Si8271AB-AS and Si8274BB4D-AS1 to Ordering Guide for Automotive Grade OPNs.
45
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Si827x Data Sheet • Revision History
Revision 1.0
May, 2018
• Replaced references and descriptions of LGA package with QFN package throughout the data sheet.
• Updated OPNs with LGA package denoted by -IM suffix to QFN packages denoted by -IM1 suffix in the Ordering Guide.
• Added Si8274DB1-AS1 OPN to Ordering Guide for Automotive Grade OPNs.
• Added Note 6 to Ordering Guide for Automotive Grade OPNs referring to Top Markings for Automotive Grade parts.
• Updated Equation 3 and the chart generated by Equation 3 in Figure 2.17 Max Load vs. Switching Frequency on page 15.
• Corrected power dissipation example calculations in Power Dissipation Considerations.
• Updated Package Outline: 14 LD QFN with new QFN package outline drawing and updated Table 6.3 Package Diagram Dimensions
on page 38 with QFN package dimensions.
• Updated Table 4.2 Regulatory Information on page 25 with certification information.
• Updated Table 4.3 Insulation and Safety-Related Specifications on page 26 symbols and clarified parameters.
• Added Surge Voltage specification to Table 4.5 VDE 0884 Insulation Characteristics on page 27.
• Updated description of Figure 4.5 NB SOIC-16, QFN-14 Thermal Derating Curve on page 28 and Figure 4.4 NB SOIC-8 Thermal
Derating Curve on page 28.
Revision 0.6
December, 2017
• Updated Figure 2.12 Rise/Fall Time vs. Load on page 10.
• Updated Table 4.1 Electrical Characteristics on page 21.
• Added "(no load)" under IDDx specification test condition.
• Added tSD and tRESTART specs.
• Corrected storage temp and power dissipation for SOIC-8 package in Table 4.6 IEC Safety Limiting Values1 on page 27.
• Added footnote about VO+ and VOA/VOB voltages with respect to ground in Table 4.8 Absolute Maximum Ratings 1 on page 30 with
improvement from other pins.
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 0.5
February, 2016
• Initial release.
46
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