Si834x Data Sheet
Isolated Smart Switch
KEY FEATURES
The Si834x provides four isolated high-side or low-side switches with low RON. These switches
are ideal for driving resistive and inductive loads like solenoids, relays, and lamps commonly
found in industrial control systems like Programmable Logic Controllers (PLC). Each switch is
galvanically isolated for safety using Skyworks’ groundbreaking CMOS-based isolation technology, offering better reliability and performance than the traditional optocoupler-based isolation,
including high Common-Mode Transient Immunity (CMTI) over 100 kV/µs.
The logic interface supports low-power 2.25 V MCUs, while the switches offer a wide supply
range of 9 V – 32 V ideal for industrial voltage levels. The switches are capable of providing
0.7 A depending on load conditions. Each switch offers complete fault protection. An innovative
multi-voltage clamp efficiently handles an unlimited amount of demagnetization energy (EAS).
The over-current protection includes an Inrush Current Mode to drive loads like lamps. Additionally, the device power supplies are monitored, and the switches are safely constrained or
shutdown on faults.
Eight diagnostics are reported through the logic interface, offering an unprecedented level of
details and control. Diagnostics are configured, monitored, and cleared via the Serial Peripheral Interface (SPI) or exposed on active-low, open-drain indicator pins for easy access and
combination. Diagnostic communication is independent of switch control signals, with separate
isolation channels and constant error checking, ensuring long-term reliability.
Safety Approvals (Pending)
• UL 1577 recognized: Up to 1500 Vrms for 1 minute
• CSA certified under: IEC 60950-1, 62368-1
• VDE certification conformity: VDE 0884-10
• CQC certification approval: GB4943.1
Applications
• Programmable logic controllers
• Industrial data acquisition
• Motion controllers
• Smart solid-state relays
• High-side or low-side switch
• Logic Supply: 2.25 V – 5.5 V
• Switch Supply: 9 V – 32 V
• Fast (10 µs) update rate
• High continuous current (700 mA)
and low RON (145 mΩ)
• Unique multi-voltage output clamp
• Unlimited demagnetization (EAS)
• Efficient and fast turn-OFF
• Inrush Current Mode: 8 A for 20 ms
• Current-limited overload protection
• Over-temperature protection
• Undervoltage protected supplies
• Up to 8 different diagnostics
• Multiple power supply reports
• Over-current, over-temperature
• Open-circuit warning
• Communication error
• Channel status indicators
• Dedicated fault indicator
• Disable outputs asynchronously
• Control 128 channels via SPI
• 1.5 kVRMS safety rated isolation
NC
GND2
A1
DNC
A1
DNC
GND2
A2
VDD2
A3
B1
A4
VDD2
OE
NSS
SCLK
MOSI
VDD2
GND1
FLT
VDD1
GND1
VDD2_WRN
VDD2
LED1
Sensors &
GND2
LED2
Protection
VDD2
LED3
DNC
LED4
NC
GND2
Si83408AFA-IF
6x Receivers/
1x Transmitter
B3
B4
MISO
1
VDD2
B1
4x Low-Side Switches
GND1
MOSI_THRU
Status & Diagnostics
VDD1
B2
GND2
Isolation Barrier
FLT
6x Receivers/
1x Transmitter
GND1
Isolation Barrier
6x Transmitters/
1x Receiver
OE
VDD2
6x Transmitters/
1x Receiver
A4
Status & Diagnostics
A3
4x High-Side Switches
A2
4x Input Interface
GND2
4x Input Interface
NC
GND2
• Transient immunity > 100 kV/μs
• Compliant to IEC 61131-2
• Compact 9x9 DFN-32 package
• 5 kV ESD Protection
• -40 – 125 ˚C operating temperature
B2
GND2
B3
GND2
B4
GND2
Sensors &
Protection
VDD2
VDD2
DNC
NC
GND2
Si83414AAA-IF
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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1
Si834x Data Sheet • Ordering Guide
1. Ordering Guide
Table 1.1. Si834x Ordering Guide
Ordering Part
Number
Output1
Switch
Type
Input2
Interface
Output
Channels
Continuous
Output
Current
Channel
Status
Indicators
Low
Voltage
Indicator
Open
Channel
Indicator
Clear
Fault
Input
Yes
No
No
No
No
No
No
No
No
Yes
No
No
No
No
No
No
No
No
No
Yes
No
No
No
Yes
No
Yes
No
No
No
Yes
Iso.
Rating
Products Available Now
Si83404AAA-IF
Si83408ADA-IF
Parallel
Sourcing
SPI
Si83408AFA-IF
Parallel/
SPI
Si83414AAA-IF
Parallel
Si83418ADA-IF
Sinking
SPI
Yes
4
0.7 A
No
Yes
4
0.7 A
Parallel/
SPI
Si83418AFA-IF
No
1.5
kVrms
Contact Skyworks Sales for These Options
Si83404ABA-IF
Si83404ACA-IF
Si83414ABA-IF
Si83414ACA-IF
Sourcing
Sinking
Parallel
Parallel
4
4
0.7 A
0.7 A
Yes
Yes
1.5
kVrms
Note:
1. Output switch can source current in a high-side, open-source configuration or sink current in a low-side, open-drain configuration.
2. SPI provides access to all diagnostic, configuration, and channel status information. Devices without a parallel interface allow
output channel control through the SPI as well.
3. "Si" and "SI" are used interchangeably.
4. An "R" at the end of the Ordering Part Number indicates tape and reel option.
2
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2
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Truth Tables .
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. 7
3.2 Switch Timing Behavior .
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.12
3.3 Switch Types
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.13
3.4 Switch Protection . . . . . . . . . . . . .
3.4.1 Demagnetization Energy Protection . . . . .
3.4.2 Over-Current Protection with Inrush Current Mode
3.4.3 Over-Temperature Protection. . . . . . . .
3.4.4 Power Supply Protection . . . . . . . . .
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.13
.14
.15
.18
.20
3.5 Diagnostics and Monitoring . . . .
3.5.1 Power Supply Diagnostics. . .
3.5.2 Over-Temperature Diagnostics .
3.5.3 Over-Current Diagnostics . . .
3.5.4 Open-Circuit Diagnostics . . .
3.5.5 Communication Error Diagnostics
3.5.6 Channel Status Monitoring . .
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.23
.24
.25
.26
.27
.27
.28
3.6 Serial Peripheral Interface . . . .
3.6.1 SPI Register Map . . . . .
3.6.2 SPI Communication Transactions
3.6.3 SPI Read Operation . . . . .
3.6.4 SPI Write Operation . . . . .
3.6.5 SPI Daisy Chain Organization .
3.6.6 SPI Timing Behavior . . . .
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.28
.29
.32
.33
.33
.34
.35
4. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . .
36
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4.1 Recommended Application Circuits . . . . . . . . . . .
4.1.1 Isolated Switch with Parallel Inputs and Diagnostic Indicators .
4.1.2 Isolated High-Side Switch with Parallel Inputs and Fault Control
4.1.3 Isolated High-Side Switch with SPI . . . . . . . . . .
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.36
.36
.38
.39
4.2 Layout Considerations .
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.41
4.3 Power Dissipation Considerations
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.42
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
44
5.1 Typical Operating Characteristics .
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.54
6. Pin and Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . .
59
6.1 Pin Descriptions
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.59
6.2 Package Drawing .
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.63
6.3 Land Pattern.
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.65
6.4 Top Marking .
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.66
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7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Revision 0.5 .
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.67
4
Si834x Data Sheet • System Overview
2. System Overview
A single channel of the Si834x Isolated Smart Switch is analogous to that of an optocoupler and a relay driver, except that an RF
carrier is modulated across the isolation barrier instead of light. This simple architecture provides a robust isolation path and requires
no special considerations or initialization at startup. The RF carrier is modulated using methods that optimize fault tolerance and
propagation delay across the isolation barrier.
Switch
Control
4 Parallel Channels
Figure 2.1. Parallel/SPI Sourcing Device System Diagram
The fundamental channel structure described above is augmented using a number of innovative technologies. The output switch is a
low ON-State Resistance (RON) device capable of driving inductive and resistive loads at continuous currents of 700 mA. It includes
precise voltage, current, and temperature sensors that continuously monitor the switch and load conditions, protecting the device by
reducing driver performance or forcing a controlled shutdown when necessary.
The switch uses a sophisticated multi-voltage output clamp, called a “smart output clamp”, that both protects the switch from harmful
inductive kickback voltage (or back EMF) while still offering fast demagnetization of inductors to reduce contact arcing and increase
switching speed.
Four identical channels are packaged together into an Si834x device, each with its own set of sensors. Switches are controlled using
dedicated isolation channels which increase reliability and timing performance. A bidirectional, fault-tolerant isolation channel is also
implemented between the switch and logic interface, allowing the host controller to configure, monitor, and diagnose the switches and
their loads.
The logic interface offers dedicated parallel input channels and an asynchronous output enable (OE) pin for high speed switch control
as well as a rich SPI for diagnostics and monitoring. Eight different diagnostic reports are available in the device status registers
accessed via SPI which provide a complete picture of device and load condition. See Diagnostics and Monitoring for more information
on the available reports.
5
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Si834x Data Sheet • System Overview
Switch
Control
4 Parallel Channels
Figure 2.2. SPI Sourcing Device System Diagram
The true status of each switch output is communicated across the isolation barrier to the logic interface and can be monitored by the
controller through the status registers. On some product options, such as the one depicted in the figure above, the channel status is
also indicated by open-drain, active-low LED output pins that can quickly provide end-user feedback on switch status.
Switch
Control
4 Parallel Channels
Figure 2.3. Parallel Interface Device System Diagram
The Si834x is also offered without the SPI to simplify designs and provide an easy migration path from existing optocoupler-based
solutions, as illustrated in the figure above. Depending on the device selection, different switch diagnostics are exposed using additional
indicator pins, such as a switch supply voltage low indicator (VDD2_WRN\).
6
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Si834x Data Sheet • Device Operation
3. Device Operation
This section describes the capabilities of the Si834x Isolated Smart Switch devices and how they should be used to achieve different
goals within a design. Refer to the Ordering Guide and Recommended Application Circuits for information on each device and how they
are designed into different applications.
3.1 Truth Tables
The following tables describe the logical behavior of the Si834x Isolated Smart Switch devices. Use these tables to determine the state
of a specific channel's outputs on a specific Si834x device, based on the device's current and past state, and its current inputs. The
state of other device channels also impacts some channel output states. When applicable, this is described in the table's footnotes.
Table 3.1. Si834xxxAx Truth Table
Mode
Fault
Normal
Inputs1
State2
Outputs
An
OE
VDD1Q3
VDD2Q4
VDD2Q-14
FaultQ5
VDD2_WRN\6, 7
FLT\6
LEDn\6
Bn8
X
X
NP
–
–
–
OFF
U
OFF
OFF
X
X
P
NP
NP
D
OFF
ON
OFF
OFF
X
X
P
NP
W
D
ON
ON
OFF
OFF
X
X
P
W
–
D
ON
ON
OFF9
OFF9
X
X
P
P
–
D
OFF
ON
OFF9
OFF9
L
X
P
W
–
ND
ON
OFF
OFF
OFF
X
L
P
W
–
ND
ON
OFF
OFF
OFF
H
H
P
W
–
ND
ON
OFF
ON
ON
L
X
P
P
–
ND
OFF
OFF
OFF
OFF
X
L
P
P
–
ND
OFF
OFF
OFF
OFF
H
H
P
P
–
ND
OFF
OFF
ON
ON
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Logic values listed in this table are assumed to transition at the same time as the device state.
2. "NP" is the "not powered" state, "P" is the "powered" state, "W" is the "warning" state, "ND" is the "not detected" state, "D" is
the detected state, and "–" is an irrelevant state. The current state (Q) and the previous state (Q-1) of the device, as well as the
current inputs to the device, define the current outputs of the device.
3. "Not powered" (NP) state is defined as VDD1 < VDD1UV. "Powered" (P) state is defined as VDD1 > VDD1UV. Logic inputs can
power VDD1 through an internal diode if its source has adequate current. See Power Supply Characteristics for details.
4. "Not powered" (NP) state is defined as VDD2 < VDD2UV9. "Warning" (W) state is defined as VDD2UV9 < VDD2 < VDD2UV18.
"Powered" (P) state is defined as VDD2 > VDD2UV18. See Power Supply Characteristics and Protection and Diagnostics for
details.
5. The VDD2Q "not powered" (NP) state forces a FaultQ "detected" state. FaultQ state automatically changes to "not detected" (ND)
when all fault conditions are removed. Faults are defined in Diagnostics and Monitoring.
6. "Undetermined" (U) can be any value within the absolute maximum rating of the output. The output is both active-low and
open-drain. See Recommended Application Circuits for more information.
7. VDD2 must remain within a state long enough to be measured for this output to change. If VDD2 changes states sufficiently
quickly, this output will remain unchanged. See Diagnostics and Monitoring for more information.
8. The electrical characteristics for ON and OFF vary based on device selection, switch protection conditions, and switch supply
conditions. See Switch Types and Switch Protection for more information.
9. If an Over-Temperature Constraint fault is detected while the output is ON, the output will not immediately shut-down. If an
Over-Temperature Constraint fault is detected while the output is OFF, the output will be prevented from turning ON. If an
Overvoltage Constraint fault is detected, the output will operate normally. See Switch Protection for more information.
7
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Si834x Data Sheet • Device Operation
Table 3.2. Si834xxxBx Truth Table
Mode
Fault
Normal
Inputs1
State2
An OE VDD1Q3 VDD2Q4
Outputs
VDD2Q-14
FaultQ5
Bn LoadQ
Bn LoadQ-1
OPEN_CH\6, 7
FLT\6
LEDn6
Bn8
X
X
NP
–
–
–
–
–
OFF
U
OFF
OFF
X
X
P
NP
NP
D
–
–
OFF
ON
OFF
OFF
X
X
P
NP
P
D
–
ND
ON
ON
OFF
OFF
X
X
P
P
–
D
ND
–
ON
ON
OFF9
OFF9
X
X
P
P
–
D
D
–
OFF
ON
OFF9
OFF9
L
X
P
P
–
ND
ND
–
ON
OFF
OFF
OFF
X
L
P
P
–
ND
ND
–
ON
OFF
OFF
OFF
L
X
P
P
–
ND
D
–
OFF
OFF
OFF
OFF
X
L
P
P
–
ND
D
–
OFF
OFF
OFF
OFF
H
H
P
P
–
ND
–
–
OFF
OFF
ON
ON
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Logic values listed in this table are assumed to transition at the same time as the device state.
2. "NP" is the "not powered" state, "P" is the "powered" state, "ND" is the "not detected" state, "D" is the detected state, and "–" is an
irrelevant state. The current state (Q) and the previous state (Q-1) of the device, as well as the current inputs to the device, define
the current outputs of the device.
3. "Not powered" (NP) state is defined as VDD1 < VDD1UV. "Powered" (P) state is defined as VDD1 > VDD1UV. Logic inputs can
power VDD1 through an internal diode if its source has adequate current. See Power Supply Characteristics for details.
4. "Not powered" (NP) state is defined as VDD2 < VDD2UV9. "Powered" (P) state is defined as VDD2 > VDD2UV9. See Power
Supply Characteristics for details.
5. The VDD2Q "not powered" (NP) state forces a FaultQ "detected" state. FaultQ state automatically changes to "not detected" (ND)
when all fault conditions are removed. Faults are defined in Diagnostics and Monitoring.
6. "Undetermined" (U) can be any value within the absolute maximum rating of the output. The output is both active-low and
open-drain. See Recommended Application Circuits for more information.
7. All channels are assumed to have the same load state. A "not detected" (ND) load state on any channel will turn ON this output.
The load must remain within a state long enough to be measured for this output to change. If the load changes state sufficiently
quickly, this output will remain unchanged. See Diagnostics and Monitoring for more information.
8. The electrical characteristics for ON and OFF vary based on device selection, switch protection conditions, and switch supply
conditions. See Switch Types and Switch Protection for more information.
9. If an Over-Temperature Constraint fault is detected while the output is ON, the output will not immediately shut-down. If an
Over-Temperature Constraint fault is detected while the output is OFF, the output will be prevented from turning ON. If an
Overvoltage Constraint fault is detected, the output will operate normally. See Switch Protection for more information.
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Si834x Data Sheet • Device Operation
Table 3.3. Si834xxxCx Truth Table
Mode
Fault
Normal
Inputs1
State2
Outputs
An
OE
FLT_CLR
VDD1Q3
VDD2Q4
FaultQ5
FaultQ-15
FLT\6
LEDn\6
Bn7
X
X
X
NP
–
–
–
U
OFF
OFF
X
X
X
P
NP
D
–
ON
OFF
OFF
X
X
X
P
P
D
–
ON
OFF8
OFF8
L
X
L
P
P
ND
D
ON
OFF
OFF
X
L
L
P
P
ND
D
ON
OFF
OFF
H
H
L
P
P
ND
D
ON
ON9
ON9
L
X
H
P
P
ND
D
OFF
OFF
OFF
X
L
H
P
P
ND
D
OFF
OFF
OFF
H
H
H
P
P
ND
D
OFF
ON
ON
L
X
X
P
P
ND
ND
OFF
OFF
OFF
X
L
X
P
P
ND
ND
OFF
OFF
OFF
H
H
X
P
P
ND
ND
OFF
ON
ON
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Logic values listed in this table are assumed to transition at the same time as the device state.
2. "NP" is the "not powered" state, "P" is the "powered" state, "ND" is the "not detected" state, "D" is the detected state, and "–" is an
irrelevant state. The current state (Q) and the previous state (Q-1) of the device, as well as the current inputs to the device, define
the current outputs of the device.
3. "Not powered" (NP) state is defined as VDD1 < VDD1UV. "Powered" (P) state is defined as VDD1 > VDD1UV. Logic inputs can
power VDD1 through an internal diode if its source has adequate current. See Power Supply Characteristics for details.
4. "Not powered" (NP) state is defined as VDD2 < VDD2UV9. "Powered" (P) state is defined as VDD2 > VDD2UV9. See Power
Supply Characteristics for details.
5. The "detected" (D) state will persist as a previous state (Q-1) until the current fault state (Q) is "not detected" (ND) and the
FLT_CLR input is high. Faults are defined in Diagnostics and Monitoring.
6. "Undetermined" (U) can be any value within the absolute maximum rating of the output. The output is both active-low and
open-drain. See Recommended Application Circuits for more information.
7. The electrical characteristics for ON and OFF vary based on device selection, switch protection conditions, and switch supply
conditions. See Switch Types and Switch Protection for more information.
8. If an Over-Temperature Constraint fault is detected while the output is ON, the output will not immediately shut-down. If an
Over-Temperature Constraint fault is detected while the output is OFF, the output will be prevented from turning ON. If an
Overvoltage Constraint fault is detected, the output will operate normally. See Switch Protection for more information.
9. If a Communication Error Shutdown fault was previously detected and is currently reported, the output will be prevented from
turning ON. See Diagnostics and Monitoring for more information.
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Si834x Data Sheet • Device Operation
Table 3.4. Si834xxxDx Truth Table
Mode
Fault
Normal
Inputs1
State3
Outputs
SW_EN[n]2
OE
VDD1Q4
VDD2Q5
FaultQ6
FLT\7, 8
LEDn\8
Bn9
X
X
NP
–
–
U
OFF
OFF
X
X
P
NP
D
ON
OFF
OFF
X
X
P
P
D
ON
OFF10
OFF10
L
X
P
P
ND
OFF
OFF
OFF
X
L
P
P
ND
OFF
OFF
OFF
H
H
P
P
ND
OFF
ON
ON
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Logic values listed in this table are assumed to transition at the same time as the device state.
2. This input is supplied via the SPI from the SW_EN register. Bit addresses are zero indexed such that channel 1 (output B1) is
supplied from the SW_EN[0] bit.
3. "NP" is the "not powered" state, "P" is the "powered" state, "ND" is the "not detected" state, "D" is the detected state, and "–" is an
irrelevant state. The current state (Q) and the previous state (Q-1) of the device, as well as the current inputs to the device, define
the current outputs of the device.
4. "Not powered" (NP) state is defined as VDD1 < VDD1UV. "Powered" (P) state is defined as VDD1 > VDD1UV. Logic inputs can
power VDD1 through an internal diode if its source has adequate current. See Power Supply Characteristics for details.
5. "Not powered" (NP) state is defined as VDD2 < VDD2UV9. "Powered" (P) state is defined as VDD2 > VDD2UV9. See Power
Supply Characteristics for details.
6. The VDD2Q "not powered" (NP) state forces a FaultQ "detected" (D) state. FaultQ state automatically changes to "not detected"
(ND) when all fault conditions are removed. Faults are defined in Diagnostics and Monitoring.
7. The default behavior shown here can be modified through the SPI. See Serial Peripheral Interface for details.
8. "Undetermined" (U) can be any value within the absolute maximum rating of the output. The output is both active-low and
open-drain. See Recommended Application Circuits for more information.
9. The electrical characteristics for ON and OFF vary based on device selection, switch protection conditions, and switch supply
conditions. See Switch Types and Switch Protection for more information.
10. If an Over-Temperature Constraint fault is detected while the output is ON, the output will not immediately shut-down. If an
Over-Temperature Constraint fault is detected while the output is OFF, the output will be prevented from turning ON. If an
Overvoltage Constraint fault is detected, the output will operate normally. See Switch Protection for more information.
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Si834x Data Sheet • Device Operation
Table 3.5. Si834xxxFx Truth Table
Mode
Fault
Normal
Inputs1
State2
Outputs
An
OE
VDD1Q3
VDD2Q4
FaultQ5
FLT\6
Bn7
X
X
NP
–
–
U
OFF
X
X
P
NP
D
ON
OFF
X
X
P
P
D
ON
OFF8
L
X
P
P
ND
OFF
OFF
X
L
P
P
ND
OFF
OFF
H
H
P
P
ND
OFF
ON
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Logic values listed in this table are assumed to transition at the same time as the device state.
2. "NP" is the "not powered" state, "P" is the "powered" state, "ND" is the "not detected" state, "D" is the detected state, and "–" is an
irrelevant state. The current state (Q) and the previous state (Q-1) of the device, as well as the current inputs to the device, define
the current outputs of the device.
3. "Not powered" (NP) state is defined as VDD1 < VDD1UV. "Powered" (P) state is defined as VDD1 > VDD1UV. Logic inputs can
power VDD1 through an internal diode if its source has adequate current. See Power Supply Characteristics for details.
4. "Not powered" (NP) state is defined as VDD2 < VDD2UV9."Powered" (P) state is defined as VDD2 > VDD2UV9. See Power Supply
Characteristics for details.
5. The VDD2Q "not powered" (NP) state forces a FaultQ "detected" (D) state. FaultQ state automatically changes to "not detected"
(ND) when all fault conditions are removed. Faults are defined in Diagnostics and Monitoring.
6. "Undetermined" (U) can be any value within the absolute maximum rating of the output. The output is both active-low and
open-drain. See Recommended Application Circuits for more information. It's default behavior shown here can be modified
through the SPI. See Serial Peripheral Interface for details.
7. The electrical characteristics for ON and OFF vary based on device selection, switch protection conditions, and switch supply
conditions. See Switch Types and Switch Protection for more information.
8. If an Over-Temperature Constraint fault is detected while the output is ON, the output will not immediately shut-down. If an
Over-Temperature Constraint fault is detected while the output is OFF, the output will be prevented from turning ON. If an
Overvoltage Constraint fault is detected, the output will operate normally. See Switch Protection for more information.
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Si834x Data Sheet • Device Operation
3.2 Switch Timing Behavior
The Si834x exhibits different timing behavior depending on the state of the power supplies, as well as the switch inputs. In the figure
below, the analog power supply voltages are plotted against the digital input and output state of the device, with relevant device timings
listed. It is important to note that the analog behavior of the Si834x device changes based on the switch type selected. See Switch
Types for details.
Startup
Normal
Operation
VDD1UV+
VDD1UV-
VDD1
Cycle
VDD2
Cycle
VDD1HYS
VDD1
VDD2HYS
VDD2UV9+
VDD2UV9VDD2
An/OE
tPC1
tST
tPHL
tPLH
tPC2
tSD1
Bn
A
B
C
D
Figure 3.1. Switch Timing Behavior
At marker A in the figure above, both power supplies, though unpowered initially, exceed the undervoltage threshold (VDD1UV and
VDD2UV9). At this point, the device begins to start up. Until the Device Startup Time (tST) elapses, the output remains off. After tST, the
output state begins to track the input state. Note that the analog timing behavior from device input to device output is depicted in Figure
5.1 on page 47.
At marker B, the input control signal is turned off. After the Turn OFF Propagation Delay (tPHL) elapses, the output will turn off. When
the input is turned back on, an additional Turn ON Propagation Delay (tPLH) must elapse before the output returns to the ON state.
At marker C, the logic interface power supply is turned completely off to begin a power cycle. When VDD1 drops below VDD1UV, the
device begins to shutdown. After the Logic Interface Shutdown Time (tSD1) elapses, the output is turned off. When VDD1 exceeds the
VDD1UV threshold again, the Logic Interface Power Cycle Time (tPC1) must elapse before the output will again track the input and turn
back on.
At marker D, the switch power supply is turned completely off to begin a power cycle. When VDD2 drops below VDD2UV9, the output
immediately turns off. When VDD2 exceeds VDD2UV9 again, the Switch Power Cycle Time (tPC2) must elapse before the output will
again track the input and turn back on.
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Si834x Data Sheet • Device Operation
3.3 Switch Types
The Si834x Isolated Smart Switch is available in two switch configurations to meet a broad range of application requirements.
VDD2
VDD2
Clamp
Control
Switch
Control
Bn
Smart
Output
Clamp
Clamp
Control
Figure 3.2. Sourcing Device
Load
Bn
Load
GND2
Smart
Output
Clamp
Switch
Control
GND2
Figure 3.3. Sinking Device
As shown in the figures above, the sourcing configuration operates as an open-source output for high-side switching. It connects to
VDD2 when the switch is turned ON. The sinking configuration uses an open-drain output for low-side switching. It connects to GND2
when the switch is turned ON. Both the sourcing and sinking output configurations are IEC61131-2 compliant. Each switch can source
or sink 700 mA of continuous current.
Additionally, the Si834x devices offer an Inrush Current Mode which can briefly provide up to 8 A of current. This is ideal for driving
loads with low startup impedance like lamps. To reliably achieve continuous currents of 700 mA, follow the circuit design and layout
recommendations in this document. See Layout Considerations and Recommended Application Circuits for details on how to design for
high continuous current devices.
All switches include a smart clamp output to quickly and safely demagnetize inductive loads, as well as advanced over-current protection, over-temperature protection, and open-circuit detection. When the switch is OFF, the output can be considered high impedance
(Hi-Z). However, the demagnetization clamp will engage in the OFF state if the voltage on the output pin exceeds the Demagnetization
Clamp High Voltage (VCLMPH) specification. Also, there will be some OFF state current (IO(OFF)) to facilitate open circuit detection. See
Figure 5.10 on page 57 and Figure 5.11 on page 58 for details on the output behavior when the switch is OFF.
3.4 Switch Protection
The Si834x Isolated Smart Switch contains sophisticated protection technology. It is designed to operate for decades driving a broad
range of loads. It can seamlessly recover from faults ranging from a simple switch supply overvoltage, to a dead short on a driven
output channel. The following sections detail individual methods of protection, and how they behave in common scenarios.
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Si834x Data Sheet • Device Operation
3.4.1 Demagnetization Energy Protection
The Si834x Isolated Smart Switch includes a high efficiency, multi-voltage “smart” output clamp used to protect the switch from harsh
demagnetization voltage, commonly referred to as back EMF, flyback voltage, inductive voltage “kick-back”, or sometimes just as a
“voltage kick.” The smart clamp is actively controlled based on the current through the switch, the switch supply voltage, and the
switch temperature. By dynamically adjusting the clamp voltage based on device and load conditions, the Si834x balances safety with
performance. It limits device power dissipation to safe levels, while still delivering fast turn-off performance that allows inductors to
switch quickly and reduces arcing and arc welding failures in relays.
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
A
B
Figure 3.4. Demagnetization Protection Behavior
The figure above illustrates the behavior of a high-side (sourcing) Si834x switch when driving an inductor at the switches’ typical ON
State Load Current (IO(ON)) and under normal operating conditions. It plots the digital input to the switch (An) as well as the output
voltage (VBn) and output current (IBn) from the switch where n is a specific channel number.
At marker A, the switch, driving a fully charged inductor, is turned off. The inductor resists a change in current by generating a very
large negative voltage at the switch output (Bn) and across the smart output clamp. Initially, because the current through the smart
clamp exceeds the Demagnetization Clamp Current Threshold (ICLMPT), the clamp voltage is constrained to the Demagnetization
Clamp Low Voltage (VCLMPL). At this clamp voltage, demagnetization occurs slowly, but power dissipation in the channel is limited to a
safe level.
At marker B, current through the clamp falls below ICLMPT and the clamp voltage is changed to Demagnetization Clamp High Voltage
(VCLMPH). The higher clamp voltage will rapidly demagnetize the inductor. The increased power dissipation during this phase of
protection will cause a small temperature rise in the channel, but with inductor current sufficiently constrained below ICLMPT, this rise is
easily tolerated by the Si834x device.
This two-step approach when turning off an inductor gives the Si834x the ability to demagnetize an unlimited amount of energy from
a single turn-off pulse, on a single channel (EAS(1CH)). See Table 5.12 on page 53 for maximum energy dissipation under other
conditions.
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Si834x Data Sheet • Device Operation
3.4.2 Over-Current Protection with Inrush Current Mode
The Si834x Isolated Smart Switch includes short-circuit-proof, over-current protection with automated restart. Unlike other over-currentprotected switches, the Si834x rapidly samples current through the switch, disabling the output while an over-current condition remains
present, rather than depending on an increased switch resistance and thermal protection alone to limit current through the switch. This
approach drastically reduces the power dissipation through the switch during an over-current condition, eliminating the need for thermal
independence of separate channels, increasing the lifespan of the switch, simplifying the thermal requirements of the end-system, and
still ensuring safe operation of the switch even with a dead short present for an indefinite amount of time.
The Si834x devices also include an Inrush Current Mode, which enables them to drive loads with low startup impedance like lamps by
providing a brief high current when the channel is initially turned on.
Short-Circuit
An
VBn
IOPCL
tOPCT
tOCPD
tOCLP
tOPRD
tOPRD
IOCL
tOCL
tOCL
IBn
OC_SDn
A
B
C
D E
Figure 3.5. Over-Current Shutdown Behavior
The figure above illustrates the behavior of a high-side (sourcing) Si834x switch when driving an inductor at the switches’ typical
ON State Load Current (IO(ON)) under normal operating conditions initially, but then experiencing a short-circuit. Note that marker B
depicts the Si834x switches’ behavior when it is turned on in a short-circuit state. The figure plots the digital input to the switch (An)
as well as the output voltage (VBn) and output current (IBn) from the switch where n is a specific channel number. It also illustrates
the Over-Current Shutdown diagnostic register value for the channel (OC_SDn) when the enable mask for auto-clearing of diagnostics
(ACLR_EN) is set to true. This is the default diagnostic report clearing behavior.
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Si834x Data Sheet • Device Operation
Initially, the switch channel is turned on and the load inductor is fully charged. The current must exceed the Output Current Limit
Threshold (IOCLT), which is similar to the Output Current Limit (IOCL) in the figure above, for the switch to detect an over-current
condition and engage its over-current protection. At marker A, a dead short (0 Ω resistance) is placed on the output to the switch
channel which causes an immediate voltage drop and current rise well above IOCLT. The Si834x device will immediately engage
its over-current protection and limits the current to the Output Current Limit (IOCL) by altering the resistance of the switch. If the
over-current condition is not removed within the Output Current Limit Pulse time (tOCL), the output is immediately shutdown and
OC_SDn is set to true. The channel will remain shutdown for the duration of the Over-Current Protection Retry Delay (tOPRD).
At marker B, after the Over-Current Protection Retry Delay has expired, OC_SDn is set to false, and the channel is turned on again.
If the over-current condition is once again detected on the output, the resistance of the switch will once again be altered to limit the
current to IOCL for no longer then tOCL, at which point the channel will shut down again, protecting itself from high power dissipation.
The switch will attempt to turn on again in the same way, multiple times, at a retry period equal to Output Current Limit Period (tOCLP),
and for up to the Over-Current Protection Duration (tOCPD). If the over-current condition is no longer detected at any time during an
Over Current Limit Pulse, the switch resistance is immediately reduced to normal ON-State Output Resistance (RON).
At marker C, the Si834x tests the load to determine if it requires high inrush current for normal operation. The current limit is increased
to Output Peak Current Limit (IOPCL), and the pulse time is reduced to Output Peak Current Test Pulse (tOPCT). See the figure below
for details on switch behavior when driving a load that requires a high inrush current. In the case of a short-circuit or other over-current
condition that cannot be resolved with high inrush current, after tOPCT passes, the output is shutdown again for tOPRD, and OC_SDn is
set to true. This cycle will repeat indefinitely as long as the over-current condition remains detected.
At marker D, the dead short is removed. However, during the time the channel is shutdown, no changes in the over-current condition
are detected. This is true for any period of time the channel is shutdown. Therefore, the channel remains shutdown until tOCLP expires,
at which time the channel is turned on, and normal operation resumes.
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Si834x Data Sheet • Device Operation
An
VBn
IOPCL
tOCPD
tOCLP
IOCL
tOCL
tOPCL
IBn
A
B
C
Figure 3.6. Inrush Current Mode Behavior
The figure above illustrates the behavior of a high-side (sourcing) Si834x switch when driving a load that requires a high inrush current
such as an incandescent lamp. The figure plots the digital input to the switch (An) as well as the output voltage (VBn) and output current
(IBn) from the switch where n is a specific channel number.
At marker A, the channel is turned on and the current through the switch is immediately detected above the Output Current Limit
Threshold (IOCLT), which engages the over-current protection and limits the current to the Output Current Limit (IOCL). See Figure 3.5 on
page 15 for details on typical over-current protection.
At marker B, similar to the over-current condition depicted in Figure 3.5 on page 15, the Si834x switch alters its resistance to allow for
a higher Output Peak Current Limit (IOPCL). Unlike the over-current condition, if the current through the switch remains less than IOPCL,
the switch will maintain the increased current limit for a time up to the Output Peak Current Limit Pulse (tOPCL). The current through
the switch must reduce to a level below IOCLT, which is similar to IOCL depicted in the figure above, before tOPCL passes. Otherwise,
the channel is deemed to be in an over-current state, at which time it is shutdown and Over-Current Shutdown diagnostic register
(OC_SDn) is set to true.
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Si834x Data Sheet • Device Operation
3.4.3 Over-Temperature Protection
The Si834x Isolated Smart Switch includes independent over-temperature protection for each channel. It has two levels of protection
that balance device safety with switch performance. The Si834x will continue to operate safely with reduced performance when
individual channels are over-temperature, only shutting down channels when all channels are detected to be over-temperature.
TOT
Normal Operation
(TBn < TOT)
OT Event
(TBn ≥ TOT)
OT Event
THYS
(TBn±1 ≥ TOT)
TB(ANY)
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
OT_CNSn
A
B C
D E
F
Figure 3.7. Over-Temperature Constraint Behavior
The figure above illustrates the behavior of a high-side (sourcing) Si834x switch when driving an inductor at the switches’ typical ON
State Load Current (IO(ON)), but then experiencing two different over-temperature events (OT Event). The "Normal Operation" section is
identical to Figure 3.4 on page 14 and is included for reference. The figure plots the digital input to the switch (An), the temperature of
any output channel (TB(ANY)), as well as the output voltage (VBn) and output current (IBn) from the switch where n is a specific channel
number. It also illustrates the Over-Temperature Constraint diagnostic register value for the channel (OT_CNSn) when the enable mask
for auto-clearing of diagnostics (ACLR_EN) is set to true. This is the default diagnostic report clearing behavior.
Under normal conditions where ambient temperature is limited to the Derated Ambient (TAD), calculated in Power Dissipation Considerations, the most likely cause of over-temperature is demagnetizing a large inductor (EAS). Specifically, when the smart clamp is set to
the Demagnetization Clamp High Voltage (VCLMPH) and power dissipation is at its peak. This temperature rise is illustrated in the figure
above at marker A for an EAS, which falls below the maximum specification of the device. See Table 5.12 on page 53 for more details
on the absolute maximum specifications.
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Si834x Data Sheet • Device Operation
Marker B illustrates the switch behavior when the dissipated EAS is too large for the current ambient temperature. When the Si834x
smart clamp transitions to VCLMPH, the switch temperature rises quickly until it reaches the Over-Temperature Threshold (TOT) at
marker C. At this point, the smart clamp for each Si834x channel is constrained to the Demagnetization Clamp Low Voltage (VCLMPL),
and OT_CNSn is set to true. This protects the device by reducing power dissipation and forcing all inductors attached to the Si834x to
demagnetize more slowly.
While the Si834x is over-temperature on any channel, all channels are prevented from turning on in order to further reduce power
dissipation and recover quickly, as illustrated at marker D. Note that a channel in inrush current mode, or experiencing an Over-Current
Shutdown will also have it's retry attempts suppressed during its Over-Current Protection Duration (tOCPD) period. Once the temperature of the channel falls below the Over-Temperature Hysteresis (THYS) level, as illustrated by marker E, OT_CNSn is set to false, and
all channels resume normal operation.
It is important to note that an over-temperature condition on any channel will cause all channels to be constrained in the manner described above, not just the channel with the over-temperature diagnostic report. This is illustrated at marker F where a different channel,
not illustrated, exceeds TOT, forcing the illustrated channel to remain at VCLMPL and constraining its demagnetization performance.
Normal Operation
Over-Temperature
TOT
THYS
TB(ALL)
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
OT_SD
A
B C
Figure 3.8. Over-Temperature Shutdown Behavior
If ambient temperature is not limited to TAD, or if EAS is much larger than the specified maximum, it is possible that the temperature
of all channels (TB(ALL)) will exceed TOT, as illustrated in the figure above. In this event, as illustrated at marker A, all channels are
immediately shutdown, and the Over-Temperature Shutdown register (OT_SD) will be set to true. If a channel is driving an inductor, the
smart clamp will be constrained to VCLMPL and demagnetization time will be increased to help reduce power dissipation. All channels
will be prevented from turning on (marker B) until the temperature of all channels falls below THYS, as depicted at marker C, at which
time the OT_SD register will be set to false and all channels will resume normal operation.
19
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Si834x Data Sheet • Device Operation
3.4.4 Power Supply Protection
The Si834x Isolated Smart Switch monitors both the logic interface and switch power supplies, protecting the device and load when
the power supplies are out of specification. Like the over-temperature protection, the Si834x balances performance with safety by
constraining switch performance under some power supply conditions, and safely shutting down under others.
Normal Operation
Overvoltage
VDD2OV32+
VDD2OV32VDD2
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
VDD2_OS
A
B
C
Figure 3.9. VDD2 Overvoltage Constraint Behavior
The figure above illustrates the behavior of a high-side (sourcing) Si834x switch when driving an inductor at the switches’ typical
ON State Load Current (IO(ON)), but then experiences an overvoltage condition on the switch power supply (VDD2). The "Normal
Operation" section is identical to Figure 3.4 on page 14 and is included for reference. The figure plots the digital input to the switch
(An), the VDD2 supply voltage (VDD2), as well as the output voltage (VBn) and output current (IBn) from the switch where n is a specific
channel number. It also illustrates the VDD2 Out of Specification register value (VDD2_OS) when the enable mask for auto-clearing of
diagnostics (ACLR_EN) is set to true. This is the default diagnostic report clearing behavior.
At marker A, VDD2 exceeds the VDD2 Overvoltage Threshold (VDD2OV32). In order to reduce power dissipation to a safe level, the
smart clamp for each channel is constrained to Demagnetization Clamp Low Voltage (VCLMPL), and the VDD2_OS register is set to
true. While the smart clamp for each channel is limited to VCLMPL, demagnetization performance is constrained and all inductive loads
turn off more slowly, as illustrated at marker B. Unlike an Over-Temperature Constraint, the output channels are not prevented from
turning on (marker C). Once VDD2 falls below VDD2OV32 again, the smart clamp returns to "Normal Operation", and the VDD2_OS
register is set back to false.
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Si834x Data Sheet • Device Operation
It is important to note that overvoltage is not prevented from damaging the device if VDD2 remains above VDD2OV32 or exceeds the
absolute maximum specification. It only protects the device from higher power dissipation when demagnetizing an inductive load at
higher voltages, and generates a diagnostic report. If VDD2 exceeds the VDD2 ESD Clamp Threshold (VDD2CLMP), the VDD2 ESD
clamp will engage, damaging the device.
Normal Operation
Undervoltage
VDD2
VDD2UV9+
VDD2UV9-
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
VDD2_OS
A
B
C
Figure 3.10. VDD2 Undervoltage Shutdown Behavior
The switch is protected against a VDD2 undervoltage condition in a very similar manner to VDD2 overvoltage conditions, as illustrated
by the figure above. At marker A, VDD2 falls below the VDD2 Undervoltage Threshold (VDD2UV9). All channels are immediately
shutdown, and the VDD2_OS register is set to true. Note that the smart clamp operates normally during shutdown. While VDD2 is
undervoltage, all channels are prevented from turning on (marker B). Only after VDD2 rises above VDD2UV9 again will all channels be
allowed to return to normal operation, and the VDD2_OS register set back to false, as illustrated at marker C.
It is important to note that VDD2 must remain powered to offer undervoltage protection in the manner described above. If VDD2
is completely unpowered (0 V), the smart clamp voltage is not well defined. Also, the Master Diagnostic register (MASTER_DIAG)
may not accurately report the VDD2 state. In this condition, if the switch is undamaged, the Communication Error register value
(COMM_ERR) will be set to true, denoting a loss of communication with the unpowered switch. Finally, when power is restored to
VDD2, the device must wait for VDD2 Switch Power Cycle Time (tPC2) to pass before normal operation will resume. See Switch Timing
Behavior for details.
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Si834x Data Sheet • Device Operation
Normal Operation
Undervoltage
VDD1
VDD1UV+
VDD1UV-
An
VBn
VCLMPL
VCLMPH
ICLMPT
IBn
FLT
A
B
C
Figure 3.11. VDD1 Undervoltage Shutdown Behavior
The logic interface is also protected against a VDD1 undervoltage condition in the same way as VDD2, illustrated by the figure above.
Unlike the VDD2 undervoltage condition, the VDD1 undervoltage condition is only reported on the FLT\ pin, not through a diagnostic
register. Like the VDD2 undervoltage protection, all channels are immediately shutdown when VDD1 falls below VDD1 Undervoltage
Threshold (VDD1UV), as illustrated at marker A. All channels are prevented from turning on while VDD1 remains undervoltage (marker
B), and normal operation immediately resumes when VDD1 rises above VDD1UV, as illustrated by marker C.
Like VDD2 undervoltage protection, VDD1 must remain powered to offer undervoltage protection in the manner described above. If
VDD1 is completely unpowered (0 V), the FLT\ pin may be in an undetermined state and may show a logic high value if connected to
VDD1 through a pull-up resistor. When power is restored to VDD1, the device must wait for VDD1 Logic Interface Cycle Time (tPC1) to
pass before normal operation will resume. See Switch Timing Behavior for details.
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Si834x Data Sheet • Device Operation
3.5 Diagnostics and Monitoring
The Si834x Isolated Smart Switch communicates rich diagnostic and monitoring information to the host controller including the
condition of the load, power supplies, and built-in protection. Eight separate diagnostic reports are available, as well as channel status
reports.
Table 3.6. Diagnostics Overview
Scope
Per Channel
Diagnostic
Severity1
Open-Circuit
Warning
Over-Current
Shutdown
Channel is overloaded. Output is immediately turned off.
Constraint
Channel is too hot. Inductors demagnetize slowly. Output will not turn back on.
Shutdown
All channels are too hot. All outputs are immediately turned off.
Over-Temperature
All Channels
Description
Channel has no load detected. Output is operating normally.
VDD2 is under VDD2UV18. All outputs operating normally.
VDD2 Low-Voltage
Warning
VDD2 Overvoltage
Constraint
VDD2 is over VDD2OV32. Inductors demagnetize slowly.
VDD2 Undervoltage
Shutdown
VDD2 is over VDD2UV9. All outputs are turned off.
VDD1 Undervoltage
Shutdown
VDD1 is under VDD1UV. All outputs are turned off.
Communication Error
Shutdown
Communication across the isolation barrier is lost. All outputs are turned off.
Note:
1. Diagnostics with a severity of "Constraint" or "Shutdown" are defined as faults and exposed on the FLT\ output. The configuration
for FLT\ can be modified using the SPI, if available. See Serial Peripheral Interface for details.
Diagnostics and monitoring information is reported in different ways depending on the device selected (see the Ordering Guide for
device options.) Devices with the SPI allow access to all diagnostic and monitoring information via diagnostic registers. One active-low,
open-drain indicator pin (FLT\) is available on SPI devices and provides immediate diagnostic report feedback to the user, or can be
used as a fast diagnostic interrupt for the controller. The diagnostic reports exposed on this indicator pin are configurable via the SPI.
By setting a true value in the Fault Enable Mask (FLT_EN) register at the desired diagnostic’s bit field, the indicator pin will be turned
ON when the corresponding diagnostic report is true. See Serial Peripheral Interface for more details.
Devices without the SPI have a fixed configuration and expose diagnostics and monitoring information on active-low, open-drain
indicator pins only. These pins can drive an LED to provide end-user feedback, they can be combined with a pull-up resistor and read
by the controller, or multiple pins can be combined to simplify diagnostics and monitoring across devices. Like SPI devices, an FLT\
indicator pin is always provided. It is configured to report any diagnostic which represents an abnormal switch behavior. This is also the
default configuration for SPI devices. Contact Skyworks for custom device configurations not available in the Ordering Guide.
A diagnostic report can be cleared from the Si834x device once the condition that caused the report is removed from the device. If
a report is cleared while the condition remains, a new report will be automatically generated. See Switch Protection for details on the
conditions that cause diagnostic reports.
For SPI devices, all diagnostics are set to have their reports automatically cleared when the conditions that caused the report are
removed. However, this can be controlled for each diagnostic, except for the VDD1 Undervoltage Shutdown diagnostic, through the
Automatic Diagnostic Clear Enable Mask (ACLR_EN) register. If a bit field in this enable mask is set to false, the corresponding
diagnostic report will remain until it is cleared by setting a true value in the Clear Diagnostic (CLR_DIAG) register at the corresponding
diagnostic’s bit field.
It is important to note that the operation of an output channel is not affected by the presence of a diagnostic report. For example, if the
device is not configured to automatically clear a diagnostic report, then the diagnostic report will persist after the condition that caused
the report is removed. Once the condition that caused the report is removed, the channel will resume normal operation regardless of
diagnostic report state. The Communication Error diagnostic is an exception to this behavior. See Communication Error Diagnostic for
details.
For parallel interface only devices, a device with a Clear Fault Input pin (Si834xxxCx) is required to manually clear diagnostic reports on
the FLT\ pin. It operates the same way as setting a true value in the CLR_DIAG register for all diagnostics. All other parallel interface
only devices are configured to automatically clear diagnostic reports when the conditions that caused the report are removed.
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Si834x Data Sheet • Device Operation
3.5.1 Power Supply Diagnostics
The Si834x Isolated Smart Switch offers complete power supply diagnostics for both power supplies, including overvoltage, low-voltage, and undervoltage conditions.
Table 3.7. Switch Power Supply Diagnostics
MASTER_DIAG[5:4]
Output Behavior4
VDD2_OS
VDD2_
LOW
Switch
Clamps
Supply Voltage1
FLT\2
VDD2_
WRN\3
VDD2 Voltage OK
VDD2UV18 < VDD2 < VDD2OV32
̶
OFF
0
0
Normal
Normal
VDD2 Low-Voltage Warning
VDD2UV9 < VDD2 < VDD2UV18
̶
ON
0
1
Normal
Normal
VDD2 Overvoltage Constraint
VDD2 > VDD2OV32
ON
OFF
1
0
Normal
VCLMP =
VCLMPL
VDD2 Undervoltage Shutdown
VDD2 < VDD2UV9
ON
ON5
15
15
Turns OFF
Normal
Diagnostic
Note:
1. Supply voltage must remain within this voltage range long enough to be measured for a change to be reported. If supply voltage
changes sufficiently quickly, the diagnostic state will remain unchanged.
2. The output is both active-low and open-drain. "–" denotes that this diagnostic does not turn on the output, but other diagnostics
might. The default configuration for FLT\ is depicted, but can be modified using the SPI, if available. See Serial Peripheral
Interface for details.
3. The output is both active-low and open drain. It is only available on specific product offerings. See the Ordering Guide for more
details.
4. Behavior assumes only the defined diagnostic condition is present. Exceptions to normal behavior due to a fault are defined here.
See Switch Protection for more information. Clamp behavior applies to all smart output clamps, for all channels.
5. If the supply is unpowered, this value may not be accurately reported. Assuming there is no damage to the device, a
COMM_ERR (MASTER_DIAG bit 7 = 1) will also be reported when VDD2 is unpowered and can be queried via the SPI. See
Switch Protection for more information.
The table above describes the switch power supply diagnostic reports, where they are reported by default, and provides a brief
overview of how the output behavior changes with each report. Note that the two bit fields in the Master Diagnostic register (MASTER_DIAG[5:4]) can be read separately or as a two-bit field. If read separately, bit 5 reports when VDD2 voltage is out of device
specifications and the output behavior is abnormal. Bit 4 simply reports a warning when VDD2 voltage is low. If read as a two-bit field,
all four possible power supply states can be discerned.
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Si834x Data Sheet • Device Operation
Table 3.8. Logic Interface Power Supply Diagnostics
Supply Voltage1
FLT\2
VDD1 Voltage OK
VDD1 > VDD1UV
VDD1 Undervoltage Shutdown
VDD1 < VDD1UV
Diagnostic
Output Behavior3
Switch
Clamps
–
Normal
Normal
ON
Turns OFF
Normal
Note:
1. Supply voltage must remain within this voltage range long enough to be measured for a change to be reported. If supply voltage
changes sufficiently quickly, the diagnostic state will remain unchanged.
2. The output is both active-low and open-drain. "–" denotes that this diagnostic does not turn on the output, but other diagnostics
might.
3. Behavior assumes only the defined diagnostic condition is present. Exceptions to normal behavior due to a fault are defined here.
See Switch Protection for more information. Clamp behavior applies to all smart output clamps, for all channels.
The table above describes the undervoltage shutdown diagnostic report for the logic interface power supply, where it is reported, and
provides a brief overview of how the output behavior changes with the report. A VDD1 Undervoltage Shutdown is only reported on the
FLT\ pin and has no corresponding SPI register entry. If VDD1 is completely unpowered (0 V), the FLT\ output is in an unknown state.
A short glitch may be observed on the FLT\ pin when it is connected to VDD1 via a pull-up resistor, until the logic interface is powered.
See Switch Protection for more details.
3.5.2 Over-Temperature Diagnostics
The Si834x Isolated Smart Switch reports over-temperature in different levels of severity allowing the controller to take different actions
depending on how the switch output behavior is changing.
Table 3.9. Over-Temperature Diagnostics
Diagnostic
Temperature OK
Over-Temperature Constraint
Over-Temperature Shutdown
Switch
Temperature1
Channels
FLT\2
OT_SD
OT_CNSn3
TBn < TOT
Any Channel
–
0
Any Channel
ON
All Channels
ON
TBn > TOT
Output Behavior4
Switch
Clamps
0
Normal
Normal
0
1
Stays OFF
VCLMP = VCLMPL
1
1
Turns OFF
VCLMP = VCLMPL
Note:
1. Channel must remain above this temperature long enough to be measured for a change to be reported. If the temperature
changes sufficiently quickly, the diagnostic state will remain unchanged.
2. The output is both active-low and open-drain. "–" denotes that this diagnostic does not turn on the output, but other diagnostics
might. The default configuration for FLT\ is depicted, but can be modified using the SPI, if available. See Serial Peripheral
Interface for details.
3. Reported in Diagnostic registers (DIAG), depending on the channel. See Serial Peripheral Interface for details.
4. Behavior assumes only the defined diagnostic condition is present. Exceptions to normal behavior due to a fault are defined here.
See Switch Protection for more information. Clamp behavior applies to all smart output clamps, for all channels.
The table above describes the over-temperature diagnostic reports, where they are reported by default, and provides a brief overview of
how the output behavior changes with each report. An Over-Temperature Constraint is reported in the Diagnostic (DIAG) registers on a
per-channel basis where n, in OT_CNSn, describes the specific channel that has exceeded the Over-Temperature Threshold (TOT). An
Over-Temperature Shutdown is reported in the MASTER_DIAG SPI register in bit field OT_SD when all channels have exceeded TOT.
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Si834x Data Sheet • Device Operation
3.5.3 Over-Current Diagnostics
The Si834x Isolated Smart Switch reports over-current diagnostics on a per-channel basis so the controller can take action on a specific
channel without disrupting operation on other channels.
Table 3.10. Over-Current Diagnostics
Diagnostic
Current OK
Over-Current Shutdown
An or
SW_EN[n]1
Output Current
FLT\2
OC_SDn3
L
–
–
H
IBn < IOCLT
H
IBn > IOCLT
Output Behavior4
Switch
Clamp
0
Normal
Normal
–
0
Normal
Normal
ON
1
Turns OFF
Normal
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Bit addresses are zero-indexed such that channel 1 (output B1) is enabled by the SW_EN[0] bit.
2. The output is both active-low and open-drain. "–" denotes that this diagnostic does not turn on the output, but other diagnostics
might. The default configuration for FLT\ is depicted, but can be modified using the SPI, if available. See Serial Peripheral
Interface for details.
3. Reported in Diagnostic registers (DIAG), depending on the channel. See Serial Peripheral Interface for details.
4. Behavior assumes only the defined diagnostic condition is present. Exceptions to normal behavior due to a fault are defined here.
See Switch Protection for more information.
The table above describes the over-current diagnostic report, where it is reported by default, and provides a brief overview of how
the output behavior changes with the report. An Over-Current Shutdown can only be reported when the channel input is high (true).
Over-Current Shutdown is reported in the Diagnostic (DIAG) registers on a per-channel basis where n, in OC_SDn, describes the
specific channel that has exceeded the Output Current Limit Threshold (IOCLT).
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Si834x Data Sheet • Device Operation
3.5.4 Open-Circuit Diagnostics
The Si834x Isolated Smart Switch can detect and report an open-circuit on each switch channel allowing the controller to easily detect
the condition of individual loads.
Table 3.11. Open-Circuit Diagnostic
Diagnostic
Open-Circuit Undetected
Open-Circuit Warning
An or
SW_EN[n]1
Load
Resistance2
OPEN_CH\3
OPEN_WRNn4
H
–
OFF
L
RL < RLMAX
L
RL > RLMAX
Output Behavior5
Switch
Clamp
0
Normal
Normal
OFF
0
Normal
Normal
ON
1
Normal
Normal
Note:
1. "X" is any logic value, "H" is a logic high (true) value, and "L" is a logic low (false) value. Logic pins should always be connected
to either logic high or low. Bit addresses are zero-indexed such that channel 1 (output B1) is enabled by the SW_EN[0] bit.
2. "–" denotes that load resistance RL is not measured. Open-Circuit is only detected during channel OFF.
3. The output is both active-low and open drain. It is only available on specific product offerings. See the Ordering Guide for more
details.
4. Reported in Diagnostic registers (DIAG), depending on the channel. See Serial Peripheral Interface for details.
5. Behavior assumes only the defined diagnostic condition is present. Exceptions to normal behavior due to a fault are defined here.
See Switch Protection for more information.
The table above describes the open-circuit diagnostic report, where it is reported by default, and provides a brief overview of how
the output behavior changes with the report. An Open-Circuit Warning can only be reported when the channel input is low (false).
Open-Circuit Warning is reported in the Diagnostic (DIAG) registers on a per-channel basis where n, in OPEN_WRNn, describes the
specific channel with a load resistance that exceeds the Load Resistance Threshold for Open-Circuit Diagnostic (RLMAX).
3.5.5 Communication Error Diagnostics
The Si834x Isolated Smart Switch includes a bidirectional communication channel between the logic interface and the switch, across
the isolation barrier. This communication channel is used for diagnostics, monitoring, and reporting. The channel input signals, which
turn switches on and off are sent across the isolation barrier using their own dedicated unidirectional isolation channels to maximize
reliability and performance.
The bidirectional diagnostic and configuration channel is continually monitored for faults or loss of communication from both the logic
interface and the switch, like a bidirectional communication channel watchdog. If any error or loss of communication is detected by
either the logic interface or the switch, a Communication Error (COMM_ERR) is reported in the Master Diagnostic (MASTER_DIAG)
register, and the switches are safely shut down until the error is cleared. Unlike other diagnostic reports, when a Communication Error
induces a diagnostic report, the outputs will be immediately disabled. All outputs will remain disabled until the Communication Error
condition is removed and the diagnostic report is cleared.
If the switch is damaged or completely unpowered (VDD2 = 0 V), the logic interface will set COMM_ERR to true and disable all switch
outputs. Likewise, if the logic interface is damaged or completely unpowered (VDD1 = 0 V), the switch will disable all switch outputs. In
this way, the switch is ensured to never operate unless bidirectional communication is continually verified and both logic interface and
switch appear in good condition.
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Si834x Data Sheet • Device Operation
3.5.6 Channel Status Monitoring
The Si834x Isolated Smart Switch simplifies end-user feedback by providing active-low, open-drain, output channel status indicator pins
(LEDn) on select product options (see Ordering Guide for details.) The channel status indicator pins are on the logic interface side of
the device and protected by the isolation barrier. Moreover, by implementing channel status indicators on the low-voltage logic interface,
the power consumed by the indicator circuits is lower then an equivalent circuit on the high-voltage switch side of the device. This
design choice also maximizes the current supplied to a load from the switches.
The LEDn pins show the same information as the Switch Status (SW_STAT) register, not the Switch Enable (SW_EN) register, which
is equivalent to the parallel input (An) signals. This distinction is important. By indicating the switch status, the indicators will reflect the
true output state, not just the output state commanded by the host controller.
For example, using a device with the SPI and channel status indicators (like the Si83408ADA-IF), if the controller attempts to turn on
the B1 switch by setting the SW_EN1 bitfield to true but the output is in an over-current condition, B1 will instead shut-down (see Switch
Protection for details.) In this scenario, the SW_STAT1 bit will be set to false and LED1 will turn OFF. If the over-current condition is
removed and the B1 switch recovers and turns ON, the LED1 will immediately turn ON as well.
3.6 Serial Peripheral Interface
The Si834x includes a Serial Peripheral Interface (SPI) on select product options. It provides diagnostics, monitoring, and configuration
capabilities for both the switch and logic interface. The direct-mapped registers allow an external master SPI controller to monitor
the status of the switches, collect and clear diagnostic reports, configure how the switches operate, and how reports are indicated.
Additionally, support is provided to easily daisy-chain up to thirty-two Si834x devices. Each of these daisy-chained devices may be
uniquely addressed by one master SPI controller.
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Si834x Data Sheet • Device Operation
3.6.1 SPI Register Map
The addressable SPI registers are listed below and include descriptions for each field or bit.
Table 3.12. Si834x SPI Register Map
Register Name
SPI
Address
Read/ Reset
Write Value
Description
Master diagnostic register
MASTER_DIAG
0x0
R
8'h0
7 COMM_ERR
Communication Error (all channels shutdown)
6 OT_SD
All Channels Over-Temperature (all channels shutdown)
5 VDD2_OS
VDD2 Out of Specification
4 VDD2_LOW
VDD2 Low-Voltage (warning)
3 CHAN_DIAG4
Diagnostic reported on channel B4
2 CHAN_DIAG3
Diagnostic reported on channel B3
1 CHAN_DIAG2
Diagnostic reported on channel B2
0 CHAN_DIAG1
Diagnostic reported on channel B1
Diagnostic register for switch channels B2 and B1
DIAG_B21
0x1
R
8'h0
7 OC_SD2
Channel B2: Over-Current Shutdown
6 RSVD
Reserved
5 OT_CNS2
Channel B2: Over-Temperature Constraint
4 OPEN_WRN2
Channel B2: Open-Circuit Warning
3 OC_SD1
Channel B1: Over-Current Shutdown
2 RSVD
Reserved
1 OT_CNS1
Channel B1: Over-Temperature Constraint
0 OPEN_WRN1
Channel B1: Open-Circuit Warning
Diagnostic register for switch channels B3 and B4
DIAG_B43
29
0x2
R
8'h0
7 OC_SD4
Channel B4: Over-Current Shutdown
6 RSVD
Reserved
5 OT_CNS4
Channel B4: Over-Temperature Warning
4 OPEN_WRN4
Channel B4: Open-Circuit Constraint
3 OC_SD3
Channel B3: Over-Current Shutdown
2 RSVD
Reserved
1 OT_CNS3
Channel B3: Over-Temperature Constraint
0 OPEN_WRN3
Channel B3: Open-Circuit Warning
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Si834x Data Sheet • Device Operation
Register Name
SPI
Address
Read/ Reset
Write Value
Description
Switch status and switch enable for channels B4 to B1
SW_STAT
R
0x3
R/W1
SW_EN
RSVD
8'h0
0x4
N/A
N/A
7 SW_STAT4
Switch B4: Output State (1 = On, 0 = Off)
6 SW_STAT3
Switch B3: Output State (1 = On, 0 = Off)
5 SW_STAT2
Switch B2: Output State (1 = On, 0 = Off)
4 SW_STAT1
Switch B1: Output State (1 = On, 0 = Off)
3 SW_EN4
1 = Turn on switch B4 0 = Turn off switch B4
2 SW_EN3
1 = Turn on switch B3 0 = Turn off switch B3
1 SW_EN2
1 = Turn on switch B2 0 = Turn off switch B2
0 SW_EN1
1 = Turn on switch B1 0 = Turn off switch B1
Reserved
A 1'b1 in a bit field clears the corresponding diagnostic registers
CLR_DIAG
0x5
W
N/A
7 CLR_COMM_ERROR
Clear: Communication Error Shutdown
6 CLR_OT_SD
Clear: All Channels Over-Temperature Shutdown
5 CLR_VDD2_OS
Clear: VDD2 Out of Specification
4 CLR_VDD2_LOW
Clear: VDD2 Low-Voltage Warning
3 CLR_OC_SD
Clear all channels: Over-Current Shutdown
2 RSVD
Reserved
1 CLR_OT_CNS
Clear all channels: Over-Temperature Constraint
0 CLR_OPEN_WRN
Clear all channels: Open-Circuit Warning
Enable mask for diagnostic types reported on FLT\ pin
FLT_EN
30
0x6
R/W
8'hEA
7 EN_COMM_ERROR
Enable: Communication Error Shutdown
6 EN_OT_SD
Enable: All Channels Over-Temperature Shutdown
5 EN_VDD2_OS
Enable: VDD2 Out of Specification
4 EN_VDD2_LOW
Enable: VDD2 Low-Voltage Warning
3 EN_OC_SD
Enable: Any Channel: Over-Current Shutdown
2 RSVD
Reserved
1 EN_OT_CNS
Enable: Any Channel: Over-Temperature Constraint
0 EN_OPEN_WRN
Enable: Any Channel: Open-Circuit Warning
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Si834x Data Sheet • Device Operation
Register Name
SPI
Address
Read/ Reset
Write Value
Description
Enable mask for auto-clearing diagnostic reports (1 = auto-clear enabled, 0 = autoclear disabled)
7 ACLR_COMM_ERROR Auto-clear: Communication Error Shutdown
ACLR_EN
0x7
R/W
8'hFF
6 ACLR_OT_SD
Auto-clear: Over-Temperature Shutdown
5 ACLR_VDD2_OS
Auto-clear: VDD2 Undervoltage Shutdown
4 ACLR_VDD2_LOW
Auto-clear: VDD2 Low-Voltage Warning
3 ACLR_OC_SD
Auto-clear all channels: Over-Current Shutdown
2 RSVD
Reserved
1 ACLR_OT_CNS
Auto-clear all channels: Over-Temperature Constraint
0 ACLR_OPEN_WRN
Auto-clear all channels: Open-Circuit Warning
RSVD
0x8
N/A
N/A
Reserved
RSVD
0x9
N/A
N/A
Reserved
Note:
1. Register is read only for all devices with a parallel input interface.
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Si834x Data Sheet • Device Operation
3.6.2 SPI Communication Transactions
SPI communication is performed using a four wire control interface. The four Si834x device pins utilized for SPI include:
• SCLK (input) the SPI clock
• NSS (input) active low device select
• MOSI (input) master-out-slave-in
• MISO (output) master-in-slave-out
Additionally, a fifth wire MOSI_THRU (output) is provided as an Si834x device pin to facilitate daisy chaining.
An Si834x SPI communication packet is composed of three serial bytes. In this sequence, byte0 is the control byte, and specifies the
operation to be performed as well as the device to be selected in a daisy chain organization. The CID[4:0] field should be set to all
zeros by the SPI master in non-daisy-chained operation. Next, byte1 specifies the address of the internal Si834x SPI register to be
accessed. The final byte in the packet consists of either the data to be written to the addressed Si834x SPI register (using MOSI), or the
data read from the addressed Si834x SPI register (using MISO). Details of the SPI communication packet are presented in the following
figure for an Si834x SPI write transaction.
NSS
SCLK
MOSI
Control[7:0]
Address[7:0]
Control Byte
7
6
BRCT R/Wb
5
0
4
3
2
1
BRCT
1 - broadcast (write)
0 - only addressed part (write)
Ignored on reads
R/Wb
1 - read
0 - write
0
CID[0] CID[1] CID[2] CID[3] CID[4]
Address Byte
7
6
5
4
3
2
1
0
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Data Byte
7
6
5
4
3
2
1
0
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Data[7:0]
CTL[5] Reserved (set to 0)
CID[4:0] Daisy-chained part ID (0) is closest to the master
MOSI. Accomplished by decrementing the CID as
it passes through to the next Si834x device in the
daisy chain on MOSI_THRU
Figure 3.12. SPI Communication Packet Structure, Write Operation and Control Byte Structure
The SPI master will provide the timing of the signals and framing of the communication packets for all Si834x SPI inputs: NSS, SCLK,
and MOSI. Data is communicated from the SPI master to the Si834x using the MOSI signal. The NSS and SCLK signals provide the
necessary control and timing reference allowing the Si834x to discern valid data on the MOSI signal. Data is returned to the SPI master
by the Si834x utilizing the MISO signal only during the final byte of a three byte SPI read communication packet. At all other times, the
MISO signal is tri-stated by the Si834x. Each of the eight bits for these three packets is captured by the Si834x on eight adjacent rising
edges of SCLK. Each frame of eight bits is composed within bounding periods where the device select, NSS, is deasserted. Upon the
reception of the eight bits within a byte transaction, the deassertion of NSS advances the byte counter within the internal Si834x SPI
state machine. Should the transmission of an eight bit packet be corrupted, either with the deassertion of NSS before the eighth rising
edge of SCLK, or with the absence of the deassertion of NSS after the eighth rising edge of SCLK, the internal SPI state machine may
become unsynchronized with the master SPI controller.
To re-establish SPI synchronization with the Si834x, the SPI master may, at any time, deassert the SPI device select signal NSS, and
force a clock cycle on SCLK. When unsynchronized, the rising edge of SCLK when NSS is deasserted (high) re-initializes the internal
SPI state machine. The Si834x will then treat the immediately following eight bit SPI transaction after NSS is once again asserted as
the first byte in a three byte SPI communication packet.
Any preceding communication packet will be abandoned by the Si834x at the point synchronization is lost, and the NSS signal is
deasserted. This could occur at any point in the three byte sequence of a SPI communication packet. One should note that abandoning
a SPI write operation early, even during the last byte of the three byte SPI communication packet, will leave the destination register
unchanged. However, if the number of SCLK cycles exceeds eight during the last byte of the three byte SPI write packet, the
destination Si834x register may be corrupted. To remedy both of these situations, it is recommended that such a corrupted write
operation be repeated immediately following resynchronization of the SPI.
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Si834x Data Sheet • Device Operation
3.6.3 SPI Read Operation
Referring to Figure 3.12 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 32, in the SPI read
operation the control byte will only have bit 6 set to a 1 in a single Si834x device organization (no daisy chaining). Bit 7 (the broadcast
bit) is ignored during a read operation since only one device may be read at a time in either a single or daisy-chained organization.
The second byte in the three byte read packet is provided by the SPI master to designate the address of the Si834x internal register
to be queried. If the read address provided does not correspond to a physically available Si834x internal register, all zeroes will be
returned as the read value by the Si834x.
The read data is provided during the final byte of the three byte read communication packet to the querying master SPI device utilizing
the Si834x’s MISO output, which remains tristated at all other times.
The SPI read operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
Control[7:0]
Address[7:0]
MISO
ReadData[7:0]
Figure 3.13. SPI Read Operation
3.6.4 SPI Write Operation
Again referring to Figure 3.12 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 32, in the SPI
write operation the control byte may optionally have bit 7 (the broadcast bit) set to 1. During the SPI write operation, the broadcast bit
forces all daisy-chained Si834x devices to update the designated internal SPI register with the supplied write data, regardless of the
Si834x device being addressed using the CID[4:0] field of the control word.
The second byte in the three byte write packet is provided by the SPI master to designate the address of the Si834x internal register to
be updated. If the write address provided does not correspond to a physically available Si834x internal register, no internal Si834x SPI
register update will occur.
The write data is provided by the SPI master during the final byte of the three byte write communication packet. The Si834x MISO
output remains tristated during the entire SPI write operation.
The SPI write operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
Control[7:0]
Address[7:0]
MISO
WriteData[7:0]
Hi-Z
Figure 3.14. SPI Write Operation
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Si834x Data Sheet • Device Operation
3.6.5 SPI Daisy Chain Organization
The Si834x provides the capability to easily interconnect multiple Si834x devices on a common SPI administered by a single SPI master requiring no additional control signals. To accomplish this, the Si834x includes the additional SPI device output pin MOSI_THRU.
Connecting together multiple Si834x devices in this manner utilizes the MOSI_THRU pin of one Si834x device to feed the MOSI pin of
the next Si834x device in the daisy chain. All bits composing the SPI communication packet from the SPI master are passed directly
through by the Si834x from the MOSI input to the MOSI_THRU output unchanged, except for the CID[4:0] field of the control byte.
MOSI_THRU
MISO
NSS
SCLK
...
MOSI
MOSI_THRU
Si834x[31]
...
MISO
MISO
NSS
SCLK
MOSI
NSS
SCLK
Si834x[2]
MOSI
MOSI_THRU
MISO
NSS
SCLK
Si834x[1]
MOSI
MISO
NSS
SCLK
MOSI
Si834x[0]
MOSI_THRU
The least significant five bits of the control byte in the SPI communication packet, CID[4:0], are dedicated to addressing one of up
to thirty-two Si834x devices connected in a daisy chain, with 00000 indicating the device whose MOSI pin is fed directly by the SPI
master, 00001 the following Si834x device, etc. As this bit field is passed through the Si834x, it is decremented by one. This five bit
field is placed in the control word by the SPI master in reverse order, allowing the carry of the decrement to ripple into the next bit in
the CID field as the bits of the control word proceed: CID[0] is placed at bit 4 and CID[4] placed at bit 0 of the control word. When
a given Si834x device in the daisy chain is presented with the CID[4:0] code of 00000, it is activated as the one to be addressed.
All remaining operations between the SPI master and the Si834x activated in this manner proceed as previously discussed in Serial
Peripheral Interface for the case of a single Si834x slave. The organization of a system with Si834x devices daisy-chained in this
manner is depicted in the figure below.
SPI Master
Figure 3.15. SPI Daisy-Chain Organization
From the preceding figure, and referring to Figure 3.12 SPI Communication Packet Structure, Write Operation and Control Byte
Structure on page 32, in order to read from Si834x[1], the control word would be:
Control[7:0] = 0101_0000.
Similarly, in order to write to Si834x[12], the control word would be:
Control[7:0] = 0000_0110.
Finally, if it were desired to update an internal SPI register of all daisy-chained Si834x devices, the control word would be:
Control[7:0] = 1000_0000.
If the broadcast bit is zero during a write operation, only the Si834x device being addressed using the CID[4:0] field of the control word
in a daisy-chain organization will be updated. If the broadcast bit is one during a write operation, the CID[4:0] field is ignored, and
all Si834x devices connected in a daisy chain will be updated. For non-daisy-chain operations, the CID[4:0] field should always be all
zeros.
Note that there is a finite combinational delay associated with passing the MOSI input pin of a given Si834x to the MOSI_THRU output
pin. As a result, the maximum possible SCLK frequency will be reduced based on the number of Si834x devices connected in a
daisy-chain organization.
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Si834x Data Sheet • Device Operation
3.6.6 SPI Timing Behavior
The timing diagram for the Si834x SPI is presented in the figure below.
tC
SCLK
tSU1
tSU2
tH1
tH2
tNSS
NSS
Rx bit
MOSI
Rx bit
Rx bit
Rx bit
tDTHRU
MOSI_THRU
Rx bit
Rx bit
Rx bit
tDO2
tDO1
MISO
Rx bit
Tx bit
Tx bit
tDZ
Tx bit
Tx bit
Figure 3.16. SPI Timing Diagram
The timing specifications depicted in this figure apply to each byte of the three byte Si834x SPI communications packet. Refer to the
SPI timing specifications in Table 5.3 SPI Timing Characteristics on page 46.
Although this discussion of the Si834x SPI has focused on a preferred organization (separate MISO/MOSI wires), other options are
available with regard to the Si834x control interface. Possible Si834x organizations include:
• MISO/MOSI wired operation
• MISO/MOSI may be two separate wires, or may be connected together if the SPI master is capable of tristating its MOSI pin
during the data byte packet transfer of a read operation.
• Multiple Si834x devices interfaced in a non-daisy-chain format
• The SPI master provides multiple NSS signals, one for each of a multiple of Si834x slaves.
• Every Si834x shares a single trace from its MOSI input back to the SPI master (the Si834x MOSI_THRU signal is not utilized).
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Si834x Data Sheet • Application Information
4. Application Information
The Si834x is designed to be both flexible and robust to meet a wide range of application requirements, safely survive unexpected
loads, and rapidly recover normal operation. To achieve these objectives, the appropriate Si834x device must be selected and its circuit
carefully designed.
4.1 Recommended Application Circuits
The following examples illustrate typical circuit configurations using the Si834x Isolated Smart Switch.
4.1.1 Isolated Switch with Parallel Inputs and Diagnostic Indicators
VDD1
D3
D2
D1
C1
1 µF
C2
0.1 µF
R1
R2
Controller
Output
Enable
R3
R4
R5
VDD2
Si83404xAx
VDD1
VDD2
GND1
GND2
C3
0.1 µF
C4
10 µF
C5
47 µF
FLT
LEDn
VDD2_WRN
An
Bn
OE
C6
0.01 µF
L1
Figure 4.1. Recommended Si83404xAx Application Circuit
In the figure above, the Si834x is controlled via a simple set of digital outputs from the controller. An output enable signal is also
supplied from the controller for increased fault tolerance, safety, and state control. R4 and R5 are added to improve signal integrity,
especially for applications with long traces. They should be placed near the controller. Indicator LEDs D1, D2, and D3 are connected to
the Si834x through current limiting resistors R1, R2, and R3 for end-user diagnostic feedback. If indicators are not desired, the indicator
outputs can be connected directly to the controller with a pull-up resistor on the pin to send channel status information. The bypass
capacitors, C1 through C5, on the logic interface (VDD1) and switch (VDD2) power supplies should be located as close to the chip as
possible. Be sure to correctly size the decoupling capacitors based on the load and switching requirements. See Layout Considerations
for more information on sizing the decoupling capacitors. Due to the sophisticated built-in switch protection of the Si834x, connecting
and switching channels in parallel to increase the continuous current capability is not supported.
The figure above illustrates an Si83404xAx high-side sourcing device, however, the circuit is similar when using other Si834x devices,
and the guidance given around placement and sizing of components, like current limiting resistors, remains the same for all devices.
For example, VDD2_WRN is replaced with OPEN_CH when using an Si83404xBx device.
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Si834x Data Sheet • Application Information
VDD1
D3
D2
D1
C1
1 µF
C2
0.1 µF
R1
R2
Controller
Output
Enable
R3
R4
R5
VDD2
Si83414xAx
VDD1
VDD2
GND1
GND2
C3
0.1 µF
C4
10 µF
C5
47 µF
FLT
VDD2
LEDn
VDD2_WRN
An
L1
Bn
OE
C6
0.01 µF
Figure 4.2. Recommended Si83414xAx Application Circuit
In the figure above, a low-side (sinking) Si83414xAx device is illustrated. It is identical to Figure 4.1 on page 36, with the exception
of the circuit attached to the switch output Bn. Note that a high-side switch must source current into a load, such as the inductor L1
in Figure 4.1 on page 36. A low-side switch must sink current from a load, such as the inductor L1 in Figure 4.2 on page 37. The
recommended sinking output circuit is identical for all low-side (sinking) Si834x devices.
Note that, under normal conditions, the Si834x Isolated Smart Switch requires no additional components to protect the switch output
circuit such as fuses for short-circuit protection or diodes for demagnetization voltage protection (back EMF or voltage kick-back). If the
application must meet a surge specification, additional protection may be required.
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Si834x Data Sheet • Application Information
4.1.2 Isolated High-Side Switch with Parallel Inputs and Fault Control
VDD1
D2
D1
C1
1 µF
C2
0.1 µF
R1
Controller
Enable
Output
Clear
R2
R3
R4
R5
VDD2
Si83404xCx
VDD1
VDD2
GND1
GND2
C3
0.1 µF
C4
10 µF
C5
47 µF
FLT
LEDn
OE
An
Bn
FLT_CLR
C6
0.01 µF
L1
Figure 4.3. Recommended Si83404xCx Application Circuit
In the figure above, the Si834x has an additional input signal from the controller used to clear any faults reported by the device. Once a
fault is reported, the FLT\ output will turn ON until both the fault condition is removed and the FLT_CLR pin is given a logic high value,
manually clearing the fault report from the device. Controlled restart of the outputs after a fault can be achieved by connecting the FLT\
output to the OE input with a pull-up resistor. In this configuration, when a fault is reported, all outputs will be disabled until the fault is
cleared.
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Si834x Data Sheet • Application Information
4.1.3 Isolated High-Side Switch with SPI
VDD1
D2
D1
C1
1 µF
C2
0.1 µF
R1
Controller
Enable
SCLK
NSS
MOSI
MISO
R2
R3
R4
R5
R6
R7
VDD2
Si83408xDx
VDD1
VDD2
GND1
GND2
C3
0.1 µF
C4
10 µF
C5
47 µF
FLT
LEDn
Bn
OE
C6
0.01 µF
L1
SCLK
NSS
MOSI
MISO
Figure 4.4. Recommended Si83408xDx Application Circuit
In the figure above, the Si834x is monitored and controlled through the SPI from the controller. Control signals to turn ON or OFF a
switch, as well as device configuration signals, are communicated via the SPI only, reducing required controller pins.
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Si834x Data Sheet • Application Information
VDD1
D1
Controller
Output
Enable
SCLK
NSS
MOSI
MISO
C1
1 µF
C2
0.1 µF
R1
R2
R3
R4
R5
R6
R7
VDD2
Si83408xFx
VDD1
VDD2
GND1
GND2
C3
0.1 µF
C4
10 µF
C5
47 µF
FLT
An
Bn
OE
C6
0.01 µF
L1
SCLK
NSS
MOSI
MISO
Figure 4.5. Recommended Si83408xFx Application Circuit
The Si83408xFx retains the efficient parallel input interface, while adding the SPI for configuration and diagnostics, by eliminating
channel status indicator pins. This device is illustrated above. When using this device, it is recommended that channel status indicators
be implemented using additional controller output pins, or by adding them to the switch output circuit.
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Si834x Data Sheet • Application Information
4.2 Layout Considerations
High voltage circuits (i.e., circuits with > 30 VAC or > 60 VDC) must be physically separated from the safety extra-low voltage circuits
(SELV is a circuit with < 30 VAC or < 60 VDC) by a certain distance (creepage/clearance) to ensure safety in the end-user application. If
a component, such as the Si834x, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide
a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5.7 Insulation
and Safety-Related Specifications on page 50 and Table 5.9 VDE 0884-10 Insulation Characteristics on page 51 provide details
about the creepage/clearance and working voltage capabilities of the Si834x. These tables also detail the component standards
(UL1577, VDE 0884, CSA and CQC), which are readily accepted by certification bodies to provide proof for end-system specification
requirements. Refer to the end-system specification requirements before starting any design that uses the Si834x.
Several additional layout recommendations should be taken into consideration when designing for the Si834x Isolated Smart Switch
device. These recommendations improve signal integrity, mitigate inrush current concerns, optimize heat dissipation, and improve the
manufacturability of the end-system.
1. Place a pair of bypass capacitors as close as possible to the VDD1 power supply pin. A 0.1 µF capacitor, and a 1 µF or larger
capacitor are recommended. It is important that the decoupling capacitors are selected such that the maximum VDD1 Slew Rate
specification found in Table 5.12 Absolute Maximum Ratings on page 53 is not exceeded. Add a 10 Ω resistor in series with the
bypass capacitor pair to form a low-pass filter for applications where VDD1 may experience a high slew rate, such as a hot-pluging
event.
2. An entire PCB plane should be dedicated to the GND1 reference to improve signal integrity. If an entire PCB plane is not dedicated
to the GND1 reference, be cautious of a signal's ground path when connected to the Si834x logic interface.
3. It is recommended to use a resistor on to each logic interface pin to improve signal integrity and reduce EMI concerns, especially
for long traces. They should be placed as close to the controller as possible. See the Recommended Application Circuits for
details.
4. To improve heat dissipation, add multiple thermal relief vias extending from the PCB pads connected to ePAD1 and ePAD2 and
their appropriate ground planes, through the PCB, and exposed on the opposite side of the board. Use small-diameter vias, as
large-diameter vias may reduce manufacturability.
5. Open board space surrounding the Si834x device, on the opposite side of the PCB from the Si834x device and around the thermal
relief vias, further improves heat dissipation.
6. Place a pair of bypass capacitors as close as possible to the VDD2 switch power supply pin. A 0.1 µF capacitor, and a 10 µF
or larger capacitor are recommended. An additional 47 µF capacitor is recommended if Inrush Current Mode will be used. It
is important that the decoupling capacitors are selected such that the maximum VDD2 Slew Rate specification found in Table
5.12 Absolute Maximum Ratings on page 53 is not exceeded.
7. Bulk bypass capacitance can be added to the existing bypass capacitors on the VDD2 switch power supply. Size the bulk capacitor
based upon end-system load requirements and the specified maximum VDD2 slew rate.
8. Use the widest traces possible for the switch output pins in order to handle large inrush currents.
9. To reduce EMI concerns and channel crosstalk, minimize the current return path for switch outputs. Be sure to consider the
additional current return path through the bulk capacitor, especially when using a low-side (sinking) device.
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Si834x Data Sheet • Application Information
4.3 Power Dissipation Considerations
When the Si834x device is operating within the rated ambient temperature range, the only significant source of temperature rise is the
demagnetization of inductive loads. The Si834x was designed to drive and demagnetize 1.15 H loads on all channels simultaneously
without exceeding the thermal limitations of the device. If the user exceeds the temperature limitations of the device, it will reduce the
demagnetization clamp voltage to VCLMPL for all channels, which will extend the turn-OFF time of all inductive loads, and all channels
will be prevented from turning on again. This reduces power dissipation until the device temperature is reduced to acceptable levels.
See Over-Temperature Protection for details on this process.
Due to the innovative Over-Temperature Protection feature, the designer should only be concerned about the switch temperature at the
beginning of the load switching cycle. The switch temperature must be maintained below the Over-Temperature Threshold. Therefore,
the Derated Ambient temperature (T AD) is dependent on device power dissipation and thermal impedance. The estimated device power
dissipation is composed of quiescent power dissipation (PQ) and power dissipation for each channel (PCH) as shown in Equation 4.3.1
and supported by Equations 4.3.2 and 4.3.3.
T AD < TOT − THY S − θJ A PQ + nCH ∙ PCH
Equation 4.3.1
Where:
TOT is the Over-Temperature Threshold (˚C).
THYS is the Over-Temperature Hysteresis (˚C).
øJA is the Junction-to-Ambient thermal resistance (˚C/W).
nCH is the number of channels actively driving a load.
The logic interface contributes a negligible amount of power to the total device power dissipation. To simplify the estimate, it has been
removed from both PQ and PCH in the equations below.
PQ = IDD2Q ∙ V DD2
Equation 4.3.2
Where:
IDD2Q is the VDD2 Supply Quiescent Current (A).
VDD2 is the VDD2 Supply Voltage (V).
For a conservative power dissipation estimate, the maximum quiescent current specification IDD2Q(MAX) should be used in Equation
4.3.2.
The power dissipated by a single channel is estimated by Equation 4.3.3 and supported by Equations 4.3.4 through 4.3.7. It is
comprised of the power dissipation when the channel is ON (PON), the power dissipated when the channel is turning on (PSW), and the
power dissipated when the channel is turning off and demagnetizing an inductor (PCLMP).
PCH = PON + PSW + PCLMP
Equation 4.3.3
The estimated power dissipation when the channel is ON, given by Equation 4.3.4, is dependent on the current through the load, the
switch's ON-State Resistance, and how long the load is driven.
PON = IL2 ∙ RON ∙
tON
tSW
Equation 4.3.4
Where:
IL is the current through the load (A).
RON is the ON-State Output Resistance (Ω).
tON is the time during a single switching period that the channel is ON (s).
tSW is the switching period of the channel (s).
For a conservative power dissipation estimate, the maximum current through the load and the maximum ON-State Output Resistance
should be used in Equation 4.3.4.
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Si834x Data Sheet • Application Information
The estimated power dissipation when the channel is turning on, given by Equation 4.3.5, is dependent on the switch supply voltage,
the load capacitance, and the switching period.
PSW = V DD22 ∙
CL
2 ∙ tSW
Equation 4.3.5
Where:
VDD2 is the VDD2 Supply Voltage (V).
CL is the load capacitance (C).
tSW is the switching period of the channel (s).
Note that the load capacitance (CL) should include any capacitance built into the circuit, such as the 10 nF capacitor recommended in
Layout Considerations.
The estimated power dissipation when the channel is turning off and demagnetizing an inductor is dependent on the current through
the load, the smart output clamp voltage, and the switching period. If the current through the load is greater than the Demagnetization
Clamp Current Threshold (IL > ICLMPT), then use Equation 4.3.6 for the power dissipated by a single channel (PCH).
V CLMPL ∙
IL + ICLMPT
∙
2
PCLMP =
+V CLMPH ∙
L IL − ICLMPT )
IL + ICLMPT
RL
+ V CLMPL Tsw
2
ICLMPT
ICLMPT ∙ L
∙ I
2
CLMPT ∙ RL
+ V CLMPH TSW
2
Equation 4.3.6
Where:
VCLMPL is the Demagnetization Clamp Low Voltage (V).
VCLMPH is the Demagnetization Clamp High Voltage (V).
IL is the current through the load (A).
ICLMPT is the Demagnetization Clamp Current Threshold (A).
L is the inductance of the load (H).
RL is the resistance of the load(Ω).
TSW is the switching period of the channel (s).
For a conservative power dissipation estimate, the maximum current through the load should be used in Equation 4.3.6 and Equation
4.3.7. The time during a single switching period (TSW) that the channel is OFF must be large enough to completely discharge the load
inductance.
If the current through the load is less then the Demagnetization Clamp Current Threshold (IL < ICLMPT), then use Equation 4.3.7 for the
power dissipated by a single channel (PCH).
PCLMP = V CLMPH ∙
IL
IL ∙ L
∙
2
IL ∙ RL
+ V CLMPH TSW
2
Equation 4.3.7
Where:
VCLMPH is the Demagnetization Clamp High Voltage (V).
IL is the current through the load (A).
L is the inductance of the load (H).
RL is the resistance of the load (Ω).
TSW is the switching period of the channel (s).
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Si834x Data Sheet • Electrical Specifications
5. Electrical Specifications
Table 5.1. Power Supply Characteristics
Operating range for the following specifications: VDD1 = 2.25 - 5.5 V; VDD2 = 9 - 32 V; TA = –40 to +125 °C; Typical specs: VDD1 = 5
V; VDD2 = 24 V; TA = 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD1 Supply Voltage
VDD1
2.25
—
5.5
V
VDD2 Supply Voltage
VDD2
9
24
32
V
VDD1 Undervoltage Threshold
VDD1 Undervoltage Hysteresis
VDD2 Undervoltage Threshold
VDD2 Undervoltage Hysteresis
VDD1UV+
VDD1 rising
1.90
2.03
2.16
V
VDD1UV-
VDD1 falling
1.85
1.99
2.1
V
—
50
—
mV
VDD1HYS
VDD2UV9+
VDD2 rising
8.2
8.6
9.0
VDD2UV9-
VDD2 falling
8
8.35
8.7
—
200
—
mV
VDD2UV9HYS
V
VDD2CLMP
ICLMP = 1 mA
—
48
—
V
VDD1 Supply Quiescent Current
IDD1Q
All An = LOW
3.3
3.6
4.3
mA
VDD2 Supply Quiescent Current
IDD2Q
All An = LOW
8
9.8
12
mA
—
4.1
—
3.5
4.2
5
—
10.2
—
8
10
12
VDD2 ESD Clamp Threshold
VDD1 Supply Active Current
1 Channel Active
IDD11CH
All Channels Active
IDD1ALL
Active An inputs toggling at
1 kHz (50% duty cycle)
mA
VDD2 Supply Active Current
1 Channel Active
IDD11CH
All Channels Active
IDD1ALL
Active Bn outputs toggling
at 1 kHz (50% duty cycle),
no load
mA
Device Startup Time1
tST
—
2.0
—
ms
VDD1 Logic Interface Power Cycle Time1
tPC1
—
80
—
µs
VDD2 Switch Power Cycle Time1
tPC2
—
2.4
—
ms
VDD1 Logic Interface Shutdown Time1
tSD1
—
2.9
—
µs
Note:
1. Startup, power cycle, and shutdown timing are detailed in Switch Timing Behavior.
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Si834x Data Sheet • Electrical Specifications
Table 5.2. Logic Interface Characteristics
Operating range for the following specifications: VDD1 = 2.25 - 5.5 V; VDD2 = 9 - 32 V; TA = –40 to +125 °C; Typical specs: VDD1 = 5
V; VDD2 = 24 V; TA = 25 °C
Parameter
Low Level Input Voltage
High Level Input Voltage
Input Hysteresis
Input Capacitance
Input Leakage Current
Symbol
Test Condition
Min
Typ
Max
VDD1 = 2.5 V ± 10%
—
—
VDD1 x 0.2
VDD1 = 3.3 V ± 10%
—
—
0.8
VDD1 = 5.0 V ± 10%
—
—
1
VDD1 = 2.5 V ± 10%
VDD1 x 0.5
—
—
VDD1 = 3.3 V ± 10%
2.0
—
—
VDD1 = 5.0 V ± 10%
2.3
—
—
VHYS
—
0.25
—
V
CI
—
2
—
pF
| ILKG |
—
—
1
µA
VIL
VIH
Unit
V
V
Low Level Output Voltage1
VOL
IOH = 4 mA
—
—
0.4
V
High Level Output Voltage1
VOH
IOH = -4 mA
VDD1 - 0.4
—
—
V
ZOH
—
50
—
ZOL
—
65
—
ZOLED
—
30
—
8
—
—
Output Impedance
Logic Output1
Indicator Output2
Indicator Output Current2
IOLED
VOLED = 0.5 V
Ω
mA
Note:
1. Parameter applies to MOSI_THRU, and MISO logic output pins.
2. Parameter applies to FLT\, VDD2_WRN\, OPEN_CH\, LEDn\ indicator output pins. Indicator outputs use an active-low, opendrain configuration where current is sinked into the pin. See Recommended Application Circuits for more information.
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Si834x Data Sheet • Electrical Specifications
Table 5.3. SPI Timing Characteristics
Operating range for the following specifications: VDD1 = 2.25 - 5.5 V; VDD2 = 9 - 32 V; TA = –40 to +125 °C; Typical specs: VDD1 = 5
V; VDD2 = 24 V; TA = 25 °C
Parameter
Symbol
Min
Typ
Max
Unit
tC
100
—
—
ns
SCLK High or Low Time
tPW
30
—
—
ns
Delay time, SCLK fall to MISO active
tDO1
—
—
20
ns
Delay time, SCLK fall to MISO transition
tDO2
—
—
20
ns
Delay time, NSS rise to MISO hi-Z
tDZ
—
—
20
ns
Setup time, NSS fall to SCLK fall
tSU1
25
—
—
ns
Hold time, SCLK rise to NSS rise
tH1
20
—
—
ns
Setup time, MOSI to SCLK rise
tSU2
25
—
—
ns
Hold time, SCLK rise to MOSI transition
tH2
20
—
—
ns
tNSS
200
—
—
ns
tDTHRU
—
—
15
ns
Cycle time (SCLK)2
Delay time between NSS active
Propagation delay, MOSI to MOSI_THRU2
Note:
1. See Figure 3.16 SPI Timing Diagram on page 35 for SPI timing characteristics test conditions.
2. When implementing a daisy chain, see SPI Daisy Chain Organization for cycle time considerations. Cycle time will increase
according to tC N = tC MIN + tDTHRU N − 1 where N is the number of Si834x devices present in the daisy chain.
Table 5.4. Load Driving Characteristics
Operating range for the following specifications: VDD1 = 2.25 - 5.5 V; VDD2 = 9 - 32 V; TA = –40 to +125 °C; Typical specs: VDD1 = 5
V; VDD2 = 24 V; TA = 25 °C; CL=10 nF; RLOAD = 47 Ω
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
MPW
An or OE pins
10
—
—
µs
—
2.3
—
—
2.1
—
—
2.9
—
—
2.2
—
tPSK
—
—
250
ns
Si8340x Sourcing Output Rise Time4
tR
—
3.0
—
µs
Si8341x Sinking Output Fall Time5
tF
—
3.0
—
µs
—
8.3
—
—
8.3
—
Recommended High or Low Pulse Width
Turn ON Propagation Delay1
Si8340x Sourcing Devices
Si8341x Sinking Devices
tPLH
µs
Turn OFF Propagation Delay2
Si8340x Sourcing Devices
Si8341x Sinking Devices
Channel-Channel Skew3
tPHL
µs
Turn ON Voltage Slope
Si8340x Sourcing Devices
Si8341x Sinking Devices
46
dV/dtON
V/µs
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Si834x Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
—
7.6
—
—
10.2
—
Unit
Turn OFF Voltage Slope
Si8340x Sourcing Devices
dV/dtOFF
Si8341x Sinking Devices
V/µs
OFF State Output Current
| IO(OFF) |
VO(OFF) = 0 V to VDD2
—
—
100
µA
ON State Load Current
| IO(ON) |
Continuous operation
—
0.5
0.7
A
RON
IOL = 0.5 A, VDD2 = 24 V
—
145
280
mΩ
CL
10
—
1000
nF
ICLMP(MIN)
1
—
—
mA
ON-State Output Resistance
Load Capacitance
Demagnetization Current to Engage Clamp
Note:
1. Turn ON propagation delay is measured from the time the input (An or OE) is 50% ON to the time the output (Bn) is 10% ON and
rising. See Figure 5.1 Turn ON and Turn OFF Timing on page 47 for measurement details.
2. Turn OFF propagation delay is measured from the time the input (An or OE) is 50% ON to the time the output (Bn) is 90% ON
and falling. See Figure 5.1 Turn ON and Turn OFF Timing on page 47 for measurement details.
3. Channel-channel skew is the magnitude of the difference in turn ON or turn OFF propagation delay times measured between
different channels operating at the same supply voltages, load, and ambient temperature.
4. Output rise time is measured from the time the output is 10% ON to the time the output is 90% ON. For sinking output
devices (Si8341x), rise time is determined by load conditions. See Figure 5.1 Turn ON and Turn OFF Timing on page 47 for
measurement details.
5. Output fall time is measured from the time the output is 90% ON to the time the output is 10% ON. For sourcing output
devices (Si8340x), fall time is determined by load conditions. See Figure 5.1 Turn ON and Turn OFF Timing on page 47 for
measurement details.
50%
VAn
tPLH
tR
tPHL
tF
90%
10%
VBn
Figure 5.1. Turn ON and Turn OFF Timing
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Si834x Data Sheet • Electrical Specifications
Table 5.5. Protection and Diagnostics
Operating range for the following specifications: VDD1 = 2.25 - 5.5 V; VDD2 = 9 - 32 V; TA = –40 to +125 °C; Typical specs: VDD1 = 5
V; VDD2 = 24 V; TA = 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Common Mode Transient Immunity
CMTI
100
—
—
kV/µs
Output Current Limit1
IOCL
0.7
0.88
1.1
A
Output Current Limit Threshold2
IOCLT
—
1.15
—
A
Output Current Limit Pulse3
tOCL
—
155
—
µs
Output Current Limit Period3
tOCLP
—
1
—
ms
Over-Current Protection Duration3
tOCPD
—
6
—
ms
Output Peak Current Limit4
IOPCL
—
8
—
A
Output Peak Current Test Pulse4
tOPCT
—
11.5
—
µs
Output Peak Current Limit Pulse4
tOPCL
—
20
—
ms
Over-Current Protection Retry Delay
tOPRD
—
500
—
ms
—
-17.5
—
—
VDD2+17.5
—
—
-2.1
—
—
VDD2+2.1
—
—
0.4
—
Demagnetization Clamp High Voltage5
Si8340x Sourcing Devices
Si8341x Sinking Devices
VCLMPH
IO = 1 mA
VCLMPL
IO ≥ ICLMPT
V
Demagnetization Clamp Low Voltage5
Si8340x Sourcing Devices
Si8341x Sinking Devices
Demagnetization Clamp Current Threshold5
48
ICLMPT
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A
48
Si834x Data Sheet • Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
9 V ≤ VDD2 < 16 V
40
—
—
kΩ
VDD2 ≥ 16V
100
—
—
kΩ
VDD2UV18+
VDD2 rising
—
18.5
—
VDD2UV18-
VDD2 falling
—
18.0
—
VDD2OV32+
VDD2 rising
—
33.5
—
VDD2OV32-
VDD2 falling
—
33
—
Load Resistance Threshold for Open-Circuit
Diagnostic
RLMAX
VDD2 Low-Voltage Threshold
VDD2 Overvoltage Threshold6
V
V
Over-Temperature Threshold7
TOT
159
167
175
°C
Over-Temperature Hysteresis
THYS
—
33
—
°C
Note:
1. The current limit is applied when an output is first turned ON, and when over-current conditions are present on the output. It is
applied in a pulsed fashion for tOCL and repeats for tOCPD. See Switch Protection for details.
2. The current measured through the output must exceed this threshold in order to be detected as an over-current condition and for
the Output Current Limit (IOCL) to be enforced. See Switch Protection for details.
3. Period may be reduced during operation if over-current conditions are removed. See Switch Protection for details.
4. Peak output current is only available for a short time period tOPCL, and only during a perceived over-current condition detected
when the output is first turned ON or after the Over-Current Protection Retry Delay. See Switch Protection for details.
5. The demagnetization clamp voltage is VCLMPL while the current through the output is equal to or above ICLMPT. When current
through the output is below ICLMPT, the demagnetization clamp voltage is VCLMPH. Under certain fault conditions, this behavior is
modified and performance is constrained. See Switch Protection for details.
6. Inductive load demagnetization performance is constrained above this threshold. See Switch Protection for details.
7. Any channel that exceeds the Over-Temperature Threshold will have its demagnetization performance constrained. If all channels
exceed the Over-Temperature Threshold, all channels will be unconditionally shutdown. By default, this behavior will persist until
the Over-Temperature condition(s) are removed. See Switch Protection for details.
Si834x
VDD2
VDD1
9 to 32 V
Supply
OE
3 to 5 V
Isolated
Supply
Bn
An
Oscilloscope
1k
GND1
GND2
Isolated
Ground
Input
Vcm Surge
Output
+
High Voltage
Surge Generator
High Voltage
Differential
Probe
Output
-
Figure 5.2. Common Mode Transient Immunity (CMTI) Test Circuit for Sourcing Device
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Si834x Data Sheet • Electrical Specifications
Table 5.6. Regulatory Information (Pending)
CSA
Certified under IEC 60950-1, 62368-1. For more details, see Master Contract Number 232873.
VDE
Certified according to VDE-0884. For more details, see File 5006301-4880-0001.
Up to 560 Vpeak for basic insulation working voltage.
UL
Certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to1500 VRMS isolation voltage for basic insulation.
CQC
Certified under GB4943.1-2011.
Note: Regulatory Certifications apply to 1.5 kVRMS rated devices which are production tested to 1.8 kVRMS for 1 second. For more
information, see Ordering Guide.
Table 5.7. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
9x9 DFN-32
Unit
Nominal External Air Gap (Clearance)
CLR
3.5 min
mm
Nominal External Tracking (Creepage)
CPG
3.5 min
mm
Minimum Internal Gap (Internal Clearance)
DTI
0.008
mm
Tracking Resistance
CTI
600
V
Erosion Depth
ED
0.040
mm
Resistance (Input-Output)1
RIO
1012
Ω
Capacitance (Input-Output)
CIO
1
pF
IEC60112
f = 1 MHz
Note:
1. To determine resistance and capacitance, the Si834x is converted into a 2-terminal device. Pins 1–16 are shorted together to
form the first terminal, and pins 17 – 32 are shorted together to form the second terminal. The parameters are then measured
between these two terminals.
Table 5.8. IEC 60664-1 Ratings
Parameter
Basic Isolation Group
Installation Classification
50
Test Condition
9x9 DFN-32
Material Group
I
Rated Mains Voltages < 50 VRMS
I-IV
Rated Mains Voltages < 100 VRMS
I-III
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Si834x Data Sheet • Electrical Specifications
Table 5.9. VDE 0884-10 Insulation Characteristics
Parameter
Symbol
Test Condition
9x9 DFN-32
Unit
560
VPEAK
VPR
Method b1 (VIORM x1.875 = VPR,
100%
Production Test, tm=1 sec, Partial
Discharge < 5 pC)
1050
VPEAK
Transient Overvoltage
VIOTM
t = 60 sec
2000
VPEAK
Surge Voltage
VIOSM
Tested with 2000 V
1538
VPEAK
VIORM
Maximum Working Insulation Voltage
Input to Output Test Voltage
Pollution Degree (DINVDE 0110, Table 1)
2
>109
RS
Insulation Resistance at TS,VIO = 500 V
Ω
Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured
by protective circuits. The Si834x provides a climate classification of 40/125/21.
Table 5.10. IEC Safety Limiting Values
Parameter
Symbol
Safety Temperature
TS
Safety Current
IS
Output Power
PS
Max
Test Condition
9x9 DFN-32
Unit
150
°C
θJA = 30 °C/W, TJ = 150 ˚C, TA = 25 ˚C, VDD2 = 32 V
130
mA
θJA = 30 °C/W, TJ=150 °C, TA = 25 °C
4
W
Note: Maximum value allowed in the event of a failure; for more information, see Thermal Derating Curve Figure 5.3 on page 52.
Table 5.11. Thermal Characteristics
Parameter
Ambient Temperature1
Symbol
Test Condition
Min
Max
Unit
-40
125
°C
4-layer, 2s2p JEDEC test board
—
30
ºC/W
2-layer, Si834x-KIT evaluation board
—
25
ºC/W
4-layer, 2s2p JEDEC test board
—
1.5
ºC/W
TA
9x9 DFN-32 Package Thermal Resistance
Junction-to-Ambient
θJA
Junction-to-Case (Exposed Pad)
θJC
Note:
1. The maximum ambient temperature is dependent on data frequency, output load conditions, fault conditions, number of operating
channels, and supply voltages. See Power Dissipation Considerations for more details.
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Si834x Data Sheet • Electrical Specifications
600
480
VDD = 9 V
360
IS (mA)
VDD = 12 V
240
VDD = 24 V
120
VDD = 32 V
0
0
40
80
TA (°C)
120
160
Figure 5.3. Safety Current (IS) vs. Ambient Temperature (TA) Derating Curve
52
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Si834x Data Sheet • Electrical Specifications
Table 5.12. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
VDD1 Supply Voltage
VDD1
-0.3
7
V
VDD2 Supply Voltage
VDD2
-0.3
40
V
VDD1 Slew Rate
VDD1∆
—
1
V/µs
VDD2 Slew Rate2
VDD2∆
—
1
V/µs
Storage Temperature3
TSTG
-65
+150
°C
Junction Temperature
TJ
—
+175
°C
VIO-G
-0.3
VDD1+0.3
V
EAS(1CH)
—
Unlimited
J
—
8
J
—
2.5
J
—
260
°C
Voltage on Any Logic Pin with Respect to Ground
One Channel Single Pulse Turn OFF Energy Dissipation4
All Channels Simultaneously Driven Single Pulse Turn OFF Energy Dissipation4
Si8340x Sourcing Devices
Si8341x Sinking Devices
EAS(ALL)
Lead Solder Temperature (10 s)
Human Body Model (JEDEC JS-001) ESD Rating
ESDHBM
5
—
kV
Charged Device Model (JEDEC JS-002) ESD Rating
ESDCDM
1
—
kV
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality
and Reliability Monitor Report at https://www.skyworksinc.com/Product_Certificate.aspx.
2. Absolute maximum slew rate only applies to supply voltage changes larger than 3 V.
3. VDE certifies storage temperature from –40 to 150 °C.
4. Tested at TA = 125 ˚C and maximum Load Current IO(ON) for the channel. See Table 5.4 Load Driving Characteristics on page 46
for details.
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Si834x Data Sheet • Electrical Specifications
5.1 Typical Operating Characteristics
The typical performance characteristics depicted in the figures below are for information purposes only. Refer to the data tables in the
Electrical Specifications for actual specification limits.
250
TA = 125˚C
RON (mΩ)
1
200
TA = 25˚C
150
TA = -40˚C
100
50
1
IL = 500 mA
2
0
9
14
19
VDD2 (V)
24
29
Figure 5.4. On Resistance (RON) vs. Switch Supply Voltage (VDD2)
Note:
1. IL is the current sinking or sourcing through the output channel depending on the output channel configuration. See Switch Types
for details.
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Si834x Data Sheet • Electrical Specifications
250
RON (mΩ)
1
210
170
130
90
VDD2 = 24 V
1
IL = 500mA 2
50
-40
0
40
TA (˚C)
80
120
Figure 5.5. On Resistance (RON) vs. Ambient Temperature (TA)
Note:
1. IL is the current sinking or sourcing through the output channel depending on the output channel configuration. See Switch Types
for details.
3.6
3.5
IDD1 (mA)
TA = 125˚C
3.4
TA = 25˚C
TA = -40˚C
3.3
All An = LOW
3.2
2.25
3.00
3.75
VDD1 (V)
4.50
5.25
Figure 5.6. Logic Interface Supply Quiescent Current (IDD1Q) vs. Logic Interface Supply Voltage (VDD1)
55
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Si834x Data Sheet • Electrical Specifications
3.6
IDD1 (mA)
3.5
3.4
3.3
VDD1 = 3.3 V
All An = LOW
3.2
-40
0
40
TA (˚C)
80
120
Figure 5.7. Logic Interface Supply Current Quiescent (IDD1Q) vs. Ambient Temperature (TA)
11
TA = 125˚C
IDD2 (mA)
10
TA = 25˚C
9
TA = -40˚C
8
All An = LOW
7
9
14
19
VDD2 (V)
24
29
Figure 5.8. Switch Supply Quiescent Current (IDD2Q) vs. Switch Supply Voltage (VDD2)
56
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Si834x Data Sheet • Electrical Specifications
11
IDD2 (mA)
10
9
8
VDD2 = 24 V
All An = LOW
7
-40
0
40
TA (˚C)
80
120
Figure 5.9. Switch Supply Quiescent Current (IDD2Q) vs. Ambient Temperature (TA)
VO(OFF) = VDD2 + VF 2
10
VDD2 = 24 V
C
TA = 25 °C
0
VO(OFF) = VCLMPH
IO(OFF) (mA)
1
5
-5
-10
-35
-18
0
VO(OFF) (V)
18
35
Figure 5.10. OFF State Output Current (IO(OFF)) vs. Output Voltage (VO(OFF)) for Sourcing Devices
Note:
1. IO(OFF) is considered positive when current is flowing into the output pin.
2. VF denotes the voltage of a forward biased diode.
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Si834x Data Sheet • Electrical Specifications
VO(OFF) = VDD2 + VCLMPH
10
VDD2 = 24 V
TA = 25 °C
0
-5
-10
-18
VO(OFF) = -VF2
IO(OFF) (mA)1
5
0
18
VO(OFF) (V)
35
53
Figure 5.11. OFF State Output Current (IO(OFF)) vs. Output Voltage (VO(OFF)) for Sinking Devices
Note:
1. IO(OFF) is considered positive when current is flowing into the output pin.
2. VF denotes the voltage of a forward biased diode.
58
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Si834x Data Sheet • Pin and Package Descriptions
6. Pin and Package Descriptions
6.1 Pin Descriptions
The Si834x consists of multiple die in a package with different bond-outs for different customer needs. Each bond-out is represented by
a pin-out below. The Ordering Guide describes the part number and features for these products.
32
GND2
NC
1
32
GND2
2
31
DNC
A1
2
31
DNC
A2
3
30
GND2
A2
3
30
VDD2
A3
4
29
VDD2
A3
4
29
GND2
A4
5
28
B1
A4
5
28
B1
OE
6
27
VDD2
OE
6
27
GND2
GND1
7
GND1
7
26
B2
FLT
8
FLT
8
25
GND2
24
B3
23
GND2
VDD1
9
GND1
10
ePAD1
ePAD2
26
B2
25
VDD2
24
B3
VDD1
9
23
VDD2
GND1
10
ePAD2
VDD2_WRN
11
22
B4
VDD2_WRN
11
22
B4
LED1
12
21
VDD2
LED1
12
21
GND2
LED2
13
20
GND2
LED2
13
20
VDD2
LED3
14
19
VDD2
LED3
14
19
VDD2
LED4
15
18
DNC
LED4
15
18
DNC
NC
16
17
GND2
NC
16
17
GND2
Si83404xAA-IF
Si83414xAA-IF
NC
1
32
GND2
NC
1
32
GND2
A1
2
31
DNC
A1
2
31
DNC
30
GND2
A2
3
30
VDD2
4
29
VDD2
A3
4
29
GND2
A4
5
28
B1
A4
5
28
B1
OE
6
27
VDD2
OE
6
27
GND2
GND1
7
GND1
7
26
B2
FLT
8
FLT
8
25
GND2
24
B3
23
GND2
VDD1
9
GND1
10
ePAD1
ePAD2
26
B2
25
VDD2
ePAD1
Isolation Barrier
3
Isolation Barrier
A2
A3
ePAD2
24
B3
VDD1
9
23
VDD2
GND1
10
OPEN_CH
11
22
B4
OPEN_CH
11
22
B4
LED1
12
21
VDD2
LED1
12
21
GND2
LED2
13
20
GND2
LED2
13
20
VDD2
LED3
14
19
VDD2
LED3
14
19
VDD2
LED4
15
18
DNC
LED4
15
18
DNC
NC
16
17
GND2
NC
16
17
GND2
Si83404xBA-IF
59
ePAD1
Isolation Barrier
1
A1
Isolation Barrier
NC
Si83414xBA-IF
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Si834x Data Sheet • Pin and Package Descriptions
NC
1
32
GND2
NC
1
32
GND2
A1
2
31
DNC
A1
2
31
DNC
30
GND2
A2
3
30
VDD2
4
29
VDD2
A3
4
29
GND2
A4
5
28
B1
A4
5
28
B1
OE
6
27
VDD2
OE
6
27
GND2
GND1
7
GND1
7
26
B2
FLT
8
FLT
8
25
GND2
24
B3
23
GND2
VDD1
9
GND1
10
ePAD1
ePAD2
26
B2
25
VDD2
24
B3
VDD1
9
23
VDD2
GND1
10
ePAD1
Isolation Barrier
3
Isolation Barrier
A2
A3
ePAD2
FLT_CLR
11
22
B4
FLT_CLR
11
22
B4
LED1
12
21
VDD2
LED1
12
21
GND2
LED2
13
20
GND2
LED2
13
20
VDD2
LED3
14
19
VDD2
LED3
14
19
VDD2
LED4
15
18
DNC
LED4
15
18
DNC
NC
16
17
GND2
NC
16
17
GND2
Si83404xCA-IF
Si83414xCA-IF
Figure 6.1. 4-Channel Parallel Interface Devices
1
32
GND2
DNC
LED1
2
31
DNC
30
GND2
LED2
3
30
VDD2
29
VDD2
LED3
4
29
GND2
5
28
B1
LED4
5
28
B1
OE
6
27
VDD2
OE
6
27
GND2
GND1
7
GND1
7
26
B2
FLT
8
FLT
8
25
GND2
24
B3
23
GND2
32
GND2
LED1
2
31
LED2
3
LED3
4
LED4
VDD1
9
GND1
10
ePAD1
Isolation Barrier
1
ePAD2
26
B2
25
VDD2
24
B3
VDD1
9
23
VDD2
GND1
10
MOSI_THRU
11
22
B4
NSS
12
21
VDD2
ePAD1
Isolation Barrier
NC
NC
ePAD2
MOSI_THRU
11
22
B4
NSS
12
21
GND2
SCLK
13
20
GND2
SCLK
13
20
VDD2
MOSI
14
19
VDD2
MOSI
14
19
VDD2
MISO
15
18
DNC
MISO
15
18
DNC
NC
16
17
GND2
NC
16
17
GND2
Si83408xDA-IF
Si83418xDA-IF
Figure 6.2. 4-Channel SPI Devices
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Si834x Data Sheet • Pin and Package Descriptions
NC
1
32
GND2
NC
1
32
GND2
A1
2
31
DNC
A1
2
31
DNC
30
GND2
A2
3
30
VDD2
4
29
VDD2
A3
4
29
GND2
A4
5
28
B1
A4
5
28
B1
OE
6
27
VDD2
OE
6
27
GND2
GND1
7
GND1
7
26
B2
FLT
8
FLT
8
25
GND2
24
B3
23
GND2
VDD1
9
GND1
10
ePAD1
ePAD2
26
B2
25
VDD2
24
B3
VDD1
9
23
VDD2
GND1
10
MOSI_THRU
11
22
B4
NSS
12
21
VDD2
ePAD1
Isolation Barrier
3
Isolation Barrier
A2
A3
ePAD2
MOSI_THRU
11
22
B4
NSS
12
21
GND2
SCLK
13
20
GND2
SCLK
13
20
VDD2
MOSI
14
19
VDD2
MOSI
14
19
VDD2
MISO
15
18
DNC
MISO
15
18
DNC
NC
16
17
GND2
NC
16
17
GND2
Si83408xFA-IF
Si83418xFA-IF
Figure 6.3. 4-Channel Parallel/SPI Devices
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Si834x Data Sheet • Pin and Package Descriptions
Table 6.1. Si834x Pin Descriptions
62
Pin Name
Type
Description
A1 – A4
Input
B1 – B4
Sourcing/Sinking Output
OE
Input
FLT\
Open-drain Output
Active-low output that indicates diagnostic reports
LED1\ – LED4\
Open-drain Output
B1 – B4 output status indicators. Shows ON or OFF state of output
FLT_CLR
Input
Input to manually clear faults that are not cleared automatically
VDD2_WRN\
Open-drain Output
Active-low output that indicates a VDD2 Low-Voltage Warning
OPEN_CH\
Open-drain Output
Active-low output that indicates an open circuit on any output channel
MOSI_THRU
Push-pull Output
NSS
Input
SPI chip select
SCLK
Input
SPI clock
MOSI
Input
SPI input
MISO
Push-pull Output
GND1
Ground
Isolated logic interface ground
GND2
Ground
Isolated switch ground. All GND2 pins must be used and tied together
VDD1
Supply
Isolated logic interface power supply
VDD2
Supply
Isolated switch power supply. All VDD2 pins must be used and tied together
NC
Other
Not connected. Pin is not used and should be tied to GND1
DNC
Other
Do not connect. Pin must be left floating
RSVD
Other
Reserved without specific function. Pin must be tied to GND1
ePAD1
Ground
Exposed thermal pad for logic interface. Pad must be tied to GND1
ePAD2
Ground
Exposed thermal pad for switches. Pad must be tied to GND2
Input channels
Output channels
Output enable, active-high
SPI data out for cascading multiple Si834x devices together
SPI output
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Si834x Data Sheet • Pin and Package Descriptions
6.2 Package Drawing
32-Pin 9x9 DFN (DFN-32)
The figure below illustrates the package details for the Si834x in a 32-pin 9x9 DFN package. The table below lists the values for the
dimensions shown in the illustration.
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Si834x Data Sheet • Pin and Package Descriptions
Table 6.2. 32-Pin 9x9 DFN Package Diagram Dimensions1, 2, 3, 4
Dimension
MIN
MAX
A
0.8
0.90
A1
0
0.05
A2
0.65 REF
A3
0.203 REF
b
0.2
0.30
D
9 BSC
E
9 BSC
e
0.50 BSC
J
1.23
1.43
J1
2.31
2.51
K
2.45
2.65
K1
6.65
6.85
L
0.35
0.45
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.10
eee
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Si834x Data Sheet • Pin and Package Descriptions
6.3 Land Pattern
32-Pin 9x9 DFN (DFN-32)
The figure below illustrates the recommended land pattern details for the Si834x in a 32-pin 9x9 DFN package. The table below lists the
values for the dimensions shown in the illustration.
C1
Y1
X1
J2
J1
Y3
Y2
E
X2
X3
Table 6.3. PCB Land Pattern
Dimension
mm
C1
9.00
J1
2.64
J2
2.92
E
0.50
X1
0.30
Y1
0.80
X2
2.51
Y2
6.85
X3
1.43
Y3
2.65
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60mm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. An array of square openings with approximately 50% coverage may be used for each of the center ground pads (ePAD1 and
ePAD2).
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si834x Data Sheet • Pin and Package Descriptions
6.4 Top Marking
S i 8 3 4 U VWX Y
Y Y WW T T T T T T
e4
C C
Table 6.4. 32-Pin 9x9 DFN Top Marking Explanation
Line 1 Marking:
Base Part Number Ordering
Options
Si834 = Isolated Smart Switch series
U = Switch Type
0 = Sourcing output (high-side)
1 = Sinking output (low-side)
(See Ordering Guide for more
information)
V = Input & Output Configuration
4 = 4 channel output, parallel input only
8 = 4 channel output, SPI programmable
W = Switch Protection Configuration
A = All protection methods enabled, default configuration
X = Indicator Configuration
A = LEDn\ indicators, FLT\ indicator, VDD2_WRN\ indicator
B = LEDn\ indicators, FLT\ indicator, OPEN_CH\ indicator
C = LEDn\ indicators, FLT\ indicator, FLT_CLR input
D = LEDn\ indicators, FLT\ indicator
F = FLT\ indicator
Y = Isolation Rating
A = 1.5 kVRMS
Line 2 Marking
Line 3 Marking
66
YY = Year
WW = Workweek
Assigned by the assembly house. Corresponds to the year and workweek
of the mold date.
TTTTTT = Mfg Code
Manufacturing code from the Assembly Purchase Order form
CC = Country of Origin ISO Code
TW = Taiwan
Abbreviation
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Si834x Data Sheet • Revision History
7. Revision History
7.1 Revision 0.5
August 28, 2019
• Initial release.
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