SI8388P-IU

Si838x Data Sheet Bipolar Digital Field Inputs for PLCs and Industrial I/O Modules KEY FEATURES The Si838x provides eight input channels ideal for 24 V digital logic commonly used for industrial applications. These channels can either sink or source current and feature integrated safety rated isolation. In combination with a few external components, this provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input interface is based on Silicon Labs' ground-breaking CMOS based LED emulator technology which enables the bipolar capability (sinking or sourcing inputs) with no VDD required on the field side. The output interface from the Si838x device allows for low power operation with 2.25 V compliance. These products utilize Silicon Labs' proprietary CMOS-based isolation technology, supporting up to 2.5 kVRMS withstand voltage. This technology enables high CMTI (up to 300 kV/μs), lower propagation delays and channel skew, reduced variation with temperature and age, and tighter part-to-part matching. The Si838x offers longer service life and dramatically higher reliability compared to opto-coupled input solutions. • Bipolar digital interface with 24 V sinking or sourcing inputs • Eight total inputs in one package • High data rates of up to 2 Mbps • Safety rated integrated isolation of 2.5 kVRMS • Low input current of 1 mA typ • No VDD required on field side • High electromagnetic immunity • Selectable debounce filter times of up to 100 ms Product options include parallel or serialized outputs. Parallel outputs can be purchased with built-in, low-pass filters for improved noise immunity, reduced design complexity and cost. Cascading a total of 128 channels (16x Si838x) with a single MCU interface is possible with the Si8380S serial output option. The Si8380S also unlocks the ability to configure each channel with unique filtering behavior. • Configurable debounce filter modes available with SPI interface option • Transient immunity up to 300 kV/μs • Flow-through output configuration with eight outputs • Option for SPI interface with daisy-chain capability Safety Regulatory Approvals: • UL 1577 recognized • Up to 2500 VRMS for one minute Applications: • Programmable logic controllers • Industrial data acquisition • Distributed control systems • CNC machines • I/O modules • Motion control systems • Wide 2.25 to 5.5 V VDD operation • Wide operating temperature range • –40 to +125 °C • CSA component notice 5A approval • IEC 60950-1 • IEC 62368-1 • VDE certification conformity • VDE 0884-10 • CQC certification approval • GB4943.1 • Compliant to IEC 61131-2 • Type 1, 2, 3 • RoHS-compliant packages • QSOP-20 Si8380S Si8380P A1 1 20 B1 A1 1 e 19 B2 A2 2 e 18 B3 A3 3 17 B4 A4 4 16 VDD COM 5 15 GND COM 6 14 e e e 20 MISO e 19 MOSI e 18 NSS 17 SCLK 16 VDD 15 GND 14 MOSI_THRU e 13 NC NC NC 3 A4 4 COM 5 COM 6 A5 7 e B5 A5 7 A6 8 e 13 B6 A6 8 A7 9 e 12 B7 A7 9 e 12 A8 10 e 11 B8 A8 10 e 11 e silabs.com | Building a more connected world. e Isolation Barrier 2 A3 Isolation Barrier A2 SPI Rev. 1.0 Si838x Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Si838x Ordering Guide Ordering Part Number Output Interface Number of HighSpeed Channels Low-Pass Debounce Filter Delay1, 2 Package Type3 Isolation Rating Si8380S-IU Serial 0 0 ms 20-QSOP 2.5 kVRMS Si8380P-IU Parallel 0 0 ms 20-QSOP 2.5 kVRMS Si8382P-IU Parallel 2 0 ms 20-QSOP 2.5 kVRMS Si8384P-IU Parallel 4 0 ms 20-QSOP 2.5 kVRMS Si8388P-IU Parallel 8 0 ms 20-QSOP 2.5 kVRMS Si8380PF-IU Parallel 0 10 ms 20-QSOP 2.5 kVRMS Si8382PF-IU Parallel 2 10 ms 20-QSOP 2.5 kVRMS Si8384PF-IU Parallel 4 10 ms 20-QSOP 2.5 kVRMS Si8380PM-IU Parallel 0 30 ms 20-QSOP 2.5 kVRMS Si8382PM-IU Parallel 2 30 ms 20-QSOP 2.5 kVRMS Si8384PM-IU Parallel 4 30 ms 20-QSOP 2.5 kVRMS Si8380PS-IU Parallel 0 100 ms 20-QSOP 2.5 kVRMS Si8382PS-IU Parallel 2 100 ms 20-QSOP 2.5 kVRMS Si8384PS-IU Parallel 4 100 ms 20-QSOP 2.5 kVRMS Note: 1. Low-pass debounce filter delay applies to low-speed channels only. 2. All low-speed channels have a built-in 4 µs low-pass debounce filter delay, in addition to the low-pass filter delay listed in this table. See 3.6 Debounce Filter for details of the low-pass debounce filter operation. 3. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. 4. Additional filter and channel configurations available upon request. Contact Silicon Labs for more information. 5. “Si” and “SI” are used interchangeably. 6. An "R" at the end of the Ordering Part Number indicates tape and reel option. silabs.com | Building a more connected world. Rev. 1.0 | 2 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Bipolar LED Emulator Input . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Layout Recommendations . . . . . . . 3.4.1 Supply Bypass . . . . . . . . . 3.4.2 Output Pin Termination and State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 7 . 7 3.5 Serial Peripheral Interface . . . . 3.5.1 SPI Register Map . . . . . 3.5.2 SPI Communication Transactions 3.5.3 SPI Read Operation . . . . . 3.5.4 SPI Write Operation . . . . . 3.5.5 SPI Daisy-Chain Organization . 3.5.6 SPI Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . 7 . 8 . 9 . 9 .10 .11 3.6 Debounce Filter. . . . . . . 3.6.1 Debounce Control Registers . 3.6.2 Debounce Filtering Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 .12 .13 4. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 System Level Transitions . . . . . . . . . . . . . . . . . . . . . . . .14 4.2 IEC 61131-2 Compliance Options . . . . . . . . . . . . . . . . . . . . . . .15 4.3 Custom Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . .15 5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Typical Operating Characteristics. . . . .24 6. Pin and Package Definitions. . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Pin Descriptions and Block Diagrams . 7. Package Outline 8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 silabs.com | Building a more connected world. Rev. 1.0 | 3 Si838x Data Sheet System Overview 2. System Overview 2.1 Theory of Operation The operation of an Si838x channel is analogous to that of a bipolar opto-coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si838x channel is shown in the figure below. HF Transmitter e Modulator Isolation Barrier Ax/AHx VDD Demodulator Debounce B BH Bx/BHx COM Figure 2.1. Simplified Channel Diagram This product enables 24 V bipolar digital inputs to be connected to its input through a resistor network which acts as a voltage divider. Other digital voltage levels and characteristics can be implemented with simple modifications to the resistor network. See 4.2 IEC 61131-2 Compliance Options for resistor network recommendations. The inputs can be sourcing or sinking type. To enable this functionality, there is a diode bridge and an LED emulator at the front end of each input channel that drives an OOK (On-Off Key) modulator/demodulator across the capacitive isolation barrier. See 3.3 Bipolar LED Emulator Input for details on the input channel. On the output side, the signal is either passed directly to the output stage in the case of a high-speed channel (BHx), or the signal is routed through a debounce filter block in the case of a low-speed channel (Bx). Thus, the high-speed channel offers the highest performance with the least propagation delay, but also the worst noise immunity. With the addition of the debounce filter block on the lowspeed channel, precise noise control can be achieved. The debounce block is configured by selecting the debounce filter mode applied and the amount of debounce filter delay time desired. There are three debounce filter modes available: deglitch filter mode, low-pass filter mode, and blanking filter mode. There are four debounce filter delay time options available: no delay, or delays of 10, 30, or 100 milliseconds. Additionally, a built-in low-pass filter delay of 4 µs is always present in low-speed channels, regardless of user configuration options. The desired filter delay time for parallel output devices can be selected by part number in 1. Ordering Guide. This filter delay time selection applies to all low-speed channels present on the device. The only filter mode available for parallel output interface devices is the low-pass filter mode. In addition to the parallel output interface options available on the Si838x, there is also a serial output interface option. The Si8380S offers a four wire SPI interface with an additional MOSI_THRU output to facilitate the cascading of up to 16 Si8380S devices. Using the SPI interface detailed in section 3.5 Serial Peripheral Interface, the debounce filter type and filter delay time can each be controlled on a per channel basis. The debounce filter modes are explained in detail in 3.6 Debounce Filter. silabs.com | Building a more connected world. Rev. 1.0 | 4 Si838x Data Sheet Device Operation 3. Device Operation Table 3.1. Truth Table Summary VDD Input, Ax/AHx Output, Bx/BHx P1 ON HIGH P OFF LOW UP2 X Undetermined3 1. P = powered (> UVLO). 2. UP = Unpowered (< UVLO). 3. An undetermined state can be any value within the absolute maximum rating of the output channel. See Table 5.10 Absolute Maximum Ratings1 on page 23 for details. 3.1 Device Behavior During any period in which VDD is below the UVLO threshold, such as device start-up, the output Bx/BHx is in an undetermined state until VDD is brought above the UVLO threshold for a time period of approximately tSTART, after which Bx/BHx is immediately pulled low. Following this, the output is high when the current flowing from anode to cathode in the LED emulator is > IF(ON). Note that there is a propagation delay time (tP) between a valid change on the input and a valid change on the output. Also note that there is a similar rise (tR) and fall (tF) time that should be accounted for in any valid change of the output. Finally, for low-speed channels, there is an additional filter delay time added to the propagation delay time. See Table 5.2 Electrical Characteristics on page 16 for detailed propagation delay specifications for all channel configurations, as well as specifications for all other timing parameters defined here. Device startup, normal operation, and shutdown behavior are shown in the figure below. VDDHYS VDDUV+ VDDUVVDD IHYS IF(TH) Ax/AHx tSTART Bx/BHx tP tP tP tSTART tP tP 90% 50% 10% tR tF Figure 3.1. Si838x Timing Diagram silabs.com | Building a more connected world. Rev. 1.0 | 5 Si838x Data Sheet Device Operation 3.2 Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating range. During UVLO, the outputs from the device do not track the inputs to the device. For example, the device unconditionally enters UVLO when VDD falls below VDDUV– and exits UVLO when VDD rises above VDDUV+. During UVLO, the outputs are in an undetermined state and should be controlled using external components like a pull-up or pull-down resistor. See section 3.4.2 Output Pin Termination and State Control for circuit recommendations 3.3 Bipolar LED Emulator Input Each input channel on the Si838x can be modeled as a full bridge rectifier attached to an LED. A simplified equivalent circuit is depicted in Figure 3.2. Note that the model changes based on the whether the channel is sourcing or sinking current. The input current to the LED emulator is used to power the isolation channel transmitter and send the input signal across the isolation barrier. This eliminates the need for a power supply on the input side of the device. See section 2.1 Theory of Operation for a complete overview of the signal path through the device. I Ax/AHx 2.0 V e Ax/AHx = COM 3.1 k 21 COM I Ax/AHx 2.0 V 3.1 k 21 COM Figure 3.2. Bipolar LED Emulator Model 3.0 2.5 Input Voltage (V) 2.0 1.5 1.0 0.5 0.0 0 5 10 Input Current (mA) 15 20 Figure 3.3. Bipolar LED Emulator Model I-V Curve silabs.com | Building a more connected world. Rev. 1.0 | 6 Si838x Data Sheet Device Operation 3.4 Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with 109 Ω Note: 1. This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The Si838x provides a climate classification of 40/125/21. Table 5.8. IEC Safety Limiting Values1 Parameter Symbol Test Condition Max Unit QSOP-20 Safety Temperature TS Safety Current IS θJA = 105 °C/W 150 °C 240 mA 1.2 W VF = 2.8 V, VDD = 5 V, TJ = 150 °C, TA = 25 °C Power Dissipation PS Note: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 5.2 (QSOP-20) Thermal Derating Curve, Dependence of Safety Limiting Values per VDE on page 22. silabs.com | Building a more connected world. Rev. 1.0 | 21 Si838x Data Sheet Electrical Specifications Table 5.9. Thermal Characteristics Parameter IC Junction-to-Ambient Thermal Resistance Symbol QSOP-20 Unit θJA 105 °C/W 600 VDD = 2.5 V Safety Limiting Current (mA) 480 VDD = 3.3 V 360 VDD = 5.0 V 240 120 0 0 40 80 Ambient Temperature (°C) 120 160 Figure 5.2. (QSOP-20) Thermal Derating Curve, Dependence of Safety Limiting Values per VDE silabs.com | Building a more connected world. Rev. 1.0 | 22 Si838x Data Sheet Electrical Specifications Table 5.10. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit Storage Temperature TSTG –65 +150 °C Ambient Temperature TA –40 +125 °C Junction Temperature TJ — +150 °C IF(AVG) — 30 mA Peak Transient Input Current (< 1 µs pulse width, 300 ps) IFTR — 1 A Supply Voltage VDD –0.5 7 V Output Voltage VOUT –0.5 VDD+0.5 V Average Output Current IO(AVG) — 10 mA Input Power Dissipation PI — 480 mW Output Power Dissipation (includes 3 mA per channel for status LED) PO — 484 mW Total Power Dissipation PT — 964 mW Lead Solder Temperature (10 s) — 260 °C HBM Rating ESD 4 — kV Machine Model ESD 200 — V CDM 500 — V — 3000 VRMS Average Forward Input Current Maximum Isolation Voltage (1 s) Note: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions specified in the operational sections of this data sheet. silabs.com | Building a more connected world. Rev. 1.0 | 23 Si838x Data Sheet Electrical Specifications 5.1 Typical Operating Characteristics The typical performance characteristics depicted in the figures below are for information purposes only. Refer to Table 5.2 Electrical Characteristics on page 16 for actual specification limits. 3.0 2.5 TA = -40 °C TA = 25 °C Input Voltage (V) 2.0 TA = 125 °C 1.5 1.0 0.5 0.0 0 5 10 Input Current (mA) 15 20 Note: Input current and input voltages depicted in the figure above are absolute values and apply to both sourcing and sinking channel designs. Figure 5.3. Input Voltage vs. Input Current Over Temperature silabs.com | Building a more connected world. Rev. 1.0 | 24 Si838x Data Sheet Pin and Package Definitions 6. Pin and Package Definitions The Si838x consists of multiple dies in one package. Each package and bond-out serves a customer need and may reflect multiple bond options. The following packages are defined: QSOP-20. 1. Ordering Guide describes the part number and configuration for these products. Subsequent sections define the pins for each package type and the product block diagrams. 6.1 Pin Descriptions and Block Diagrams e 20 B1/BH1 A1 1 e 20 MISO A2/AH2 2 e 19 B2/BH2 A2 2 e 19 MOSI A3/AH3 3 e 18 B3/BH3 A3 3 e 18 NSS A4/AH4 4 e 17 B4/BH4 A4 4 e 17 SCLK COM 5 16 VDD COM 5 16 VDD 15 GND 14 MOSI_THRU COM 6 15 GND A5/AH5 7 e 14 A6/AH6 8 e A7/AH7 9 A8/AH8 10 Isolation Barrier 1 Isolation Barrier A1/AH1 SPI COM 6 B5/BH5 A5 7 e 13 B6/BH6 A6 8 e 13 NC e 12 B7/BH7 A7 9 e 12 NC e 11 B8/BH8 A8 10 e 11 NC Si8380P/Si8388P Si8380S e 20 BH1 AH1 1 e 20 BH1 AH2 2 e 19 BH2 AH2 2 e 19 BH2 A1 3 e 18 B1 AH3 3 e 18 BH3 A2 4 e 17 B2 AH4 4 e 17 BH4 COM 5 16 VDD COM 5 16 VDD COM 6 15 GND COM 6 15 GND A3 7 e 14 B3 A1 7 e 14 B1 A4 8 e 13 B4 A2 8 e 13 B2 A5 9 e 12 B5 A3 9 e 12 B3 A6 10 e 11 B6 A4 10 e 11 B4 Si8382P Isolation Barrier 1 Isolation Barrier AH1 Si8384P Figure 6.1. Si838x Pin Assignments and Block Diagrams silabs.com | Building a more connected world. Rev. 1.0 | 25 Si838x Data Sheet Pin and Package Definitions Table 6.1. Si838x Pin Descriptions Pin Name Description A1 – A8 Low-speed input channels AH1-AH8 High-speed input channels COM Common. Can be connected to ground for sinking inputs or the field supply for sourcing inputs B1-B8 Low-speed output channels BH1-BH8 High-speed output channels VDD Controller side power supply GND Controller side ground MOSI SPI, input SCLK SPI clock NSS SPI chip select MOSI_THRU MISO SPI serial data out for cascading multiple Si8380S devices (up to 16) SPI, output silabs.com | Building a more connected world. Rev. 1.0 | 26 Si838x Data Sheet Package Outline 7. Package Outline The figure below illustrates the package details for the 20-pin QSOP package. The table below lists the values for the dimensions shown in the illustration. Figure 7.1. 20-Pin QSOP Package Outline silabs.com | Building a more connected world. Rev. 1.0 | 27 Si838x Data Sheet Package Outline Table 7.1. Package Dimensions Dimension Min Max A — 1.75 A1 0.10 0.25 A2 1.25 — b 0.20 0.30 c 0.17 0.25 D 8.66 BSC E 6.00 BSC E1 3.91 BSC e 0.635 BSC L 0.40 L2 1.27 0.25 BSC h 0.25 0.50 θ 0° 8° aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.20 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline M0-137, Variation AD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 28 Si838x Data Sheet Land Pattern 8. Land Pattern The figure below illustrates the PCB land pattern details for the 20-pin QSOP package. The table below lists the values for the dimensions shown in the illustration. Figure 8.1. 20-Pin QSOP PCB Land Pattern Table 8.1. 20-Pin QSOP PCB Land Pattern Dimensions Dimension Feature mm C1 Pad Column Spacing 5.40 E Pad Row Pitch 0.635 X1 Pad Width 0.40 Y1 Pad Length 1.55 1. This Land Pattern Design is based on IPC-7351 design rules for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC), and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.0 | 29 Si838x Data Sheet Top Marking 9. Top Marking Figure 9.1. Si838x Top Marking (20-Pin QSOP) Table 9.1. Top Marking Explanation (20-Pin QSOP) Line 1 Marking: Base Part Number Si838 = 8-ch digital input isolator Ordering Options X = # of high-speed channels See 1. Ordering Guide for more information. Y = S, P S = serial outputs P = parallel outputs U = Debounce option None = No additional debounce filter delay time F = fast debounce filter delay time, 10 ms M = medium debounce filter delay time, 30 ms S = slow debounce filter delay time, 100 ms Line 2 Marking: YY = Year WW = Workweek Assigned by the Assembly House. Corresponds to the year and workweek of the mold date and manufacturing code from Assembly Purchase Order form. TTTTTT = Mfg Code silabs.com | Building a more connected world. Rev. 1.0 | 30 Si838x Data Sheet Revision History 10. Revision History Revision 1.0 April, 2019 • Reorganized document to improve readability • Updated content throughout the data sheet to improve readability, matched style guidelines, and corrected minor grammatical errors • Corrected the output state when device is unpowered in Table 3.1 Truth Table Summary on page 5 • Added 3.3 Bipolar LED Emulator Input to improve input channel design documentation • Added recommendation to control output states to 3.4.2 Output Pin Termination and State Control • Removed redundant specifications, added details and notes, and reorganized 5. Electrical Specifications • Added Input Voltage specifications to Table 5.2 Electrical Characteristics on page 16 • Expanded and clarified Propagation Delay specifications in Table 5.2 Electrical Characteristics on page 16 • Expanded and clarified Propagation Delay specifications in Table 5.2 Electrical Characteristics on page 16 • Defined capacitive load in test conditions for rise and fall time in Table 5.2 Electrical Characteristics on page 16 • Updated Table 5.4 Regulatory Information1 on page 20 to reflect latest certification status • Added surge voltage specification to Table 5.7 VDE 0884-10 Insulation Characteristics1 on page 21 • Corrected Safety Current specification in 4.2 IEC 61131-2 Compliance Options • Corrected plot in Figure 5.2 (QSOP-20) Thermal Derating Curve, Dependence of Safety Limiting Values per VDE on page 22 • Removed input voltage parameter from Table 5.10 Absolute Maximum Ratings1 on page 23 • Updated plot in Figure 5.3 Input Voltage vs. Input Current Over Temperature on page 24 • Corrected Line 1 Marking in Table 9.1 Top Marking Explanation (20-Pin QSOP) on page 30 Revision 0.5 April, 2016 • Initial release. silabs.com | Building a more connected world. Rev. 1.0 | 31 Smart. Connected. Energy-Friendly. Products Quality Support and Community www.silabs.com/products www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 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