Si840x
B IDIRECTIONAL I 2 C I SOLA TORS WITH U NIDIRECTIONAL
D IGITA L C HANNELS
Features
Independent, bidirectional SDA and
SCL isolation channels
Open drain outputs with 35 mA
sink current
60-year life at rated working voltage
High electromagnetic immunity
Wide operating supply voltage
3.0 to 5.5 V
I2C clocks up to 1.7 MHz Wide temperature range
–40 to +125 °C max
Unidirectional isolation channels
support additional system signals
Transient immunity 25 kV/µs
(Si8405)
RoHS-compliant packages
Up to 2500 VRMS isolation
SOIC-8 narrow body
SOIC-16 narrow body
UL, CSA, VDE recognition
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Supports
Applications
Isolated I2C, SMBus
Isolated digital power supply
communications
Power over Ethernet
Description
Motor Control Systems
Hot-swap applications
Intelligent Power systems
Ordering Information:
See page 25.
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The Si840x series of isolators are single-package galvanic isolation
solutions for I2C and SMBus serial port applications. These products are
based on Silicon Labs proprietary RF isolation technology and offer shorter
propagation delays, lower power consumption, smaller installed size, and
more stable operation with temperature and age versus opto couplers or
other digital isolators.
All devices in this family include hot-swap, bidirectional SDA and SCL
isolation channels with open-drain, 35 mA sink capability and operate to a
maximum frequency of 1.7 MHz. The 8-pin version (Si8400/01) supports
bidirectional SDA and SCL isolation; the Si8402 supports bidirectional SDA
and unidirectional SCL isolation, and the 16-pin version (Si8405) features
two unidirectional isolation channels to support additional system signals,
such as an interrupt or reset. All versions contain protection circuits to
guard against data errors if an unpowered device is inserted into a powered
system.
Small size, low installed cost, low power consumption, and short
propagation delays make the Si840x family the optimum solution for
isolating I2C and SMBus serial ports.
Safety Regulatory Approval
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1
(reinforced insulation)
Rev. 1.6 10/13
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Copyright © 2013 by Silicon Laboratories
Si840x
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Si840x
2
Rev. 1.6
Si840x
TABLE O F C ONTENTS
Section
Page
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1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4. Input and Output Characteristics for Non-I2C Digital Channels . . . . . . . . . . . . . . . . 15
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Typical Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. I2C Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.2. I2C Isolator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3. I2C Isolator Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4. I2C Isolator Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 22
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.6
3
Si840x
1. Electrical Specifications
Table 1. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
TSTG
–65
—
150
°C
TA
–40
—
125
°C
Supply Voltage (Revision A)3
VDD
–0.5
—
5.75
V
B)3
VDD
–0.5
—
6.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
IO
—
—
±10
mA
channels)
IO
—
—
±15
mA
Side B output current drive (I2C channels)
IO
—
—
±75
mA
Lead Solder Temperature (10 s)
—
—
260
°C
Maximum Isolation Voltage (1 s)
—
—
3600
VRMS
Storage Temperature2
Ambient Temperature Under Bias
Supply Voltage (Revision
Output Current Drive (non-I2C channels)
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Side A output current drive
(I2C
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "7.Ordering Guide" on page 25 for more information.
Table 2. Si840x Power Characteristics*
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C (See Figures 2 and 16 for test diagrams.)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Idda
Iddb
All channels = 0 dc
—
—
4.2
3.9
6.3
5.9
mA
mA
Idda
Iddb
All channels = 1 dc
—
—
2.3
1.9
3.5
2.9
mA
mA
Idda
Iddb
All channels = 1.7 MHz
—
—
3.2
2.9
4.8
4.4
mA
mA
AVDD current
BVDD current
Idda
Iddb
All non-I2C channels = 0
All I2C channels = 1
—
—
3.2
2.9
4.8
4.4
mA
mA
AVDD current
BVDD current
Idda
Iddb
All non-I2C channels = 1
All I2C channels = 0
—
—
6.2
6.0
9.3
9.0
mA
mA
AVDD current
BVDD current
Idda
Iddb
All non-I2C channels = 5 MHz
All I2C channels = 1.7 MHz
—
—
4.7
4.5
7.1
6.8
mA
mA
AVDD current
BVDD current
N
AVDD current
BVDD current
ot
Si8400/01/02 Supply Current
AVDD current
BVDD current
Si8405 Supply Current
*Note: All voltages are relative to respective ground.
4
Rev. 1.6
Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I2C Channels1
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Symbol
Logic Levels Side A
Logic Input Threshold2
Logic Low Output Voltages3
Input/Output Logic Low Level
Difference4
I2CVT (Side A)
I CVOL (Side A)
2
I2CV (Side A)
Test Condition
Min
Typ
Max
Unit
ISDAA = ISCLA = 3.0 mA
ISDAA = ISCLA = 0.5 mA
450
650
550
50
—
—
—
—
780
910
825
—
mV
mV
mV
mV
—
2.0
—
—
—
—
0.8
—
400
V
V
mV
—
2.0
10
µA
—
—
10
10
—
—
pF
pF
I2CVIL (Side B)
I2CVIH (Side B)
I2CVOL (Side B)
ISCLB = 35 mA
SCL and SDA Logic High
Leakage
Isdaa, Isdab
Iscla, Isclb
SDAA, SCLA = VSSA
SDAB, SCLB = VSSB
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Logic Levels Side B
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
Pin capacitance SDAA, SCLA,
SDAB, SDBB
CA
CB
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Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.450 V, VIH > 0.780 V.
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I2C Bus or SMBus” for additional information.
4. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5. Side A measured at 0.6 V.
Rev. 1.6
5
Si840x
Table 3. Si8400/01/02/05 Electrical Characteristics for Bidirectional I2C Channels1 (Continued)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C unless otherwise noted.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
—
1.7
MHz
Timing Specifications (Measured at 1.40 V Unless Otherwise Specified)
Propagation Delay
5 V Operation
Side A to side B rising5
Side A to side B falling5
Side B to side A rising
Side B to side A falling
3.3 V Operation
Side A to side B rising5
Side A to side B falling5
Side B to side A rising
Side B to side A falling
Fmax
Tphab
Tplab
Tphba
Tplba
No bus capacitance,
R1 = 1400,
R2 = 499,
See Figure 2
—
—
—
—
25
15
20
9.0
29
22
30
12
ns
ns
ns
ns
Tphab
Tplab
Tphba
Tplba
R1 = 806
R2 = 499
—
—
—
—
28
13
20
10
35
18
40
15
ns
ns
ns
ns
PWDAB
PWDBA
No bus capacitance,
R1 = 1400,
R2 = 499,
See Figure 2
—
—
9.0
11
15
20
ns
ns
PWDAB
PWDBA
R1 = 806,
R2 = 499
—
—
15
11
22
30
ns
ns
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Maximum I2C bus Frequency
Pulse width distortion
5V
Side A low to Side B low5
Side B low to Side A low
3.3 V
Side A low to Side B low5
Side B low to Side A low
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Notes:
1. All voltages are relative to respective ground.
2. VIL < 0.450 V, VIH > 0.780 V.
3. Logic low output voltages are 910 mV max from –10 to 125 °C at 3.0 mA.
Logic low output voltages are 955 mV max from –40 to 125 °C at 3.0 mA.
Logic low output voltages are 825 mV max from –10 to 125 °C at 0.5 mA.
Logic low output voltages are 875 mV max from –40 to 125 °C at 0.5 mA.
See “AN375: Design Considerations for Isolating an I2C Bus or SMBus” for additional information.
4. I2CV (Side A) = I2CVOL (Side A) – I2CVT (Side A). To ensure no latch-up on a given bus, I2CV (Side A) is the
minimum difference between the output logic low level of the driving device and the input logic threshold.
5. Side A measured at 0.6 V.
6
Rev. 1.6
Si840x
Table 4. Electrical Characteristics for Unidirectional Non-I2C Digital Channels (Si8402/05)
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
AVDD, BVDD
–0.4
4.8
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—
Maximum Data Rate
0
—
10
Mbps
Minimum Pulse Width
—
—
40
ns
Input Leakage Current
1
Output Impedance
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
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Timing Characteristics
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
Output Fall Time
tPHL, tPLH
See Figure 1
—
—
20
ns
PWD
See Figure 1
—
—
12
ns
tPSK(P-P)
—
—
20
ns
tPSK
—
—
10
ns
tr
C3 = 15 pF
See Figure 1 and
Figure 2
—
4.0
6.0
ns
tf
C3 = 15 pF
See Figure 1 and
Figure 2
—
3.0
4.3
ns
N
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Notes:
1. The nominal output impedance of a non-I2C isolator driver channel is approximately 85 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET.
When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with
controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
Rev. 1.6
7
Si840x
Table 5. Electrical Characteristics for All I2C and Non-I2C Channels
3.0 V < VDD < 5.5 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage Threshold
VDDUV+
AVDD, BVDD rising
2.15
2.3
2.5
V
VDD Negative-going Lockout
Hysteresis
VDDH–
AVDD, BVDD falling
45
75
95
mV
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
tSD
—
3.0
—
µs
tSTART
—
15
40
µs
Common Mode Transient
Immunity
Shut Down Time from UVLO
Start-up Time*
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*Note: Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing (Non-I2C Channels)
1.1. Test Circuits
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Figure 2 depicts the timing test diagram.
R1
C1
AVDD
R1
C1
BVDD
NC
C3
R2
NC
ASDA
BSDA
ADIN
BDOUT
ADOUT
BDIN
ASCL
BSCL
NC
NC
AGND
BGND
Si840x
C3
C2
Figure 2. Simplified Timing Test Diagram
8
Rev. 1.6
R2
C2
Si840x
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
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*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "7.Ordering Guide" on page 25.
Table 7. Insulation and Safety-Related Specifications
Parameter
Nominal Air Gap (Clearance)
Symbol
1
Nominal External Tracking (Creepage)1
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
Erosion Depth
Resistance (Input-Output)2
Capacitance
(Input-Output)2
ot
Input Capacitance3
Test Condition
Value
Unit
NB SOIC-8
NB SOIC-16
L(1O1)
4.9
4.9
mm
L(1O2)
4.01
4.01
mm
0.008
0.008
mm
600
600
VRMS
ED
0.040
0.019
mm
RIO
1012
1012
1.0
2.0
pF
4.0
4.0
pF
PTI
CIO
IEC60112
f = 1 MHz
CI
N
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “8. Package Outline:
8-Pin Narrow Body SOIC” and “10. Package Outline: 16-Pin Narrow Body SOIC”. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-8 package and 4.7 mm minimum for the NB SOIC-16 package.
UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the
clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 package and 3.9 mm minimum for the NB
SOIC-16 package.
2. To determine resistance and capacitance, the Si840x, SO-16, is converted into a 2-terminal device. Pins 1–8 (1-4, SO8) are shorted together to form the first terminal and pins 9–16 (5–8, SO-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Rev. 1.6
9
Si840x
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Condition
Basic Isolation Group
Specification
Material Group
Installation Classification
I
Rated Mains Voltages < 150 VRMS
I-IV
Rated Mains Voltages < 300 VRMS
I-III
Rated Mains Voltages < 400 VRMS
I-II
Rated Mains Voltages < 600 VRMS
I-II
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Characteristic
Unit
560
V peak
VIORM
Maximum Working Insulation Voltage
Input to Output Test Voltage
V peak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1050
VIOTM
t = 60 sec
4000
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Transient Overvoltage
Test Condition
2
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
V peak
>109
RS
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Case Temperature
Symbol
Test Condition
TS
IS
N
ot
Safety Input Current
Device Power Dissipation2
JA = 105 °C/W (NB SOIC-16),
140 °C/W (NB SOIC-8)
AVDD, BVDD = 5.5 V,
TJ = 150 °C, TA = 25 °C
PD
NB
SOIC-8
NB
SOIC-16
Unit
150
150
°C
160
210
mA
220
275
W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 3 and Figure 4.
2. The Si840x is tested with AVDD, BVDD = 5.5 V; TJ = 150 ºC; C1, C2 = 0.1 µF; C3 = 15 pF; R1, R2 = 3kinput 1 MHz
50% duty cycle square wave.
10
Rev. 1.6
Si840x
Table 11. Thermal Characteristics
Parameter
Symbol
JA
IC Junction-to-Air Thermal Resistance
NB
SOIC-8
NB
SOIC-16
Unit
140
105
°C/W
400
300 270
200
AVDD, BVDD = 3.6 V
160
AVDD, BVDD = 5.5 V
100
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Safety-Limiting Values (mA)
Test Condition
0
0
50
100
150
Case Temperature (ºC)
200
Figure 3. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
400
350
300
AVDD , BVDD = 3.6 V
N
ot
Safety-Limiting Current (mA)
500
210
200
AVDD , BVDD = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 4. NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.6
11
Si840x
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single unidirectional Si84xx channel is
shown in Figure 5.
Transmitter
Receiver
RF
OSCILLATOR
A
DEMODULATOR
R
N eco
ew m
D me
es n
ig de
ns d
fo
r
MODULATOR
SemiconductorBased Isolation
Barrier
B
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
N
ot
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
12
Rev. 1.6
Si840x
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO–
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Under Voltage Lockout
UVLO+
UVLO-
AVDD
UVLO+
UVLO-
BVDD
tSD
tSTART
tSTART
tPHL
tPLH
N
tSTART
ot
INPUT
R
N eco
ew m
D me
es n
ig de
ns d
fo
r
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own under
voltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally
enters UVLO when AVDD falls below AVDDUVLO– and exits UVLO when AVDD rises above AVDDUVLO+. Side B
operates the same as Side A with respect to its BVDD supply.
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.6
13
Si840x
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with
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