Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV)
Data Sheet
Low-Power, Single and Dual-Channel Digital Isolators
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of
these products remain stable across wide temperature ranges and throughout device
service life for ease of design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. Ordering options include a choice of isolation ratings (up
to 5 kV) and a selectable fail-safe operating mode to control the default output state during power loss. All products are safety certified by UL, CSA, and VDE, and products in
wide-body packages support reinforced insulation withstanding up to 5 kVRMS.
Applications
•
•
•
•
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
•
•
•
•
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
KEY FEATURES
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
• Up to 5000 VRMS isolation
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
• < 4.6 mA/channel at 100 Mbps
• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output
• Precise timing (typical)
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
• VDE certification conformity
• IEC 60747-5-5 (VDE0884 Part 5)
• EN60950-1 (reinforced insulation)
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Features List
1. Features List
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
• Up to 5000 VRMS isolation
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
• < 4.6 mA/channel at 100 Mbps
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• Schmitt trigger inputs
• Selectable fail-safe mode
• Default high or low output
• Precise timing (typical)
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
Rev. 1.4 | 1
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide1,2,3
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Maximum
Data Rate
(Mbps)
Default
Output
State
Isolation
Rating
Temp
Range
Package
Type
Si8422AB-D-IS
1
1
1
High
2.5 kVrms
–40 to 125 °C
NB SOIC-8
Si8422BB-D-IS
1
1
150
High
Si8423AB-D-IS
2
0
1
High
Si8423BB-D-IS
2
0
150
High
Si8410AD-D-IS4
1
0
1
Low
5.0 kVrms
–40 to 125 °C
WB SOIC-16
Si8410BD-D-IS4
1
0
150
Low
Si8420AD-D-IS4
2
0
1
Low
Si8420BD-D-IS4
2
0
150
Low
Si8421AD-D-IS4
1
1
1
Low
Si8421BD-D-IS4
1
1
150
Low
Si8422AD-D-IS
1
1
1
High
Si8422BD-D-IS
1
1
150
High
Si8423AD-D-IS
2
0
1
High
Si8423BD-D-IS
2
0
150
High
1. All devices >1 kVRMS are AEC-Q100 qualified.
2. “Si” and “SI” are used interchangeably.
3. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard classifications.
4. Refer to Si8410/20/21 data sheet for information regarding 2.5 kV rated versions of these products.
5. An "R" at the end of the part number denotes tape and reel packaging option.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3. Functional Description
3.1 Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si84xx channel is shown in the figure below.
Transmitter
Receiver
RF
OSCILLATOR
A
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 3.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 3.2. Modulation Scheme
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3.2 Eye Diagram
The figure below illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 3.3. Eye Diagram
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
4. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 4.1 Device Behavior during Normal Operation on
page 6, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to
determine outputs when power supply (VDD) is not present.
Table 4.1. Si84xx Logic Operation Table
VI Input1,4
VDDI State1,2,3
VDDO State1,2,3
VO Output1,4
H
P
P
H
L
P
P
L
X5
UP
P
H6 (Si8422/23)
L6 (Si8410/20/21)
X5
P
UP
Undetermined
Comments
Normal operation.
Upon transition of VDDI from unpowered to powered,
VO returns to the same state as VI in less than 1 μs.
Upon transition of VDDO from unpowered to powered,
VO returns to the same state as VI within 1 μs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.72.60 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See Section 2. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have
default output state = H, and some have default output state = L, depending on the ordering part number (OPN).
4.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
4.2 Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below
its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter
or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO
when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tSD
tSTART
tSTART
tSTART
tPHL
tPLH
OUTPUT
Figure 4.1. Device Behavior during Normal Operation
4.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with 109
>109
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
Characteristic
WB
SOIC-16
VIORM
Input to Output Test Voltage
Transient Overvoltage
Test Condition
RS
Unit
Vpeak
Vpeak
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21.
Table 5.8. IEC Safety Limiting Values1
Parameter
Symbol
Case Temperature
TS
Safety Input, Output, or Supply Current
IS
Device Power Dissipation2
PD
Test Condition
θJA = 140
°C/W (NB
SOIC-8), 100
°C (WB SOIC-16),
VI = 5.5 V, TJ
= 150 °C, TA
= 25 °C
Max
Unit
WB SOIC-16
NB SOIC-8
150
150
°C
220
160
mA
150
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 5.2 (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5 on page 23 and Figure 5.3 (NB SOIC-8) Thermal Derating Curve, Dependence
of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5 on page 23.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.9. Thermal Characteristics
Parameter
Safety-Limiting Values (mA)
IC Junction-to-Air Thermal Resistance
Symbol
WB SOIC-16
NB SOIC-8
Unit
θJA
100
140
°C/W
500
460
VDD1, VDD2 = 2.70 V
375 360
250
VDD1, VDD2 = 3.3 V
220
VDD1, VDD2 = 5.5 V
125
0
0
50
100
150
Case Temperature (ºC)
200
Safety-Limiting Values (mA)
Figure 5.2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
400
320
VDD1, VDD2 = 2.70 V
300 270
200
VDD1, VDD2 = 3.3 V
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
Case Temperature (ºC)
200
Figure 5.3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.10. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
Storage Temperature2
TSTG
–65
—
150
C°
Operating Temperature
TA
–40
—
125
C°
Junction Temperature
TJ
—
—
150
°C
VDD1, VDD2
–0.5
—
6.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive Channel
IO
—
—
10
mA
Lead Solder Temperature (10 s)
—
—
260
C°
Maximum Isolation Voltage (1 s) NB SOIC-8
—
—
4500
VRMS
Maximum Isolation Voltage (1 s) WB SOIC-16
—
—
6500
VRMS
Supply Voltage
Notes:
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Pin Descriptions
6. Pin Descriptions
6.1 Pin Descriptions (Wide-Body SOIC)
GND2
GND1
NC
VDD1
A1
RF
XMITR
NC
NC
I
s
o
l
a
t
i
o
n
RF
RCVR
GND1
NC
Si8410 WB SOIC-16
GND2
GND1
NC
NC
VDD2
VDD1
B1
A1
RF
XMITR
NC
A2
RF
XMITR
NC
NC
NC
GND1
GND2
NC
I
s
o
l
a
t
i
o
n
GND2
GND1
NC
NC
VDD2
VDD1
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
RCVR
NC
NC
NC
GND1
Si8420/23 WB SOIC-16
GND2
NC
I
s
o
l
a
t
i
o
n
GND2
GND1
NC
NC
VDD2
VDD1
NC
RF
RCVR
B1
A1
RF
RCVR
RF
XMITR
B2
A2
RF
RF
XMITR
XMITR
NC
NC
NC
GND1
GND2
Si8421 WB SOIC-16
I
s
o
l
a
t
i
o
n
VDD2
RF
XMITR
B1
RF
RCVR
B2
NC
NC
NC
Si8422 WB SOIC-16
GND2
Figure 6.1. Wide-Body SOIC
Table 6.1. Pin Descriptions
Name
SOIC-16 Pin#
SOIC-16 Pin#
Type
Description
Si8410
Si842x
GND1
1
1
Ground
NC1
2, 5, 6, 8,10,
11, 12, 15
2, 6, 8,10,
11, 15
No Connect
VDD1
3
3
Supply
A1
4
4
Digital I/O
Side 1 digital input or output.
A2
NC
5
Digital I/O
Side 1 digital input or output.
GND1
7
7
Ground
Side 1 ground.
GND2
9
9
Ground
Side 2 ground.
B2
NC
12
Digital I/O
Side 2 digital input or output.
B1
13
13
Digital I/O
Side 2 digital input or output.
VDD2
14
14
Supply
Side 2 power supply.
GND2
16
16
Ground
Side 2 ground.
Side 1 ground.
NC
Side 1 power supply.
Note:
1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Pin Descriptions
6.2 Pin Descriptions (Narrow-Body SOIC)
VDD1
A1
RF
RCVR
A2
RF
RF
RCVR
XMITR
I
s
o
l
a
t
i
o
n
VDD1
VDD2
RF
XMITR
B1
A1
RF
XMITR
RF
XMITR
RCVR
B2
A2
RF
XMITR
GND2
GND1
GND1
Si8422 NB SOIC-8
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
B1
RF
RCVR
B2
GND2
Si8423 NB SOIC-8
Figure 6.2. Narrow-Body SOIC
Name
SOIC-8 Pin#
Type
Description
Si842x
VDD1
1
Supply
Side 1 power supply.
GND1
4
Ground
Side 1 ground.
A1
2
Digital I/O
Side 1 digital input or output.
A2
3
Digital I/O
Side 1 digital input or output.
B1
7
Digital I/O
Side 2 digital input or output.
B2
6
Digital I/O
Side 2 digital input or output.
VDD2
8
Supply
Side 2 power supply.
GND2
5
Ground
Side 2 ground.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
7. Package Outlines
7.1 Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the Si84xx Digital Isolator. The table below lists the values for the dimensions shown
in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC
Table 7.1. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
—
2.65
A1
0.1
0.3
D
10.3 BSC
E
10.3 BSC
E1
7.5 BSC
b
0.31
0.51
c
0.20
0.33
e
1.27 BSC
h
0.25
0.75
L
0.4
1.27
θ
0°
7°
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
7.2 Package Outline (8-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si84xx. The table below lists the values for the dimensions shown in the illustration.
Figure 7.2. 8-pin Small Outline Integrated Circuit (SOIC) Package
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
Table 7.2. Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
0°
8°
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Land Patterns
8. Land Patterns
8.1 Land Pattern (16-Pin Wide-Body SOIC)
The figure below illustrates the recommended land pattern details for the Si84xx in a 16-pin wide-body SOIC. The table below lists the
values for the dimensions shown in the illustration.
Figure 8.1. 16-Pin SOIC Land Pattern
Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
9.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Land Patterns
8.2 Land Pattern (8-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si84xx in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 8.2. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 8.2. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Top Markings
9. Top Markings
9.1 Top Marking (16-Pin Wide Body SOIC)
Si84XYSV
YYWWTTTTTT
e4
TW
Figure 9.1. Isolator Top Marking
Table 9.1. Top Marking Explanation
Line 1 Marking: Base Part Number
Ordering Options
(See 2. Ordering Guide for more information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)1,2
S = Speed Grade
A = 1 Mbps
B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking: YY = Year
WW = Workweek
TTTTTT = Mfg Code
Line 3 Marking: Circle = 1.7 mm Diameter
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
Manufacturing code from assembly house.
“e4” Pb-Free Symbol.
(Center-Justified)
Country of Origin ISO Code Abbreviation
TW = Taiwan.
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Top Markings
9.2 Top Marking (8-Pin Narrow-Body SOIC)
Si84XYSV
YYWWRF
e3 AIXX
Figure 9.2. Isolator Top Marking
Table 9.2. Top Marking Explanation
Line 1 Marking: Base Part Number
Ordering Options
(See 2. Ordering Guide for more information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)1,2
S = Speed Grade
A = 1 Mbps
B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Line 3 Marking: Circle = 1.1 mm Diameter
“e3” Pb-Free Symbol.
Left-Justified
First two characters of the manufacturing code.
A = Assembly Site
Last four characters of the manufacturing code.
I = Internal Code
XX = Serial Lot Number
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Document Change List
10. Document Change List
10.1 Revision 0.1
• Initial release.
10.2 Revision 0.1 to Revision 1.0
• Updated features list.
• Updated transient immunity.
• Removed block diagram from front page.
• Added chip graphics on front page.
• Added Peak Eye Diagram jitter in Table 5.2 Electrical Characteristics on page 9 through Table 5.4 Electrical Characteristics1 on
page 17.
• Updated transient immunity
• Moved Table 4.1 Si84xx Logic Operation Table on page 5 to Section 4. Device Operation.
• Added Section 4. Device Operation.
• Added Section 4.4 Fail-Safe Operating Mode.
• Moved Section 4.5 Typical Performance Characteristics.
• Deleted RF Radiated Emissions section.
• Deleted RF Magnetic and Common-Mode Transient Immunity section.
• Updated MSL rating to MSL2A.
10.3 Revision 1.0 to Revision 1.1
• Numerous text edits.
• Added table notes to Table 9.1 Top Marking Explanation on page 32 and Table 9.2 Top Marking Explanation on page 33.
10.4 Revision 1.1 to Revision 1.2
• Updated Timing Characteristics in Table 5.2 Electrical Characteristics on page 9 through Table 5.4 Electrical Characteristics1 on
page 17.
10.5 Revision 1.2 to Revision 1.3
• Added references to AEC-Q100 qualified throughout.
• Changed all 60747-5-2 references to 60747-5-5.
• Updated Table 2.1 Ordering Guide1,2,3 on page 2.
• Added table notes 1 and 2.
• Removed references to moisture sensitivity levels.
• Added Revision D ordering information.
• Removed older revisions.
• Updated Section 9.1 Top Marking (16-Pin Wide Body SOIC).
10.6 Revision 1.3 to Revision 1.4
September 16, 2016
• Updated data sheet format.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.4 | 34
Table of Contents
1. Features List
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2. Ordering Guide
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3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Theory of Operation .
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3.2 Eye Diagram .
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4. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Device Startup
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4.2 Under Voltage Lockout .
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4.3 Layout Recommendations.
4.3.1 Supply Bypass . . . .
4.3.2 Pin Connections . . .
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4.4 Fail-Safe Operating Mode .
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4.5 Typical Performance Characteristics .
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5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Pin Descriptions (Wide-Body SOIC)
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6.2 Pin Descriptions (Narrow-Body SOIC) .
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7. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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7.1 Package Outline (16-Pin Wide Body SOIC) .
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7.2 Package Outline (8-Pin Narrow Body SOIC).
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8. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.1 Land Pattern (16-Pin Wide-Body SOIC) .
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9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.1 Top Marking (16-Pin Wide Body SOIC) .
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9.2 Top Marking (8-Pin Narrow-Body SOIC) .
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10. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . .
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10.1 Revision 0.1 .
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10.2 Revision 0.1 to Revision 1.0.
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10.3 Revision 1.0 to Revision 1.1.
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10.4 Revision 1.1 to Revision 1.2.
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10.5 Revision 1.2 to Revision 1.3.
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10.6 Revision 1.3 to Revision 1.4.
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Table of Contents
35
Smart.
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Energy-Friendly.
Products
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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