Si87xx
5 K V LED E MULATOR I N PU T , O PEN C OLLECTOR
O UTPUT I SOLA TORS
Features
Pin-compatible, drop-in upgrades for
popular high-speed digital
optocouplers
Performance and reliability
advantages vs. optocouplers
Resistant to temperature, age and
forward current effects
10x lower FIT rate for longer
service life
Higher common-mode transient
immunity: >50 kV/µs typical
Lower power and forward input
diode current
PCB footprint compatible with
optocoupler packaging
Wide range of product options
1 channel diode emulator input
3 to 30 V open collector output
Propagation delay 30 ns
Data rates dc to 15 Mbps
Up to 5000 VRMS isolation and 10 kV
surge protection
AEC-Q100 qualified
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
LGA8
Pin Assignments:
See page 20
SOIC-8, DIP8, LGA8
Open Collector Output
Applications
Industrial automation
Isolated data acquisition
Motor controls and drives
Test and measurement equipment
Isolated switch mode power supplies
SDIP6
Open Collector Output
Safety Regulatory Approvals
UL 1577 recognized
Up
to 5000 Vrms for 1 minute
CSA component notice 5A
approval
IEC
60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC60747-5-2/VDE0884
Part 10
(basic/reinforced insulation)
CQC certification approval
GB4943.1
SOIC-8, DIP8, LGA8
Open Collector Output
with 20 k Pull-up Resistor
Description
The Si87xx isolators are pin-compatible, one-channel, drop-in
replacements for popular optocouplers with data rates up to 15 Mbps.
These devices isolate high-speed digital signals and offer performance,
reliability, and flexibility advantages not available with optocoupler
solutions. The Si87xx series is based on Silicon Labs' proprietary CMOS
isolation technology for low-power and high-speed operation and are
resistant to the wear-out effects found in optocouplers that degrade
performance with increasing temperature, forward current, and device
age. As a result, the Si87xx series offer longer service life and
dramatically higher reliability compared to optocouplers. Ordering options
include open collector output with and without integrated pull-up resistor
and output enable options.
Rev. 1.1 4/14
Copyright © 2014 by Silicon Laboratories
SOIC-8, DIP8, LGA8
Open Collector Output
with Output Enable
Patent pending
Si87xx
Si87xx
Functional Block Diagram
VDD
Diode
Emulator
A1
REC
XMIT
IF
Output
Stage
OUT
(Open-Collector)
C1
GND
2
Rev. 1.1
Si87xx
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. Output Circuit Design and Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions (SOIC-8, DIP8, LGA8) Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Pin Descriptions (SOIC-8, DIP8, LGA8) Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Pin Descriptions (SDIP6) Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Pin Descriptions (SOIC-8, DIP8, LGA8) 20 kW Pull-Up Resistor . . . . . . . . . . . . . . . . . . 21
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
13. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.1. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.2. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 34
18.3. Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
18.4. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.5. Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.6. Top Marking Explanation (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.7. Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18.8. Top Marking Explanation (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Rev. 1.1
3
Si87xx
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VDD
3
—
30
V
3
6
3
—
—
—
15
30
15
mA
mA
mA
–40
—
125
°C
VDD Supply Voltage
IF(ON)
(see Figure 1)
Input Current
Si87xxA Devices
Si87xxB Devices
Si87xxC Devices
Operating Temperature (Ambient)
TA
Table 2. Electrical Characteristics
VDD = 5 V; GND = 0 V; TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
3
—
30
V
Output high or low (VDD = 5 to 30 V)
—
—
1.7
mA
DC Parameters
Supply Voltage
VDD
(VDD–GND)
Input Current Threshold
IF(TH)
Si87xxA devices
Si87xxB devices
Si87xxC devices
—
—
—
—
—
—
1.8
3.6
1.8
mA
mA
mA
Input Current Hysteresis
IHYS
Si87xxA devices
Si87xxB devices
Si87xxC devices
—
—
—
0.17
0.34
0.17
—
—
—
mA
mA
mA
Supply Current
IDD
Input Forward Voltage
(OFF)
VF(OFF) Measured at ANODE with respect to
CATHODE.
—
—
1
V
Input Forward Voltage
(ON)
VF(ON)
Measured at ANODE with respect to
CATHODE.
1.6
—
2.8
V
—
—
15
15
—
—
pF
pF
IOL =3 mA, VDD = 3.3 or 5 V
IOL =13 mA, VDD = 5.5 V
—
—
—
—
0.4
0.7
V
V
—
—
—
—
0.5
1
µA
µA
Peak DC collector current drive
(VDD = 5 V)
—
50
—
mA
—
—
54
—
20
—
k
2
—
30
V
—
—
0.8
V
Input Capacitance
CI
Logic Low Output
Voltage
VOL
Logic High Output
Current
IOH
Peak Output Current
IOPK
Output Low Impedance
ROL
Pull-up Resistor
Enable High Min
Enable Low Max
Enable High Current
Draw
Enable Low Current
Draw
4
RPU
f = 100 kHz
VF = 0 V,
VF = 2 V
VDD = VOUT = 5.5 V
VDD = VOUT = 24 V
Using internal pull-up
VEH
VEL
IEH
VDD = VEH = 5 V
—
20
—
µA
IEL
VDD =5 V, VEL = 0 V
—
–10
0
µA
Rev. 1.1
Si87xx
Table 2. Electrical Characteristics (Continued)
VDD = 5 V; GND = 0 V; TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
MBPS
MBPS
MBPS
AC Switching Parameters (VDD =5 V, RL = 350 , CL = 15 pF)
Maximum Data Rate
FDATA
Si87xxA devices
Si87xxB devices
Si87xxC devices
DC
DC
DC
—
—
—
15
15
1
Minimum Pulse Width
MPW
Si87xxA devices
Si87xxB devices
Si87xxC devices
66
66
1
—
—
—
—
—
—
ns
ns
µs
Propagation Delay
(Low-to-High)
tPLH
CL = 15 pF using 350 pull-up
—
—
60
ns
Propagation Delay
(High-to-Low)
tPHL
CL = 15 pF using 350 pull-up
—
—
60
ns
Pulse Width Distortion
PWD
| tPLH – tPHL |
—
—
20
ns
—
—
20
ns
15
—
ns
Propagation Delay
Skew
Rise Time
Fall Time
Device Startup Time
Common Mode
Transient Immunity
tPSK(p-p) tPSK(P-P) is the magnitude of the difference in prop delays between different units operating at same supply
voltage, load, and ambient temp.
tR
CL = 15 pF using 350 pull-up
—
tF
CL = 15 pF using 350 pull-up
—
5
—
ns
—
—
40
µs
CMTI
Output = low or high
VCM =1500 V (See Figure 2)
IF = 3 mA for Si87xxA devices
IF = 6 mA for Si87xxB devices
IF = 3 mA for Si87xxC devices
20
35
20
35
50
35
—
—
—
kV/µs
kV/µs
kV/µs
tSTART
Rev. 1.1
5
Si87xx
10
Anode
Anode
ESD
e
2.2 V
700
Cathode
Cathode
AnodetoCathodeVoltage[V]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
DiodeEmulatorInputCurrent[mA]
Figure 1. Diode Emulator Model and I-V Curve
6
Rev. 1.1
30
Si87xx
Input Signal
Switch
267
Si87xx
Anode
VDD
348
5V
Isolated
Supply
Isolated
Ground
12 V
Supply
VO
Cathode
Oscilloscope
GND
Input
High Voltage
Differential
Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 2. Common Mode Transient Immunity Characterization Circuit
Rev. 1.1
7
Si87xx
Table 3. Regulatory Information*
CSA
The Si87xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working
voltage.
60601-1: Up to 250 VRMS reinforced insulation working voltage; up to 500 VRMS basic insulation working voltage.
VDE
The Si87xx is certified according to IEC60747 and VDE0884. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1414 Vpeak for basic insulation working voltage.
VDE0884 Part 10: Up to 1414 Vpeak for reinforced insulation working voltage.
UL
The Si87xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si87xx is certified under GB4943.1-2011. For more details, see File V2012CQC001041.
Rated up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "9.Ordering Guide" on page 22.
Table 4. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
SOIC-8
DIP8
SDIP6
LGA8
Unit
Nominal Air Gap (Clearance)
L(IO1)
4.7 min
7.2 min
9.6 min
10.0 min
mm
Nominal External Tracking
(Creepage)
L(IO2)
3.9 min
7.0 min
8.3 min
10.0 min
mm
0.016
0.016
0.016
0.016
mm
600
600
600
600
V
0.031
0.031
0.057
0.021
mm
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
Resistance (Input-Output)*
RIO
Capacitance (Input-Output)*
CIO
IEC60112
12
f = 1 MHz
12
10
10
1
1
10
12
1
12
10
1
pF
*Note: To determine resistance and capacitance, the Si87xx is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6) are
shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second terminal.
The parameters are then measured between these two terminals.
8
Rev. 1.1
Si87xx
Table 5. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Specification
Test Condition
SOIC-8
DIP8
SDIP6
LGA8
I
I
I
I
Basic Isolation Group
Material Group
Installation
Classification
Rated Mains Voltages <
150 VRMS
I-IV
I-IV
I-IV
I-IV
Rated Mains Voltages <
300 VRMS
I-IV
I-IV
I-IV
I-IV
Rated Mains Voltages <
450 VRMS
I-III
I-III
I-IV
I-IV
Rated Mains Voltages <
600 VRMS
I-III
I-III
I-IV
I-IV
Rated Mains Voltages <
1000 VRMS
—
—
—
I-III
Table 6. IEC 60747-5-2 Insulation Characteristics*
Parameter
Symbol
Test Condition
Characteristic
Unit
SOIC-8
DIP8
SDIP6
LGA8
630
891
1140
1414
V peak
1181
1671
2138
2652
V peak
VPR
Method b1
(VIORM x 1.875 = VPR,
100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 sec
6000
6000
8000
8000
V peak
Surge Voltage
VIOSM
1.2 s rise, 50 s fall 50%
10
10
10
10
kV peak
2
2
2
2
>109
>109
>109
>109
Maximum Working
Insulation Voltage
Input to Output Test
Voltage
VIORM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at
TS, VIO = 500 V
RS
*Note: This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety
data is ensured by protective circuits. The Si87xx provides a climate classification of 40/125/21.
Rev. 1.1
9
Si87xx
Table 7. IEC Safety Limiting Values
Parameter
Symbol
Case Temperature
TS
Input Current
IS
Output Power
PS
Test Condition
JA = 110 °C/W (SOIC-8),
110 °C/W (DIP8),
105 °C/W (SDIP6),
220 °C (LGA8),
VF =2.8 V, TJ = 140 °C,
TA = 25 °C
Max
DIP8
SDIP6
LGA8
140
140
140
140
°C
370
370
390
185
mA
1
1
1
0.5
W
Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3, 4, 5, and 6.
10
Rev. 1.1
Unit
SOIC-8
Si87xx
Table 8. Thermal Characteristics
Parameter
IC Junction-to-Air Thermal
Resistance
OutputPo
owerͲ Ps,InputCurrentͲ Is
Typ
Symbol
JA
SOIC-8
DIP8
SDIP6
LGA8
110
110
105
220
Unit
ºC/W
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
OutputPo
owerͲ Ps,InputCurrentͲ Is
Figure 3. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884 part 10
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
Figure 4. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884 part 10
Rev. 1.1
11
OutputPo
owerͲ Ps,InputCurrentͲ Is
Si87xx
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
OutputPo
owerͲ Ps,InputCurrentͲ Is
Figure 5. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884 part 10
600
500
Ps(mW)
400
300
Is(mA)
200
100
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
Figure 6. (LGA8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884 part 10
12
Rev. 1.1
Si87xx
Table 9. Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Unit
TSTG
–65
+150
°C
Operating Temperature
TA
–40
+125
°C
Junction Temperature
TJ
—
+140
°C
IF(AVG)
—
—
—
15
30
15
mA
mA
mA
Peak Transient Input Current
(< 1 µs pulse width, 300 ps)
IFTR
—
1
A
Reverse Input Voltage
VR
—
0.3
V
Supply Voltage
VDD
–0.5
36
V
Output Voltage
VOUT
–0.5
36
V
Enable Voltage
VOUT
–0.5
VDD+0.5
V
Output Sink Current
ISINK
—
15
mA
IO(AVG)
—
8
mA
IOPK
—
75
mA
Input Power Dissipation
PI
—
90
mW
Output Power Dissipation
PO
—
50
mW
Total Power Dissipation
PT
—
140
mW
Lead Solder Temperature (10 s)
—
260
°C
HBM Rating ESD
3
—
kV
Machine Model ESD
200
—
V
CDM
500
—
V
Maximum Isolation Voltage (1 s) SOIC-8
—
4500
VRMS
Maximum Isolation Voltage (1 s) DIP8
—
4500
VRMS
Maximum Isolation Voltage (1 s) SDIP6
—
6500
VRMS
Maximum Isolation Voltage (1 s) LGA8
—
6500
VRMS
Storage Temperature
Average Forward Input Current
Si87xxA Devices
Si87xxB Devices
Si87xxC Devices
Average Output Current
Peak Output Current (VDD = 5 V)
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
Rev. 1.1
13
Si87xx
2. Functional Description
2.1. Theory of Operation
The Si87xx are pin-compatible, one-channel, drop-in replacements for popular optocouplers with data rates up to
15 Mbps. The operation of an Si87xx channel is analogous to that of an opto coupler, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for the Si87xx is shown in Figure 7.
Transmitter
Receiver
RF
OSCILLATOR
A
LED
Emulator
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
Figure 7. Simplified Channel Diagram
14
Rev. 1.1
Output Stage
Open Collector
B
Si87xx
3. Technical Description
3.1. Device Behavior
Truth tables for the Si87xx are summarized in Table 10.
Table 10. Si87xx Truth Table Summary1
Input
VDD
EN2
VO 3
OFF
> UVLO
H
HIGH
OFF
> UVLO
L
HIGH
OFF
< UVLO
H
HIGH
OFF
< UVLO
L
HIGH
ON
> UVLO
H
LOW
ON
> UVLO
L
HIGH
ON
< UVLO
H
HIGH
ON
< UVLO
L
HIGH
Notes:
1. This truth table assumes VDD is powered. UVLO is typically 2.8 V.
2. Si8712 only.
3. The output voltage level is determined by the external pull-up supply.
3.2. Device Startup
During start-up, Output VO floats and its voltage level is determined by the external pull-up until VDD rises above
the UVLO+ threshold for a minimum time period of tSTART. Following this, the output is low when the current flowing
from anode to cathode is > IF(ON). Device startup, normal operation, and shutdown behavior is shown in Figure 8.
UVLO+
VDDHYS
UVLO-
VDD
IF(ON)
IHYS
IF
tSTART
tPLH
tPHL
tSTART
Voltage level
determined by
external pull-up
supply
tPLH
VO
Figure 8. Si87xx Operating Behavior (IF > IF(MIN) when VF > VF(MIN))
Rev. 1.1
15
Si87xx
4. Applications
The following sections detail the input and output circuits necessary for proper operation of the Si87xx family.
4.1. Input Circuit Design
Opto coupler manufacturers typically recommend the circuits shown in Figures 9 and 10. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
Si87xx
Vdd
1 N/C
R1
2 ANODE
Control
Input
3 CATHODE
Open Drain or
Collector
4 N/C
Figure 9. Si87xx Input Circuit
Vdd
Si87xx
1 N/C
Control
Input
Q1
2 ANODE
3 CATHODE
R1
4 N/C
Figure 10. High CMR Si87xx Input Circuit
The optically-coupled circuit of Figure 9 turns the LED on when the control input is high. However, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 10 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing commonmode transient immunity.
Some opto coupler applications recommend reverse-biasing the LED when the control input is off to prevent
coupled noise from energizing the LED. The Si87xx input circuit requires less current and has twice the off-state
noise margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see
Figure 10) may require increasing the value of R1 to limit input current IF to its maximum rating when using the
Si87xx. In addition, there is no benefit in driving the Si87xx input diode into reverse bias when in the off state.
Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si87xx is no more than –0.3 V with respect to the cathode when reverse-biased.
16
Rev. 1.1
Si87xx
New designs should consider the input circuit configurations of Figure 11, which are more efficient than those of
Figures 9 and 10. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si87xx input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 11B). Additionally, note that the Si87xx propagation
delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX).
Control
Input
Si87xx
Si87xx
+5V
S1
R1
S2
1
N/C
2
ANODE
3
4
1
N/C
2
ANODE
CATHODE
3
CATHODE
N/C
4
N/C
MCU I/O
Port pin
R1
A
B
Figure 11. Si87xx Other Input Circuit Configurations
4.2. Output Circuit Design and Power Supply Connections
The speed of the open collector circuit is dependent upon the supply, VCC, the pullup resistor, RL, and the load
modeled by CL. Figure 12 illustrates three common circuit output configurations. For VDD = 5 V operation,
RL>350 is recommended to ensure proper VOL levels. For VDD = 30 V operation, RL > 2.1 kis recommended
to ensure proper VOL levels. If the enable pin is used (see Figure 12B) and two separate supplies power VDD and
the VO pullup resistor, the enable pin should be referenced to the VDD pin because VO cannot exceed VDD by more
than 0.5 V. Figure 12C illustrates a circuit using the internal 20 k resistor.
Note that GND can be biased at, above, or below ground as long as the voltage on VDD with respect to GND is a
maximum of 30 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The
optimum values for these capacitors depend on load current and the distance between the chip and its power
source. It is recommended that 0.1 and 1 µF bypass capacitors be used to reduce high-frequency noise and
maximize performance. Opto replacement applications should limit their supply voltages to 30 V or less.
Si87xx
Si87xx
VDD 8
VE 7
VCC 3-30 V
EN
VCC2 3-30 V
VDD 8
VE 7
RL
EN
VDD 8
VL
RL
7
VCC 3-30 V
RL
0.1, 1 µF
0.1, 1 µF
0.1, 1 µF
VO 6
VO 6
VO 6
CL
CL
CL
GND 5
A
Si87xx
VCC1 3-30 V
GND 5
GND 5
C
B
Figure 12. Si87xx Output Circuit Configurations
Rev. 1.1
17
Si87xx
5. Pin Descriptions (SOIC-8, DIP8, LGA8) Open Collector
Figure 13. Pin Configuration
Table 11. Pin Descriptions (SOIC-8, DIP8, LGA8) Open Collector
Pin
Name
1
NC*
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC*
No connect.
5
GND
External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6
VO
Output signal.
7
NC*
No connect.
8
VDD
Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
18
Rev. 1.1
Si87xx
6. Pin Descriptions (SOIC-8, DIP8, LGA8) Output Enable
Figure 14. Pin Configuration
Table 12. Pin Descriptions (SOIC-8, DIP8, LGA8) Output Enable
Pin
Name
1
NC*
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC*
No connect.
5
GND
External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6
VO
Output signal.
7
VE
Output enable. Tied to VDD to enable output.
8
VDD
Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Rev. 1.1
19
Si87xx
7. Pin Descriptions (SDIP6) Open Collector
Figure 15. Pin Configuration
Table 13. Pin Descriptions (SDIP6) Open Collector
Pin
Name
1
ANODE
2
NC*
3
Description
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
No connect.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
4
GND
5
VO
Output signal.
6
VDD
Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
20
Rev. 1.1
Si87xx
8. Pin Descriptions (SOIC-8, DIP8, LGA8) 20 k Pull-Up Resistor
Figure 16. Pin Configuration
Table 14. Pin Descriptions (SOIC-8, DIP8, LGA8) 20 k Pull-Up Resistor
Pin
Name
1
NC*
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC*
No connect.
5
GND
External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6
VO
Output signal.
7
VL
Output Pull-Up Load. Tie to VO to enable load.
8
VDD
Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Rev. 1.1
21
Si87xx
9. Ordering Guide
Table 15. Si87xx Ordering Guide1,2,3
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration
Data Rate
(Cross Reference)
Insulation
Rating
Temp Range
Pkg Type
Open Collector Output (Available in SOIC-8, DIP8, and SDIP6)
Si8710AC-B-IS
LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8710BC-B-IS
High CMTI LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8710CC-B-IS
LED input
Open collector output
1 Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8710AC-B-IP
LED input
Open collector output
15 Mbps
HCPL-4502
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8710BC-B-IP
High CMTI LED input
Open collector output
15 Mbps
HCPL-4502
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8710CC-B-IP
LED input
Open collector output
1 Mbps
HCPL-4502
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8710AD-B-IS
LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
5.0 kVrms
–40 to +125 °C
SDIP6
Si8710BD-B-IS
High CMTI LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
5.0 kVrms
–40 to +125 °C
SDIP6
Si8710CD-B-IS
LED input
Open collector output
1 Mbps
ACPL-W611,
PS9303L2
5.0 kVrms
–40 to +125 °C
SDIP6
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
22
Rev. 1.1
Si87xx
Table 15. Si87xx Ordering Guide1,2,3 (Continued)
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration
Data Rate
(Cross Reference)
Insulation
Rating
Temp Range
Pkg Type
Open Collector Output with 20 k Pullup Resistor (Available in SOIC-8, DIP8, and LGA8)
Si8711AC-B-IS
LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8711BC-B-IS
High CMTI LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8711CC-B-IS
LED input
Open collector output
with integrated pullup
1 Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8711AC-B-IP
LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8711BC-B-IP
High CMTI LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8711CC-B-IP
LED input
Open collector output
with integrated pullup
1 Mbps
HCPL-4506
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8711AD-B-IM
LED input
Open collector output
with integrated pullup
15 Mbps
HCNW-4506
5.0 kVrms
–40 to +125 °C
LGA8
Si8711BD-B-IM
High CMTI LED input
Open collector output
with integrated pullup
15 Mbps
HCNW-4506
5.0 kVrms
–40 to +125 °C
LGA8
Si8711CD-B-IM
LED input
Open collector output
with integrated pullup
1 Mbps
HCNW-4506
5.0 kVrms
–40 to +125 °C
LGA8
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Rev. 1.1
23
Si87xx
Table 15. Si87xx Ordering Guide1,2,3 (Continued)
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration
Data Rate
(Cross Reference)
Insulation
Rating
Temp Range
Pkg Type
Open Collector Output with Output Enable (Available in SOIC-8, DIP8, and LGA8)
Si8712AC-B-IS
LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8712BC-B-IS
High CMTI LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8712CC-B-IS
LED input
Open collector output
with enable
1 Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C
SOIC-8
Si8712AC-B-IP
LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8712BC-B-IP
High CMTI LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8712CC-B-IP
LED input
Open collector output
with enable
1 Mbps
HCPL-261x/260x
3.75 kVrms –40 to +125 °C
DIP8/GW
Si8712AD-B-IM
LED input
Open collector output
with enable
15 Mbps
HCNW-2611
5.0 kVrms
–40 to +125 °C
LGA8
Si8712BD-B-IM
High CMTI LED input
Open collector output
with enable
15 Mbps
HCNW-2611
5.0 kVrms
–40 to +125 °C
LGA8
Si8712CD-B-IM
LED input
Open collector output
with enable
1 Mbps
HCNW-2611
5.0 kVrms
–40 to +125 °C
LGA8
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
24
Rev. 1.1
Si87xx
10. Package Outline: 8-Pin Narrow Body SOIC
Figure 17 illustrates the package details for the Si87xx in an 8-pin narrow-body SOIC package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 17. 8-Pin Narrow Body SOIC Package
Table 16. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
0
8
Rev. 1.1
25
Si87xx
11. Land Pattern: 8-Pin Narrow Body SOIC
Figure 18 illustrates the recommended land pattern details for the Si87xx in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 18. 8-Pin Narrow Body SOIC Land Pattern
Table 17. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
26
Rev. 1.1
Si87xx
12. Package Outline: DIP8
Figure 19 illustrates the package details for the Si87xx in a DIP8 package. Table 18 lists the values for the
dimensions shown in the illustration.
Figure 19. DIP8 Package
Table 18. DIP8 Package Diagram Dimensions
Dimension
Min
Max
A
—
4.19
A1
0.55
0.75
A2
3.17
3.43
b
0.35
0.55
b2
1.14
1.78
b3
0.76
1.14
c
0.20
0.33
D
9.40
9.90
E
7.37
7.87
E1
6.10
6.60
E2
9.40
9.90
e
2.54 BSC.
L
0.38
0.89
aaa
—
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
27
Si87xx
13. Land Pattern: DIP8
Figure 20 illustrates the recommended land pattern details for the Si87xx in a DIP8 package. Table 19 lists the
values for the dimensions shown in the illustration.
Figure 20. DIP8 Land Pattern
Table 19. DIP8 Land Pattern Dimensions*
Dimension
Min
Max
C
8.85
8.90
E
2.54 BSC
X
0.60
0.65
Y
1.65
1.70
*Note: This Land Pattern Design is based on the IPC-7351 specification.
28
Rev. 1.1
Si87xx
14. Package Outline: SDIP6
Figure 21 illustrates the package details for the Si87xx in an SDIP6 package. Table 20 lists the values for the
dimensions shown in the illustration.
Figure 21. SDIP6 Package
Table 20. SDIP6 Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
4.58 BSC
E
11.50 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.1
29
Si87xx
Table 20. SDIP6 Package Diagram Dimensions (Continued)
Dimension
Min
Max
θ
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
30
Rev. 1.1
Si87xx
15. Land Pattern: SDIP6
Figure 22 illustrates the recommended land pattern details for the Si87xx in an SDIP6 package. Table 21 lists the
values for the dimensions shown in the illustration.
Figure 22. SDIP6 Land Pattern
Table 21. SDIP6 Land Pattern Dimensions*
Dimension
Min
Max
C
10.45
10.50
E
1.27 BSC
X
0.55
0.60
Y
2.00
2.05
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Rev. 1.1
31
Si87xx
16. Package Outline: LGA8
Figure 23 illustrates the package details for the Si87xx in an LGA8 package. Table 22 lists the values for the
dimensions shown in the illustration.
Figure 23. LGA8 Package
Table 22. Package Diagram Dimensions
Dimension
Min
Nom
Max
A
0.74
0.84
0.94
b
1.15
1.20
1.25
D
10.00 BSC.
e
2.54 BSC.
E
12.50 BSC.
L
1.05
1.10
1.15
L1
0.05
0.10
0.15
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.10
ddd
—
—
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
32
Rev. 1.1
Si87xx
17. Land Pattern: LGA8
Figure 24 illustrates the recommended land pattern details for the Si87xx in an LGA8 package. Table 23 lists the
values for the dimensions shown in the illustration.
Figure 24. LGA8 Land Pattern
Table 23. LGA8 Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
11.80
E
Pad Row Pitch
2.54
X1
Pad Width
1.30
Y1
Pad Length
1.80
Notes:
1. This Land Pattern Design is based on IPC-7351 specifications.
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.1
33
Si87xx
18. Top Markings
18.1. Top Marking (8-Pin Narrow Body SOIC)
18.2. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking:
Customer Part Number
Si871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
Circle = 43 mils Diameter
Left-Justified
“e4” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
34
Rev. 1.1
Si87xx
18.3. Top Marking (DIP8)
18.4. Top Marking Explanation (DIP8)
Line 1 Marking:
Customer Part Number
Si871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Circle = 51 mils Diameter
Center-Justified
“e4” Pb-Free Symbol
Country of Origin
(Iso-Code Abbreviation)
CC
Line 3 Marking:
Rev. 1.1
35
Si87xx
18.5. Top Marking (SDIP6)
18.6. Top Marking Explanation (SDIP6)
Line 1 Marking:
Device
871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
Line 4 Marking:
Country of Origin
(Iso-Code Abbreviation)
CC
36
Rev. 1.1
Si87xx
18.7. Top Marking (LGA8)
18.8. Top Marking Explanation (LGA8)
Line 1 Marking:
Device Part Number
Si871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal
pull-up
2 = open collector output w/ output
enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House.
Corresponds to the year and work week of the
assembly release.
RTTTTT = Mfg Code
Manufacturing Code from the Assembly
Purchase Order form. “R” indicates revision.
Circle = 1.6 mm Diameter
Center-Justified
"e4" Pb-Free Symbol
Country of Origin
ISO Code Abbreviation
CC
Circle = 0.75 mm Diameter
Lower Left-Justified
Pin 1 Identifier
Line 3 Marking:
Line 4 Marking:
Rev. 1.1
37
Si87xx
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
Updated various specs in Table 2 on page 4.
Added Figure 1 on page 6.
Added Figure 2 on page 7.
Added Figure 8 on page 15.
Updated various specs in Table 10 on page 16.
Removed “pending” throughout.
Added references to “CQC” throughout.
Added references to “AEC-Q100 qualified” throughout.
Updated all Top Marking figures and descriptions.
Revision 1.0 to Revision 1.1
Updated Figure 1 on page 6.
Updated Ordering Guide Table 15 on page 22.
Removed
references to moisture sensitivity levels from
table note.
38
Rev. 1.1
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
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