S i 8 7 1 x/2x
5 K V L E D E MU LAT OR I NPUT , L O G I C O UTPUT I SOLATORS
Features
High Speed: dc to 15 Mbps
2.5 to 5.5 V logic output
Pin-compatible, drop-in upgrades for
popular high-speed digital
optocouplers
Performance and reliability
advantages vs. optocouplers
Resistant to temperature, age and
forward current effects
10x lower FIT rate for longer
service life
Higher common-mode transient
immunity: >50 kV/µs typical
Lower power and forward input
diode current
Wide range of product options
Inverting and non-inverting
Disable output high, low or tri-state
1 channel diode emulator input
Propagation delay 30 ns
Up to 5000 VRMS isolation
10 kV surge withstand capability
AEC-Q100 qualified
Wide operating temperature range
– 40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
Industrial automation
Isolated data acquisition
Motor controls and drives
Test and measurement equipment
Isolated switch mode power supplies
Safety Regulatory Approvals (Pending)
Up
to 5000 Vrms for 1 minute
CSA component notice 5A
approval
IEC
60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC60747-5-2/VDE0884-10
(basic/reinforced insulation)
8
VDD
7
NC
UVLO
ANODE
2
e
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8
Industry Standard Pinout
1
8
VDD
ANODE
2
7
EN
e
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8 with Output Enable
Industry Standard Pinout
CQC certification approval
GB4943.1
ANODE 1
NC 2
Description
The Si871x/2x isolators are pin-compatible, single-channel, drop-in
replacements for popular optocouplers with data rates up to 15 Mbps.
These devices isolate high-speed digital signals and offer performance,
reliability, and flexibility advantages not available with optocoupler
solutions. The Si871x/2x series is based on Silicon Labs' proprietary
CMOS isolation technology for low-power and high-speed operation and
are resistant to the wear-out effects found in optocouplers that degrade
performance with increasing temperature, forward current, and device
age. As a result, the Si871x/2x series offer longer service life and
dramatically higher reliability compared to optocouplers. Ordering options
include logic output with and without output enable options.
Rev. 1.0 8/14
1
UVLO
UL 1577 recognized
NC
NC
Applications
Pin Assignments:
See page 21
Copyright © 2014 by Silicon Laboratories
6
VDD
5
VO
4
GND
UVLO
e
CATHODE 3
SDIP6
Industry Standard Pinout
Patent pending
Si871x/2x
Si871x/2x
Functional Block Diagram
VDD
Diode
Emulator
A1
REC
XMIT
IF
Output
Stage
OUT
(Logic Out)
C1
GND
2
Rev. 1.0
Si871x/2x
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2. Output Circuit Design and Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . 18
5. Pin Descriptions (SOIC-8, DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Pin Descriptions (SOIC-8, DIP8) with Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.1. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.2. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 31
15.3. Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
15.4. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.5. Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.6. Top Marking Explanation (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Rev. 1.0
3
Si871x/2x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VDD
2.5
—
5.5
V
IF(ON)
(See Figure 1)
6
—
30
mA
TA
–40
—
125
°C
VDD Supply Voltage
Input Current
Operating Temperature (Ambient)
Table 2. Electrical Characteristics
VDD = 5 V; GND = 0 V; TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Parameters
Supply Voltage
VDD
(VDD–GND)
2.5
—
5.5
V
Supply Current
IDD
Output high or low
(VDD = 2.5 to 5.5 V)
—
1.5
—
mA
Input Current Threshold
IF(TH)
—
—
3.6
mA
Input Current
Hysteresis
IHYS
—
0.34
—
mA
Input Forward Voltage
(OFF)
VF(OFF) Measured at ANODE with respect to
CATHODE.
—
—
1
V
Input Forward Voltage
(ON)
VF(ON)
1.4
—
2.8
V
Measured at ANODE with respect to
CATHODE.
Input Capacitance
CI
f = 100 kHz,
VF = 0 V,
VF = 2 V
—
—
15
15
—
—
pF
pF
Logic Low Output
Voltage
VOL
IOL = 4 mA
—
0.2
0.4
V
Logic High Output
Voltage
VOH
IOH = –4 mA
VDD - 0.4
VDD 0.2
—
V
Output Impedance
ZO
—
50
—
Enable High Min
VEH
VDD - 0.4
—
—
V
Enable Low Max
VEL
—
—
0.4
V
Enable High Current
Draw
IEH
VDD = VEH = 5 V
—
0
—
µA
Enable Low Current
Draw
IEL
VDD =5 V, VEL = 0 V
—
–30
0
µA
UVLO Threshold +
VDDUV+
See Figure 8 on page 16.
VDD rising
—
2.2
2.35
V
UVLO Threshold –
VDDUV–
See Figure 8 on page 16.
VDD falling
—
2
2.25
V
UVLO lockout
hysteresis
VDDHYS
50
100
—
mV
4
Rev. 1.0
Si871x/2x
Table 2. Electrical Characteristics (Continued)
VDD = 5 V; GND = 0 V; TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC
—
15
MBPS
AC Switching Parameters (VDD =5 V, CL = 15 pF)
Maximum Data Rate
FDATA
Minimum Pulse Width
MPW
66
—
—
ns
Propagation Delay
(Low-to-High)
tPLH
CL = 15 pF
5
—
50
ns
Propagation Delay
(High-to-Low)
tPHL
CL = 15 pF
5
—
50
ns
Pulse Width Distortion
PWD
| tPLH – tPHL |
—
—
25
ns
—
—
25
ns
Propagation Delay
Skew
tPSK(p-p) tPSK(P-P) is the magnitude of the difference in prop delays between different units operating at same supply
voltage, load, and ambient temp.
Rise Time*
tR
CL = 15 pF
—
2.5
4
ns
Fall Time*
tF
CL = 15 pF
—
2.5
4
ns
—
—
40
µs
35
50
—
kV/µs
Device Startup Time
tSTART
Common Mode
Transient Immunity
CMTI
Output = low or high
VCM =1500 V (See Figure 2)
IF = 6 mA
*Note: Guaranteed by design and/or characterization
Rev. 1.0
5
Si871x/2x
10
Anode
Anode
ESD
e
2.2 V
700
Cathode
Cathode
AnodetoCathodeVoltage[V]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
DiodeEmulatorInputCurrent[mA]
Figure 1. Diode Emulator Model and I-V Curve
6
Rev. 1.0
30
Si871x/2x
Input Signal
Switch
267
Si871x/2x
Anode
5V
Isolated
Supply
Isolated
Ground
5V
Supply
VDD
VO
Cathode
Oscilloscope
GND
Input
High Voltage
Differential
Probe
Output
Vcm Surge
Output
High Voltage
Surge Generator
Figure 2. Common Mode Transient Immunity Characterization Circuit
Rev. 1.0
7
Si871x/2x
Table 3. Regulatory Information*
CSA
The Si871x/2x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working
voltage.
60601-1: Up to 250 VRMS reinforced insulation working voltage; up to 500 VRMS basic insulation working voltage.
VDE
The Si871x/2x is certified according to IEC60747 and VDE0884. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1414 Vpeak for basic insulation working voltage.
VDE0884-10: Up to 1414 Vpeak for reinforced insulation working voltage.
UL
The Si871x/2x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si871x/2x is certified under GB4943.1-2011. For more details, see File V2012CQC001041.
Rated up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "8.Ordering Guide" on page 22.
Table 4. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
SOIC-8
DIP8
SDIP6
Unit
Nominal Air Gap (Clearance)
L(IO1)
4.7 min
7.2 min
9.6 min
mm
Nominal External Tracking
(Creepage)
L(IO2)
3.9 min
7.0 min
8.3 min
mm
0.016
0.016
0.016
mm
600
600
600
V
0.031
0.031
0.057
mm
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
Resistance (Input-Output)*
RIO
Capacitance (Input-Output)*
CIO
IEC60112
10
f = 1 MHz
12
1
10
12
1
10
12
1
pF
*Note: To determine resistance and capacitance, the Si871x/2x is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6)
are shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
8
Rev. 1.0
Si871x/2x
Table 5. IEC 60664-1 (VDE 0884) Ratings
Parameter
Test Condition
Specification
SOIC-8
DIP8
SDIP6
I
I
I
Basic Isolation Group
Material Group
Installation
Classification
Rated Mains Voltages <
150 VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages <
300 VRMS
I-IV
I-IV
I-IV
Rated Mains Voltages <
450 VRMS
I-III
I-III
I-IV
Rated Mains Voltages <
600 VRMS
I-III
I-III
I-IV
Rated Mains Voltages <
1000 VRMS
I-II
I-II
I-III
Table 6. IEC 60747-5-2 (VDE 0884-10) Insulation Characteristics*
Parameter
Maximum Working
Insulation Voltage
Input to Output Test
Voltage
Transient Overvoltage
Symbol
Test Condition
Unit
SOIC-8
DIP8
SDIP6
630
891
1140
V peak
1181
1671
2138
V peak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
VIOTM
t = 60 sec
6000
6000
8000
V peak
2
2
2
>109
>109
>109
VIORM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at
TS, VIO = 500 V
Characteristic
RS
*Note: This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety
data is ensured by protective circuits. The Si871x/2x provides a climate classification of 40/125/21.
Rev. 1.0
9
Si871x/2x
Table 7. IEC Safety Limiting Values
Parameter
Symbol
Case Temperature
TS
Input Current
IS
Output Power
PS
Test Condition
JA = 110 °C/W (SOIC-8),
110 °C/W (DIP8),
105 °C/W (SDIP6),
VF =2.8 V, TJ = 140 °C,
TA = 25 °C
Max
DIP8
SDIP6
140
140
140
°C
370
370
390
mA
1
1
1
W
Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3, 4,and 5.
10
Rev. 1.0
Unit
SOIC-8
Si871x/2x
Table 8. Thermal Characteristics
Parameter
Symbol
OutputPo
owerͲ Ps,InputCurrentͲ Is
IC Junction-to-Air Thermal
Resistance
Typ
SOIC-8
DIP8
SDIP6
110
110
105
JA
Unit
ºC/W
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
OutputPo
owerͲ Ps,InputCurrentͲ Is
Figure 3. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884-10
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
Figure 4. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884-10
Rev. 1.0
11
OutputPo
owerͲ Ps,InputCurrentͲ Is
Si871x/2x
1200
1000
Ps(mW)
800
600
Is(mA)
400
200
0
0
20
40
60
80
100
120
140
TsͲ CaseTemperature(°C)
Figure 5. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2 and VDE0884-10
12
Rev. 1.0
Si871x/2x
Table 9. Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Unit
TSTG
–65
+150
°C
Operating Temperature
TA
–40
+125
°C
Junction Temperature
TJ
—
+140
°C
IF(AVG)
—
30
mA
Peak Transient Input Current
(< 1 µs pulse width, 300 pps)
IFTR
—
1
A
Reverse Input Voltage
VR
—
0.3
V
Supply Voltage
VDD
–0.5
7
V
Output Voltage
VOUT
–0.5
VDD+0.5
V
Enable Voltage
VEOUT
–0.5
VDD+0.5
V
Output Source or Sink Current
IO
—
22
mA
Input Power Dissipation
PI
—
90
mW
Output Power Dissipation
PO
—
163
mW
Total Power Dissipation
PT
—
253
mW
Lead Solder Temperature (10 s)
—
260
°C
HBM Rating ESD
3
—
kV
250
—
V
CDM
2
—
kV
Maximum Isolation Voltage (1 s) SOIC-8
—
4500
VRMS
Maximum Isolation Voltage (1 s) DIP8
—
4500
VRMS
Maximum Isolation Voltage (1 s) SDIP6
—
6500
VRMS
Storage Temperature
Average Forward Input Current
Machine Model ESD
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
Rev. 1.0
13
Si871x/2x
2. Application Information
2.1. Theory of Operation
The Si871x/2x are pin-compatible, single-channel, drop-in replacements for popular optocouplers with data rates
up to 15 Mbps. The operation of an Si871x/2x channel is analogous to that of an opto coupler, except an RF carrier
is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for the Si871x/2x is shown in Figure 6.
Transmitter
Receiver
RF
OSCILLATOR
A
LED
Emulator
MODULATOR
VDD
SemiconductorBased Isolation
Barrier
DEMODULATOR
~50
Gnd
Figure 6. Simplified Channel Diagram
14
Rev. 1.0
B
Si871x/2x
3. Technical Description
3.1. Device Behavior
Truth tables for the Si871x/2x are summarized in Table 10.
Table 10. Si871x/2x Truth Table Summary*
Input
Enable
Output
Si8715 (Non-inverting)
OFF
N/A
LOW
ON
N/A
HIGH
Si8716 (Inverting)
OFF
HIGH
HIGH
ON
HIGH
LOW
X
LOW
HIGH
Si8717 (Non-inverting)
OFF
HIGH
LOW
ON
HIGH
HIGH
X
LOW
HI-Z
Si8718 (Inverting)
OFF
HIGH
HIGH
ON
HIGH
LOW
X
LOW
HI-Z
Si8719 (Inverting)
OFF
N/A
HIGH
ON
N/A
LOW
Si8720 (Inverting)
OFF
HIGH
HIGH
ON
HIGH
LOW
X
LOW
LOW
*Note: This truth table assumes VDD is powered (VDD> UVLO). If VDD is below UVLO, see
"3.3.Under Voltage Lockout (UVLO)" on page 16 for more information. When VDD <
UVLO, the output state is not guaranteed. In this condition, the output level is determined
by external circuity connected to the output.
Rev. 1.0
15
Si871x/2x
3.2. Device Startup
During startup-up, for the Si8716, Output VO is high until VDD rises above the UVLO+ threshold for a minimum time
period of tSTART. Following this, the output is low when the current flowing from anode to cathode is > IF(ON). Device
startup, normal operation, and shutdown behavior for the Si8716 is shown in Figure 7. Note that Figure 7 assumes
that Enable is asserted and that the outputs are operating in their normal operating condition (inverting for the
Si8716). See Table 10 for more details on the Enable function.
UVLO+
VDDHYS
UVLO-
VDD
IF(ON)
IHYS
IF
tSTART
tPLH
tPHL
Voltage level
determined by
external pull-up
supply
tSTART
tPLH
VO
Figure 7. Si8716 Operating Behavior (IF > IF(MIN) when VF > VF(MIN))
3.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO to its default state when VDD is below the lockout threshold. Referring
to Figure 8, upon power up, the Si871x/2x is maintained in UVLO until VDD rises above VDDUV+. During power
down, the Si871x/2x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+
– VDDHYS).
Output Voltage (VO)
VDDUV+ (Typ)
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
Supply Voltage (VDD - GND) (V)
Figure 8. Si871x/2x UVLO Response
16
Rev. 1.0
2.5
Si871x/2x
4. Applications
The following sections detail the input and output circuits necessary for proper operation of the Si871x/2x family.
4.1. Input Circuit Design
Opto coupler manufacturers typically recommend the circuits shown in Figures 9 and 10. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
Si871x/2x
Vdd
1 N/C
R1
2 ANODE
Control
Input
3 CATHODE
Open Drain or
Collector
4 N/C
Figure 9. Si871x/2x Input Circuit
Vdd
Si871x/2x
1 N/C
Control
Input
Q1
2 ANODE
3 CATHODE
R1
4 N/C
Figure 10. High CMR Si871x/2x Input Circuit
The optically-coupled circuit of Figure 9 turns the LED on when the control input is high. However, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 10 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing commonmode transient immunity.
Some opto coupler applications recommend reverse-biasing the LED when the control input is off to prevent
coupled noise from energizing the LED. The Si871x/2x input circuit requires less current and has twice the off-state
noise margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see
Figure 10) may require increasing the value of R1 to limit input current IF to its maximum rating when using the
Si871x/2x. In addition, there is no benefit in driving the Si871x/2x input diode into reverse bias when in the off state.
Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si871x/2x is no more than –0.3 V with respect to the cathode when reverse-biased.
Rev. 1.0
17
Si871x/2x
New designs should consider the input circuit configurations of Figure 11, which are more efficient than those of
Figures 9 and 10. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si871x/2x input can be driven from the I/O port of any
MCU or FPGA capable of sourcing a minimum of 6 mA (see Figure 11B). Additionally, note that the Si871x/2x
propagation delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX).
Control
Input
Si871x/2x
Si871x/2x
+5V
S1
R1
S2
1
N/C
2
ANODE
3
4
1
N/C
2
ANODE
CATHODE
3
CATHODE
N/C
4
N/C
MCU I/O
Port pin
R1
A
B
Figure 11. Si871x/2x Other Input Circuit Configurations
4.2. Output Circuit Design and Power Supply Connections
GND can be biased at, above, or below ground as long as the voltage on VDD with respect to GND is a maximum
of 5.5 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The optimum
values for these capacitors depend on load current and the distance between the chip and its power source. It is
recommended that 0.1 and 1 µF bypass capacitors be used to reduce high-frequency noise and maximize
performance. Opto replacement applications should limit their supply voltages to 5.5 V or less.
18
Rev. 1.0
Si871x/2x
5. Pin Descriptions (SOIC-8, DIP8)
NC
1
8
VDD
7
NC
UVLO
ANODE
2
e
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8
Industry Standard Pinout
Figure 12. Pin Configuration
Table 11. Pin Descriptions (SOIC-8, DIP8)
Pin
Name
1
NC*
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC*
No connect.
5
GND
Ground reference for VDD. This terminal is typically connected to ground but may be tied to a
negative or positive voltage.
6
VO
Output signal.
7
NC*
No connect.
8
VDD
Output-side power supply input referenced to GND (5.5 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Rev. 1.0
19
Si871x/2x
6. Pin Descriptions (SOIC-8, DIP8) with Output Enable
NC
1
8
VDD
7
EN
UVLO
ANODE
2
e
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8 with Output Enable
Industry Standard Pinout
Figure 13. Pin Configuration
Table 12. Pin Descriptions (SOIC-8, DIP8) with Output Enable
Pin
Name
1
NC*
2
ANODE
3
Description
No connect.
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4
NC*
No connect.
5
GND
Ground reference for VDD. This terminal is typically connected to ground but may be tied to a
negative or positive voltage.
6
VO
Output signal.
7
EN
Output enable. Tied to VDD to enable output.
8
VDD
Output-side power supply input referenced to GND (5.5 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
20
Rev. 1.0
Si871x/2x
7. Pin Descriptions (SDIP6)
ANODE 1
NC 2
6
VDD
5
VO
4
GND
UVLO
e
CATHODE 3
SDIP6
Industry Standard Pinout
Figure 14. Pin Configuration
Table 13. Pin Descriptions (SDIP6)
Pin
Name
1
ANODE
2
NC*
3
Description
Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
No connect.
CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
Ground reference for VDD. This terminal is typically connected to ground but may be tied to a
negative or positive voltage.
4
GND
5
VO
Output signal.
6
VDD
Output-side power supply input referenced to GND (5.5 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Rev. 1.0
21
Si871x/2x
8. Ordering Guide
Table 14. Si871x/2x Ordering Guide1,2,3
Ordering Part
Number (OPN)
Ordering Options
Input/Output
Configuration
Data Rate
Cross Reference
Insulation
Rating
Enable Pin/
Output State
when Active
Pkg Type
Logic Output (Available in SOIC-8, DIP8, and SDIP6)
Si8715BC-A-IS
High CMTI
Non-inverting Output
15 Mbps
3.75 kVrms
No, N/A
SOIC-8
Si8716BC-A-IS
High CMTI
Inverting Output
15 Mbps
ACPL-061L, HCPL-0600,
HCPL-0601, HCPL-0611
3.75 kVrms
Yes, High
SOIC-8
Si8717BC-A-IS
High CMTI
Non-inverting Output
15 Mbps
3.75 kVrms
Yes, Hi-z
SOIC-8
Si8718BC-A-IS
High CMTI
Inverting Output
15 Mbps
ACPL-C61L,
ACPL-W70L
3.75 kVrms
Yes, Hi-z
SOIC-8
Si8719BC-A-IS
High CMTI
Inverting Output
15 Mbps
3.75 kVrms
No, N/A
SOIC-8
Si8720BC-A-IS
High CMTI
Inverting Output
15 Mbps
3.75 kVrms
Yes, Low
SOIC-8
Si8715BC-A-IP
High CMTI
Non-inverting Output
15 Mbps
ACPL-4800,
HCPL-2202,
HCPL-2212
3.75 kVrms
No, N/A
DIP8/GW
Si8716BC-A-IP
High CMTI
Inverting Output
15 Mbps
6N137, HCPL-2601,
HCPL-2611
3.75 kVrms
Yes, High
DIP8/GW
Si8717BC-A-IP
High CMTI
Non-inverting Output
15 Mbps
3.75 kVrms
Yes, Hi-z
DIP8/GW
Si8718BC-A-IP
High CMTI
Inverting Output
15 Mbps
3.75 kVrms
Yes, Hi-z
DIP8/GW
Si8719BC-A-IP
High CMTI
Inverting Output
15 Mbps
3.75 kVrms
No, N/A
DIP8/GW
Si8720BC-A-IP
High CMTI
Inverting Output
15 Mbps
3.75 kVrms
Yes, Low
DIP8/GW
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
22
Rev. 1.0
Si871x/2x
Table 14. Si871x/2x Ordering Guide1,2,3 (Continued)
Ordering Part
Number (OPN)
Ordering Options
Input/Output
Configuration
Data Rate
Cross Reference
Insulation
Rating
Enable Pin/
Output State
when Active
Pkg Type
Si8715BD-A-IS
High CMTI
Non-inverting Output
15 Mbps
ACPL-W21L, PS9303L2
5.0 kVrms
No, N/A
SDIP6
Si8719BD-A-IS
High CMTI
Inverting Output
15 Mbps
ACPL-W61L,
ACPL-W481,
ACPL-W70L, TLP2766F
5.0 kVrms
No, N/A
SDIP6
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Rev. 1.0
23
Si871x/2x
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 15 illustrates the package details for the Si871x/2x in an 8-pin narrow-body SOIC package. Table 15 lists
the values for the dimensions shown in the illustration.
Figure 15. 8-Pin Narrow Body SOIC Package
Table 15. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol
Millimeters
Min
Max
A
1.35
1.75
A1
0.10
0.25
A2
1.40 REF
1.55 REF
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
24
1.27 BSC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
0
8
Rev. 1.0
Si871x/2x
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 16 illustrates the recommended land pattern details for the Si871x/2x in an 8-pin narrow-body SOIC.
Table 16 lists the values for the dimensions shown in the illustration.
Figure 16. 8-Pin Narrow Body SOIC Land Pattern
Table 16. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.0
25
Si871x/2x
11. Package Outline: DIP8
Figure 17 illustrates the package details for the Si871x/2x in a DIP8 package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 17. DIP8 Package
Table 17. DIP8 Package Diagram Dimensions
Dimension
Min
Max
A
—
4.19
A1
0.55
0.75
A2
3.17
3.43
b
0.35
0.55
b2
1.14
1.78
b3
0.76
1.14
c
0.20
0.33
D
9.40
9.90
E
7.37
7.87
E1
6.10
6.60
E2
9.40
9.90
e
2.54 BSC.
L
0.38
0.89
aaa
—
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
26
Rev. 1.0
Si871x/2x
12. Land Pattern: DIP8
Figure 18 illustrates the recommended land pattern details for the Si871x/2x in a DIP8 package. Table 18 lists the
values for the dimensions shown in the illustration.
Figure 18. DIP8 Land Pattern
Table 18. DIP8 Land Pattern Dimensions*
Dimension
Min
Max
C
8.85
8.90
E
2.54 BSC
X
0.60
0.65
Y
1.65
1.70
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Rev. 1.0
27
Si871x/2x
13. Package Outline: SDIP6
Figure 19 illustrates the package details for the Si871x/2x in an SDIP6 package. Table 19 lists the values for the
dimensions shown in the illustration.
Figure 19. SDIP6 Package
Table 19. SDIP6 Package Diagram Dimensions
Dimension
Min
Max
A
—
2.65
A1
0.10
0.30
A2
2.05
—
b
0.31
0.51
c
0.20
0.33
D
4.58 BSC
E
11.50 BSC
E1
7.50 BSC
e
1.27 BSC
L
0.40
1.27
h
0.25
0.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
28
Rev. 1.0
Si871x/2x
Table 19. SDIP6 Package Diagram Dimensions (Continued)
Dimension
Min
Max
θ
0°
8°
aaa
—
0.10
bbb
—
0.33
ccc
—
0.10
ddd
—
0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
29
Si871x/2x
14. Land Pattern: SDIP6
Figure 20 illustrates the recommended land pattern details for the Si871x/2x in an SDIP6 package. Table 20 lists
the values for the dimensions shown in the illustration.
Figure 20. SDIP6 Land Pattern
Table 20. SDIP6 Land Pattern Dimensions*
Dimension
Min
Max
C
10.45
10.50
E
1.27 BSC
X
0.55
0.60
Y
2.00
2.05
*Note: This Land Pattern Design is based on the IPC-7351 specification.
30
Rev. 1.0
Si871x/2x
15. Top Markings
15.1. Top Marking (8-Pin Narrow Body SOIC)
15.2. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking:
Customer Part Number
Si87 = Base name of product series
W = Isolator product series (1 or 2)
X = Output configuration
5/9 = no enable
6 = enable, output high when active
7/8 = enable, output Hi-z when active
0 = enable, output low when active
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
Circle = 43 mils Diameter
Left-Justified
“e4” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
Rev. 1.0
31
Si871x/2x
15.3. Top Marking (DIP8)
15.4. Top Marking Explanation (DIP8)
Line 1 Marking:
Customer Part Number
Si87 = Base name of product series
W = Isolator product series (1 or 2)
X = Output configuration
5/9 = no enable
6 = enable, output high when active
7/8 = enable, output Hi-z when active
0 = enable, output low when active
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Circle = 51 mils Diameter
Center-Justified
“e4” Pb-Free Symbol
Country of Origin
(Iso-Code Abbreviation)
CC
Line 3 Marking:
32
Rev. 1.0
Si871x/2x
15.5. Top Marking (SDIP6)
15.6. Top Marking Explanation (SDIP6)
Line 1 Marking:
Device
87 = Base name of product series
W = Isolator product series (1 or 2)
X = Output configuration
5/9 = no enable
6 = enable, output high when active
7/8 = enable, output Hi-z when active
0 = enable, output low when active
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
RTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
Line 4 Marking:
Country of Origin
(Iso-Code Abbreviation)
CC
Rev. 1.0
33
Si871x/2x
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
Updated Table 2 on page 4.
Updated Table 5 on page 9.
Updated Table 6 on page 9.
Updated Table 9 on page 13.
Updated Figure 8 on page 16.
34
Rev. 1.0
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