SL2309ZI-1T

SL2309 Not Recommended for New Designs Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features 10 to 140 MHz operating frequency range Low output clock jitter:  140 ps-max cycle-to-cycle jitter Low output-to-output skew: 150 ps-max Low product-to-product skew: 400 ps-max 3.3 V power supply range Low power dissipation:  26 mA-max at 66 MHz  44 mA –max at 133 MHz One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. N ot fo R r N ec o ew m m D e es nd ig e ns d   Description           The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL2309 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tristated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Fanout Buffer (NZDB). The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. Applications       Benefits Printers and MFPs Digital Copiers PCs and Work Stations DTV Routers, Switchers and Servers Digital Embeded Systems     Up to nine (9) distribution of input clock Standard and High-Drive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Low Power and Low Jitter PLL MUX CLKOUT CLKIN CLKA1 CLKA2 CLKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 2.0, May 12, 2008 400 West Cesar Chavez, Austin, TX 78701 Page 1 of 12 1 (512) 416-8500 1 (512) 416-9669 www.silabs.com SL2309 Pin Configuration 1 16 CLKOUT CLKA1 N ot fo R r N ec o ew m m D e es nd ig e ns d CLKIN 2 15 CLKA2 3 14 CLKA4 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB2 7 10 CLKB4 CLKB3 S2 8 9 S1 16-Pin SOIC and TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 4 VDD Power 3.3V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250kΩ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250kΩ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 12 GND Power Power Ground. 13 VDD Power 3.3V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 16 CLKOUT Output Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ). Rev 2.0, May 12, 2008 Reference Frequency Clock Input. Weak pull-down (250kΩ). Page 2 of 12 SL2309 General Description Select Input Control (S2, S1) The SL2309 is a low skew, low jitter Zero Delay Buffer with very low operating current. The SL2309 provides two (2) input select control pins called S1 (Pin-9) and S2 (Pin-8). This feature enables users to select various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. N ot fo R r N ec o ew m m D e es nd ig e ns d The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. In addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and Output Frequency Range The input and output frequency range is the same. But, it depends on the drive and output load (CL) levels as given in the below Table 1. Drive CL(pF) Min(MHz) Max(MHz) HIGH 15 10 140 HIGH 30 10 100 LOW 15 10 100 LOW 30 10 66 Table 1. Input/Output Frequency Range If the input clock is DC (GND to VDD) or floating, this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12μA-max supply current. In PLL by-pass mode (S2=1 and S1=0), the detection circuit is disabled and input frequency range is 10 to 100MHz for standard (-1) drive and 10 to 140MHz for high (-1H) drive. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL2309 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Rev 2.0, May 12, 2008 The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak pull-up resistors to VDD. PLL Bypass Mode If the S1 and S2 pins are logic Low(0) and High(1) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks; bank A, bank B and CLKOUT clocks are driven by directly from the reference input clock. In this operation mode SL2309 works like a non-ZDB fanout buffer. In this operation mode the input power-down detection circuit is disabled and outputs follow the input clock from DC to rated frequencies based on drive levels and load specifications. High and Low-Drive Product Options The SL2309 is offered with High Drive “-1H” and Standard Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI. Refer to the switching electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve the output-to-output skew and input-to-output specifications given in the switching electrical tables. However, Zero Delay between input and outputs can be adjusted by changing the loading at CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL2309 is designed to operate at VDD=3.3V (+/10%). An internal on-chip voltage regulator is used to provide PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. SL23EP09 Refer to SL23EP09 for extended frequency operation from 10 to 220MHz and 2.5V to 3.3V power supply operation range. Page 3 of 12 SL2309 S1 Clock A1-A4 Clock B1-4 CLKOUT Output Source PLL Status 0 0 Tri-state Tri-state Driven PLL On 0 1 Driven Tri-state Driven PLL On 1 0 Driven Driven Driven Reference Off 1 1 Driven Driven Driven PLL On N ot fo R r N ec o ew m m D e es nd ig e ns d S2 Table 2. Select Input Decoding CLKIN Input to CLKA or CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load – CLKA or CLKB Load (pF) Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 2.0, May 12, 2008 Page 4 of 12 SL2309 Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C – 260 °C N ot fo R r N ec o ew m m D e es nd ig e ns d Ambient Operating Temperature Soldering Temperature ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Latch-up 125°C -200 200 mA Operating Conditions: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition VDD 3.3V Supply Voltage 3.3V+/-10% TA Operating Temperature(Ambient) Commercial Industrial CLOAD Load Capacitance 10 to 140 MHz, -1H high drive All active PLL modes 10 to 100 MHz, -1H high drive All active PLL modes 10 to 100MHz, -1 standard drive All active PLL modes 10 to 66MHz, -1 standard drive All active PLL modes Min Max Unit 3.0 3.6 V 0 70 °C – 40 85 °C – 15 pF – 30 pF – 15 pF – 30 pF CIN Input Capacitance S1, S2 and CLKIN pins tpu Power-up Time Power-up time for all VDDs to reach minimum VDD voltage (VDD=3.0V). CLBW Closed-loop bandwidth 3.3V, (typical) 1.2 MHz ZOUT Output Impedance 3.3V, (typical), -1H high drive 22 Ω 3.3V, (typical), -1 standard drive 32 Ω Rev 2.0, May 12, 2008 – 7 pF 0.05 100 ms Page 5 of 12 SL2309 DC Electrical Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol Description Condition Min Max Unit 3.0 3.6 V Supply Voltage VIL Input LOW Voltage CLKIN, S2 and S1 Pins – 0.8 V VIH Input HIGH Voltage CLKIN, S2 and S1 pins 2.0 VDD+0.3 V IIL Input LOW Current CLKIN, S2 and S1 Pins, 0 < VIN < 0.8V – 25 µA IIH Input HIGH Current CLKIN, S2 and S1 Pins, VIN = VDD – 50 µA VOL Output LOW Voltage (All outputs) IOL = 8 mA (standard drive) – 0.4 V IOL = 12 mA (high drive) – 0.4 V VOH Output HIGH Voltage (All outputs) IOH = –8 mA (standard drive) 2.4 – V IOH = –12 mA (high drive) 2.4 – V 12 µA 25 µA – 14 mA – 26 mA – 36 mA – 44 mA 175 325 kΩ N ot fo R r N ec o ew m m D e es nd ig e ns d VDD IDDPD IDD1 IDD2 IDD3 IDD4 RPU/D Power Down Supply Current C-Grade CLKIN=0 to VDD or floating (input will be pulled-down by 250kΩ I-Grade weak pull-down on-chip resistor) All Outputs CL=0, 33MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 66MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 100MHz CLKIN Power Supply Current S2=S1=1 (High) All Outputs CL=0, 133MHz CLKIN Power Supply Current S2=S1=1 (High) Pins-1/2/3/6/7/8/9/10/11/14/15/16 Pull-up and Pull-down Resistors 250kΩ-typ – – Switching Specifications: Unless otherwise stated VDD=3.3V+/-10% and both C and I Grades Symbol FMAX1 FMAX2 INDC Description Maximum Frequency [1] (Input=Output ) All Active PLL Modes Maximum Frequency [1] (Input=Output ) PLL Bypass Mode (S2=1 and S1=0) Input Duty Cycle Condition Min Typ Max Unit High drive (-1H). All outputs CL=15pF 10 – 140 MHz High drive (-1H), All outputs CL=30pF 10 – 100 MHz Standard drive, (-1), All outputs CL=15pf 10 – 100 MHz Standard drive, (-1), All outputs CL=30pf 10 – 66 MHz High drive (-1H). All outputs CL=15pF 0 – 140 MHz High drive (-1H), All outputs CL=30pF 0 – 100 MHz Standard drive, (-1), All outputs CL=15pf 0 – 100 MHz Standard drive, (-1), All outputs CL=30pf 0 – 66 MHz Measured at 1.4V, Fout=66MHz, CL=15pF 30 50 70 % Cycle[2] Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % OUTDC2 Output Duty Cycle[2] Measured at 1.4V, Fout=66MHz, CL=15pF 40 50 60 % OUTDC1 Output Duty Rev 2.0, May 12, 2008 Page 6 of 12 SL2309 Rise, Fall Time (3.3V) [2] (Measured at: 0.8 to 2.0V) High drive (-1H), CL=15pF – – 1.5 ns High drive (-1H), CL=30pF – – 1.8 ns Standard drive (-1), CL=15pF – – 2.2 ns Standard drive (-1), CL=30pF – – 2.5 ns N ot fo R r N ec o ew m m D e es nd ig e ns d tr/f t1 Output-to-Output Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 70 150 ps t2 Product-to-Product Skew[2] (Measured at VDD/2) All outputs CL=0 or equally loaded, -1 or -1H drives – 180 400 ps t3 Delay Time, CLKIN Rising Edge to CLKOUT Rising Edge[2] (Measured at VDD/2) PLL Bypass mode Only when S2=1 and S1=0 1.5 5 8.7 ns –220 – 220 ps tPLOCK PLL Lock Time[2] Time from 90% of VDD to valid clocks on all the output clocks – – 1.0 ms CCJ Cycle-to-cycle Jitter [2] Fin=Fout=66 MHz,