SL23EP09ZC-1H

SL23EP09 Not Recommended for New Designs Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock skew: 45ps-typ Low output clock jitter:  50 ps-typ cycle-to-cycle jitter  20 ps-typ period jitter Low part-to-part output skew: 90 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation:  26 mA-max at 66 MHz and VDD=3.3 V  24 mA-max at 66 MHz and VDD=2.5V One input drives 9 outputs organized as 4+4+1 Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Standard and High-Drive options Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades The SL23EP09 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. N ot fo R r N ec o ew m m D e es nd ig e ns d    Description          Applications     The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP09 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. Benefits   Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embeded Systems   Up to nine (9) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Low Power and Low Jitter PLL MUX CLKOUT CLKIN CLKA1 CLKA2 CLKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 2.0, May 12, 2008 2400 West Cesar Chavez, Austin, TX 78701 Page 1 of 14 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com SL23EP09 Pin Configuration 1 16 CLKOUT CLKA1 2 15 CLKA2 3 14 CLKA4 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB2 7 10 CLKB4 CLKB3 S2 8 9 S1 N ot fo R r N ec o ew m m D e es nd ig e ns d CLKIN 16-Pin SOIC and TSSOP Pin Description Pin Number Pin Name Pin Type Pin Description 1 CLKIN Input 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 4 VDD Power 3.3V or 2.5V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 8 S2 Input Select Input, select pin S2. Weak pull-up (250kΩ). 9 S1 Input Select Input, select pin S1. Weak pull-up (250kΩ). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250kΩ). 12 GND Power Power Ground. 13 VDD Power 3.3V or 2.5V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250kΩ). 16 CLKOUT Output Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250kΩ). Rev 2.0, May 12, 2008 Reference Frequency Clock Input. Weak pull-down (250kΩ). Page 2 of 14 SL23EP09 General Description Select Input Control The SL23EP09 is a low skew, low jitter Zero Delay Buffer with very low operating current. The SL23EP09 provides two (2) input select control pins called S1 and S2. This feature enables users to selects various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. N ot fo R r N ec o ew m m D e es nd ig e ns d The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and output Frequency Range The input and output frequency range is the same. But, it depends on VDD and drive levels as given in the below Table 1. VDD(V) Drive Min(MHz) Max(MHz) 3.3 HIGH 10 220 3.3 STD 10 200 2.5 HIGH 10 180 2.5 STD 10 167 Table 1. Input/Output Frequency Range The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak pull-up resistors to VDD. PLL Bypass Mode If the S2 and S1 pins are logic High(1) and Low(0) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven directly from the reference input clock. In this operation mode SL23EP09 works like a non-ZDB fanout buffer. High and Low-Drive Product Options The SL23EP09 is offered with High-Drive “-1H” and Standard-Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. Skew and Zero Delay If the input clock frequency is DC (GND to VDD), this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 μA supply current. All outputs should drive the similar load to achieve output-tooutput skew and input-to-output specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. SpreadThru™ Feature Power Supply Range (VDD) If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP09 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency The SL23EP09 is designed to operate in a wide power supply range from 2.3V (Min) to 3.6V (Max). An internal onchip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL09. Rev 2.0, May 12, 2008 Page 3 of 14 SL23EP09 S1 Clock A1-A4 Clock B1-4 CLKOUT Output Source PLL Status 0 0 Tri-state Tri-state Driven PLL On 0 1 Driven Tri-state Driven PLL On N ot fo R r N ec o ew m m D e es nd ig e ns d S2 1 0 Driven Driven Driven Reference Off 1 1 Driven Driven Driven PLL On Table 2. Select Input Decoding CLKIN Input to CLKA or CLKB Delay (ps) 1500 1000 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load – CLKA or CLKB Load (pF) Figure 1. CLKIN Input to CLK A and B Delay (In terms of load difference between CLKOUT and CLK A and B) Rev 2.0, May 12, 2008 Page 4 of 14 SL23EP09 Absolute Maximum Ratings Condition Min. Max. Unit Supply voltage, VDD – 0.5 4.6 V All Inputs and Outputs – 0.5 VDD+0.5 V N ot fo R r N ec o ew m m D e es nd ig e ns d Description Ambient Operating Temperature In operation, C-Grade 0 70 °C Ambient Operating Temperature In operation, I-Grade – 40 85 °C Storage Temperature No power is applied – 65 150 °C Junction Temperature In operation, power is applied – 125 °C – 260 °C Soldering Temperature ESD Rating (Human Body Model) JEDECCC22-A114D -4000 4000 V ESD Rating (Change Device Model) JEDECCC22-C101C -1500 1500 V ESD Rating (Machine Model) JEDECCC22-A115D -200 200 V Rev 2.0, May 12, 2008 Page 5 of 14 SL23EP09 Operating Conditions: Unless Otherwise Stated VDD=2.3V to 3.6V and for Both C and I Grades Symbol Description Condition Min. Max. Unit 3.3V Supply Voltage 3.3V+/-10% 3.0 3.6 V VDD2.5 2.5V Supply Voltage 2.5V+/-10% 2.3 2.7 V TA Operating Temperature(Ambient) Commercial 0 70 °C –40 85 °C